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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2001)
San Francisco, California
Oct. 24, 2001 to Oct. 26, 2001
ISBN: 0-7695-1203-8
pp: 0357
T.M. Mak , Intel Corporation
B. Ricco' , University of Bologna
S. Di Francescantonio , University of Bologna
C. Metra , University of Bologna
ABSTRACT
Starting from the analysis of real process data and considering, as a reference, an Intel microprocessor, we evaluate the fault models that better describe the manufacturing defects that are most likely to affect signals of the clock distribution network. The probability of these faults has been estimated by means of Inductive Fault Analysis (IFA) and has been found to be, for the majority of cases, comparable if not one order of magnitude higher than that of other most likely microprocessor faults. The effects of the most likely clocks' faults has then been analyzed by means of electrical level simulations. Differently from what generally implicitly assumed, we have found that only a small percentage of these faults results in a catastrophic failure of the microprocessor, thus being possibly easily detectable during manufacturing test, while the majority results in a local failure, which can not be detected during manufacturing test, although compromising the microprocessor correct operation and causing an unacceptable decrease of its reliability.
INDEX TERMS
Clock distribution network, clock faults, testing, microprocessor
CITATION
T.M. Mak, B. Ricco', S. Di Francescantonio, C. Metra, "Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects", 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), vol. 00, no. , pp. 0357, 2001, doi:10.1109/DFTVS.2001.966789
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