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Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2000)
Yamanashi, Japan
Oct. 25, 2000 to Oct. 27, 2000
ISSN: 1063-6722
ISBN: 0-7695-0719-0
TABLE OF CONTENTS
Session 1: Yield Analysis and Modeling

The Effect of Placement on Yield for Standard Cell Designs (Abstract)

Rajnish K. Prasad , University of Massachusetts at Amherst
Israel Koren , University of Massachusetts at Amherst
pp. 3

IC Critical Volume Calculation through Ray-Casting of CSG Trees (Abstract)

Mike Moran , University of Edinburgh
Gerard A. Allan , University of Edinburgh
pp. 12

A New Defect Outline Model Used for Critical Area Estimation in VLSI (Abstract)

Xiaohong Jiang , Japan Advanced Institute of Science and Technology
Susumu Horiguchi , Japan Advanced Institute of Science and Technology
Yue Hao , Xidian University
pp. 21

Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core (Abstract)

Fred J. Meyer , Northeastern University
Nohpill Park , Oklahoma State University
pp. 30
Session 2: Yield Enhancement Techniques

VLSI Yield Optimization Based on the Sub-Processing-Element Level Redundancy (Abstract)

Yongchang Jiao , Xidian University
Tianxu Zhao , Xidian University
Yue Hao , Xidian University
pp. 41

Quality-Effective Repair of Multichip Module Systems (Abstract)

F. Meyer , Northeastern University
N. Park , Oklahoma State University
F. Lombardi , Northeastern University
pp. 47

A Self-Correcting Active Pixel Camera (Abstract)

Glenn Chapman , Simon Fraser University
Israel Koren , University of Massachusetts at Amherst
Zahava Koren , University of Massachusetts at Amherst
pp. 56
Session 3: Wafer Scale/Large Area Systems

Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications (Abstract)

Klaus Herrmann , University of Hannover
Michael Redeker , University of Hannover
Ole Mende , University of Hannover
Dieter Treytnar , University of Hannover
Markus Rudack , University of Hannover
pp. 78

Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model (Abstract)

Susumu Horiguchi , Japan Advanced Institute of Science and Technology
Xiaohong Jiang , Japan Advanced Institute of Science and Technology
pp. 96

Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit (Abstract)

Klaus Herrmann , University of Hannover
Jörg Hilgenstock , University of Hannover
Peter Pirsch , University of Hannover
Sören Moch , University of Hannover
pp. 105

A Multifunctional Laser Linking and Cutting Structure for Standard 0.25 ?m CMOS-Technology (Abstract)

Dieter Treytnar , University of Hannover
Markus Rudack , University of Hannover
Ole Mende , University of Hannover
Michael Redeker , University of Hannover
pp. 114
Session 4: Fault-Tolerant Interconnections

On the Complexity of Switch Programming in Fault-Tolerant Configurable Chips (Abstract)

F. Lombardi , Northeastern University
W. Shi , University of North Texas
K. Kumar , Northeastern University
pp. 125

Design of a Fault Tolerant Multistage Interconnection Network with Parallel Duplicated Switches (Abstract)

Naotake Kamiura , Himeji Institute of Technology
Takashi Kodera , Himeji Institute of Technology
Nobuyuki Matsui , Himeji Institute of Technology
pp. 143
Session 5: Fault-Tolerant Systems

Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs (Abstract)

Monica Alderighi , Consiglio Nazionale delle Ricerche
Sergio D'Angelo , Consiglio Nazionale delle Ricerche
Giacomo R. Sechi , Consiglio Nazionale delle Ricerche
Cecilia Metra , Universita' di Bologna
pp. 155

Fault-Tolerant High-Performance Cordic Processors (Abstract)

Jae-Hyuck Kwak , University of Texas at Austin
Vincenzo Piuri , Politecnico di Milano
Earl E. Swartzlander, Jr. , University of Texas at Austin
pp. 164

A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture (Abstract)

P. Marinucci , Consortium ULISSE
A. Salsano , University of Rome ?Tor Vergata?
M. Ottavi , Consortium ULISSE
G.C. Cardarilli , University of Rome ?Tor Vergata?
pp. 173
Session 6: Error Coding

Evaluations of Burst Error Recovery for VF Arithmetic Coding (Abstract)

Masato Kitakami , Chiba University
Eiji Fujiwara , Tokyo Institute of Technology
Hongyuan Chen , Tokyo Institute of Technology
pp. 183

Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs (Abstract)

Yasunao Katayama , IBM Research, Tokyo Research Laboratory
Sumio Morioka , IBM Research, Tokyo Research Laboratory
Yasushi Negishi , IBM Research, Tokyo Research Laboratory
pp. 201
Session 7: Reconfiguration and Repair

Self-Repairing in a Micro-Programmed Processor for Dependable Applications (Abstract)

S. Chiusano , Politecnico di Torino
P. Prinetto , Politecnico di Torino
P. Simonotti , Politecnico di Torino
A. Benso , Politecnico di Torino
G. Ugo , Politecnico di Torino
pp. 231
Session 8: Online Testing

How Does Resource Utilization Affect Fault Tolerance? (Abstract)

Christoph Scherrer , Vienna University of Technology
Andreas Steininger , Vienna University of Technology
pp. 251

Synthesis of On-Line Testing Control Units: Flow Graph Coding/Monitoring Approach (Abstract)

Eugene M. Levine , Rainbow Technologies Inc.
Vincenzo Piuri , Politecnico di Milano
Serge N. Demidenko , Massey University
pp. 266

An On-Line Reconfigurable FPGA Architecture (Abstract)

A. Walker , University of Tennessee
P.K. Lala , University of Arkansas
pp. 275
Session 9: Built-In Self-Test

Test Cost Minimization for Hybrid Bist (Abstract)

Raimund Ubar , Tallinn Technical University
Zebo Peng , Link?ping University
Gert Jervan , Link?ping University
pp. 283

BIST Architectures Selection Based on Behavioral Testing (Abstract)

D. Sciuto , Politecnico di Milano
G. Biasoli , Politecnico di Milano
F. Fummi , Universit? di Verona
F. Ferrandi , Politecnico di Milano
A. Fin , Universit? di Verona
pp. 292

BRAINS: A BIST Compiler for Embedded Memories (Abstract)

Cheng-Wen Wu , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Chen-Jong Wey , Global UniChip Corp.
Chuang Cheng , National Tsing Hua University
Ming-Chang Tsai , Global UniChip Corp.
Jing-Reng Huang , National Tsing Hua University
pp. 299
Session 10: Testing Strategies

Testing the Configurability of Dynamic FPGAs (Abstract)

N. Park , Oklahoma State University
F. Lombardi , Northeastern University
S.J. Ruiwale , Northeastern University
pp. 311

Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits (Abstract)

J.S. Wang , National Chung Cheng University
W.B. Jone , New Mexico Tech
C.H. Cheng , National Chung Cheng University
S.C. Chang , National Chung Cheng University
pp. 329

Path Delay Fault Testability Analysis (Abstract)

Tomasz Bech , Warsaw University of Technology
Janusz Sosnowski , Warsaw University of Technology
Tomasz Wabia , Warsaw University of Technology
pp. 338
Session 11: IDDQ Testing

Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families (Abstract)

Madhuban Kishor , Indian Institute of Technology at New Delhi
José Pineda de Gyvez , Philips Research
pp. 349

A New Light-Based Logic IC Screening Method (Abstract)

Michinori Nishihara , IBM Japan Ltd.
Shigeru Ohnishi , IBM Japan Ltd.
pp. 358

Testability Analysis of IDDQ Testing with Large Threshold Value (Abstract)

Masashi Takeda , University of Tokushima
Masaki Hashizume , University of Tokushima
Takeomi Tamesada , University of Tokushima
Hiroyuki Yotsuyanagi , University of Tokushima
pp. 367

The 2nd Order Analysis of IDDQ Test Data (Abstract)

Jien-Chung Lo , University of Rhode Island
Shengli Li , University of Rhode Island
Kai Zhang , University of Rhode Island
pp. 376
Session 12: Fault Injection

'BOND': An Interposition Agents Based Fault Injector for Windows NT (Abstract)

Paolo Prinetto , Politecnico di Torino
Alfredo Benso , Politecnico di Torino
Silvia Chiusano , Politecnico di Torino
Andrea Baldini , Politecnico di Torino
pp. 387

A Prototype of a VHDL-Based Fault Injection Tool (Abstract)

P.J. Gil , Universidad Polit?cnica de Valencia
D. Gil , Universidad Polit?cnica de Valencia
J. C. Baraza , Universidad Polit?cnica de Valencia
J. Gracia , Universidad Polit?cnica de Valencia
pp. 396

Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes (Abstract)

Béla Fehér , Budapest University of Technology and Economics
Régis Leveugle , TIMA Laboratory
Lörinc Antoni , TIMA Laboratory and Budapest University of Technology and Economics
pp. 405

Author Index (PDF)

pp. 421
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