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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (1999)
Albuquerque, New Mexico
Nov. 1, 1999 to Nov. 3, 1999
ISSN: 1063-6722
ISBN: 0-7695-0325-X
TABLE OF CONTENTS

Organizers (PDF)

pp. xii
Keynote Address
Session 1: Yield I

Determination of Yield Bounds Prior to Routing (Abstract)

Israel Koren , University of Massachusetts at Amherst
pp. 4

Impact of Simulation Parameters on Critical Area Analysis (Abstract)

Julie Segal , HPL Incorporated
Ron Ross , Texas Instruments
Sergei Bakarian , HPL Incorporated
pp. 14
Session 2: Yield II

Creating 35 mm Camera Active Pixel Sensors (Abstract)

Glenn Chapman , Simon Fraser University
Yves Audet , Mitel Semiconductor
pp. 22
Session 3: Testing Techniques

8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects (Abstract)

James F. Plusquellic , University of Maryland at Baltimore County
Amy Germida , University of Maryland at Baltimore County
Zheng Yan , University of Maryland at Baltimore County
pp. 68

Charge Sharing Fault Detection for CMOS Domino Logic Circuits (Abstract)

W.B. Jone , National Chung Cheng University
C.H. Cheng , National Chung Cheng University
J.S. Wang , National Chung Cheng University
S.C. Chang , National Chung Cheng University
pp. 77

Testing for Path Delay Faults Using Test Points (Abstract)

N. Denny , University of Arizona
S. Tragoudas , University of Arizona
pp. 86

Low-Cost Test for Large Analog IC's (Abstract)

Sule Ozev , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 101
Session 4: Built-In Self-Test Architectures

Novel Control Pattern Generators for Interconnect Testing with Boundary Scan (Abstract)

Fred J. Meyer , Northeastern University
Wenyi Feng , Lucent Technologies
Fabrizio Lombardi , Northeastern University
pp. 112

Low Power Dissipation in BIST Schemes for Modified Booth Multipliers (Abstract)

D. Bakalis , University of Patras and Computer Technology Institute
G.Ph. Alexiou , University of Patras and Computer Technology Institute
X. Kavousianos , University of Patras
D. Nikolos , University of Patras and Computer Technology Institute
H.T. Vergos , University of Patras and Computer Technology Institute
pp. 121

LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles (Abstract)

Dimitri Kagaris , Southern Illinois University
Spyros Tragoudas , University of Arizona
pp. 130

Power Characterization of LFSRs (Abstract)

Marco Brazzarola , Universit? di Verona
Franco Fummi , Universit? di Verona
pp. 139
Session 5: Fault Modeling and Simulation

Failure Tests on 64 Mb SDRAM in Radiation Environment (Abstract)

S. Sperandei , U.L.I.S.S.E. Consortium
M. Ricci , Istituto Nazionale di Fisica Nucleare, Laboratori Nazionali
G.C. Cardarilli , University of Rome "Tor Vergata"
G.C. Grande , U.L.I.S.S.E. Consortium
D. de Francesco , Istituto Nazionale di Fisica Nucleare
P.G. Picozza , Istituto Nazionale di Fisica Nucleare
V. Bidoli , Istituto Nazionale di Fisica Nucleare
P. Marinucci , U.L.I.S.S.E. Consortium
D. Di Giovenale , U.L.I.S.S.E. Consortium
S. Bertazzoni , University of Rome "Tor Vergata"
D. Piergentili , University of Rome "Tor Vergata"
S. Bartalucci , Istituto Nazionale di Fisica Nucleare, Laboratori Nazionali
M. Salmeri , University of Rome "Tor Vergata"
A. Rovelli , Istituto Nazionale di Fisica Nucleare, Laboratori Nazionali del Sud
A. Salsano , University of Rome "Tor Vergata"
G. Mazzenga , Istituto Nazionale di Fisica Nucleare, Laboratori Nazionali
pp. 158

RAMSES: A Fast Memory Fault Simulator (Abstract)

Chi-Feng Wu , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 165

Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information (Abstract)

Donatella Sciuto , Politecnico di Milano
Marco Brera , Politecnico di Milano
Franco Fummi , Universit? di Verona
Fabrizio Ferrandi , Politecnico di Milano
pp. 174

Fast Signature Simulation for PPSFP Simulators (Abstract)

Firas Khadour , University of Alberta
Xiaoling Sun , University of Alberta
pp. 181
Session 6: Design for Testing

Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield (Abstract)

F. Lombardi , Northeastern University
N. Park , Oklahoma State University
pp. 192

Testable and Fault Tolerant Design for FFT Networks (Abstract)

Cheng-Wen Wu , National Tsing Hua University
Jin-Fu Li , National Tsing Hua University
pp. 201

Soft-Error Detection through Software Fault-Tolerance Techniques (Abstract)

Marco Torchiano , Politecnico di Torino
Maurizio Rebaudengo , Politecnico di Torino
Massimo Violante , Politecnico di Torino
Matteo Sonza Reorda , Politecnico di Torino
pp. 210

Optimal Vector Selection for Low Power BIST (Abstract)

Fulvio Corno , Politecnico di Torino
Massimo Violante , Politecnico di Torino
Matteo Sonza Reorda , Politecnico di Torino
Maurizio Rebaudengo , Politecnico di Torino
pp. 219

A Structural Approach for Space Compaction for Sequential Circuits (Abstract)

M. Gössel , University of Potsdam
M. Seuring , University of Potsdam
pp. 227
Session 7: Self-Checking Processing Units and Systems

A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs (Abstract)

A. Walker , University of Tennessee at Knoxville
A. Singh , University of South Florida at Tampa
P.K. Lala , University of South Florida at Tampa
pp. 238

A Synthesis Methodology Aimed at Improving the Quality of TSC Devices (Abstract)

F. Salice , Politecnico di Milano and CEFRIEL
D. Sciuto , Politecnico di Milano
L. Pomante , Politecnico di Milano
C. Bolchini , Politecnico di Milano
pp. 247

Power Consumption in Fast Dividers Using Time Shared TMR (Abstract)

Earl E. Swartzlander, Jr. , University of Texas at Austin
W. Lynn Gallagher , University of Texas at Austin
pp. 256

Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors (Abstract)

Earl E. Swartzlander, Jr. , University of Texas at Austin
Vincenzo Piuri , Politecnico di Milano
pp. 265

Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs (Abstract)

Giacomo R. Sechi , Istituto di Fisica Cosmica
Vincenzo Piuri , Politecnico di Milano
Sergio D'Angelo , Istituto di Fisica Cosmica
Monica Alderighi , Istituto di Fisica Cosmica
pp. 274
Session 8: Self-Checking Memories and Interconnections

Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability (Abstract)

Eiji Fujiwara , Tokyo Institue of Technology
Haruhiko Kaneko , Tokyo Institue of Technology
Kiattichai Saowapa , Tokyo Institue of Technology
pp. 284

Erasure Error Correction with Hardware Detection (Abstract)

William D. Armitage , Rhode Island College
Jien-Chung Lo , The University of Rhode Island
pp. 293

Design of Fault-Tolerant Solid State Mass Memory (Abstract)

A. Salsano , University of Rome "Tor Vergata"
M. Salmeri , University of Rome "Tor Vergata"
P. Marinucci , Consortium ULISSE
S. Bertazzoni , University of Rome "Tor Vergata"
G.C. Cardarilli , University of Rome "Tor Vergata"
pp. 302

Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention (Abstract)

Sumio Morioka , IBM Research, Tokyo Research Laboratory
Zhao Wu , IBM Research, Tokyo Research Laboratory
Eric J. Stuckey , IBM Research, Tokyo Research Laboratory
Yasunao Katayama , IBM Research, Tokyo Research Laboratory
pp. 311
Session 9: Diagnosis

Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems (Abstract)

Cecilia Metra , University of Bologna
Sergio D'Angelo , IFC - Consiglio Nazionale delle Ricerche
Giacomo Sechi , IFC - Consiglio Nazionale delle Ricerche
pp. 330

A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths (Abstract)

Alex Orailoglu , University of California at San Diego
Yiorgos Makris , University of California at San Diego
pp. 339

Good Processor Identification in Two-Dimensional Grids (Abstract)

Fabrizio Lombardi , Northeastern University
Fred J. Meyer , Northeastern University
Jun Zhao , Lucent Technologies
pp. 348
Session 10: Reconfiguration

Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources (Abstract)

Fred J. Meyer , Northeastern University
Wenyi Feng , Lucent Technologies
Xiaotao Chen , Lucent Technologies
Fabrizio Lombardi , Northeastern University
pp. 368

Defect and Fault Tolerance FPGAs by Shifting the Configuration Data (Abstract)

Abderrahim Doumar , Chiba University
Satoshi Kaneko , Chiba University
Hideo Ito , Chiba University
pp. 377

Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures (Abstract)

William H. Mangione-Smith , University of California at Los Angeles
John Lach , University of California at Los Angeles
Miodrag Potkonjak , University of California at Los Angeles
pp. 386

Reconfiguration of Two-Dimensional Meshes Embedded in Faulty Hypercubes (Abstract)

Naotake Kamiura , Himeji Institute of Technology
Yutaka Hata , Himeji Institute of Technology
Sumito Nakano , Himeji Institute of Technology
Nobuyuki Matsui , Himeji Institute of Technology
pp. 395

Author Index (PDF)

pp. 404
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