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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (1998)
Austin, Texas
Nov. 2, 1998 to Nov. 4, 1998
ISSN: 1063-6722
ISBN: 0-8186-8832-7
TABLE OF CONTENTS
Keynote Address
Session 1: Yield and Defect Density
Session 2: Layout and Critical Area

Yield and Routing Objectives in Floorplanning (Abstract)

Zahava Koren , University of Massachusetts
Israel Koren , University of Massachusetts
pp. 28

Orphan Metal Removal as an Element of DFM (Abstract)

Neil Harrison , Philips Semiconductors
pp. 37
Invited Presentation
Session 3: Reliability Enhancement

Process Variations and their Impact on Circuit Operation (Abstract)

Melvin A. Breuer , University of Southern California
Suriyaprakash Natarajan , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 73
Session 4: Defect and Fault Analysis

Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits (Abstract)

D. Racz , Royal Military College of Canada
S. Adham , Royal Military College of Canada
D. Al-Khalili , Royal Military College of Canada
M. Hossain , Royal Military College of Canada
C. Rozon , Royal Military College of Canada
pp. 84

Characterization of CMOS Defects using Transient Signal Analysis (Abstract)

James F. Plusquellic , University of Maryland
Steven P. Levitan , University of Pittsburgh
Donald M. Chiarulli , University of Pittsburgh
pp. 93

Functional Verification Coverage vs. Physical Stuck-at Fault Coverage (Abstract)

Xiao Sun , Applied Micro Circuits Corporation
Carmie Hull , Applied Micro Circuits Corporation
pp. 108

An Integrated HW and SW Fault Injection Environment for Real-Time Systems (Abstract)

M. Sonza Reorda , Politecnico di Torino
A. Benso , Politecnico di Torino
P.L. Civera , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
pp. 117
Panel Session: Fault Tolerance
Session 5: Testing Techniques

Increasing Current Testing Resolution (Abstract)

Claude Thibeault , ?cole de Technologie Sup?rieure
pp. 126
Session 6: Testing of Regular Structures

A New Method for Testing EEPLA's (Abstract)

Fabrizio Lombardi , Northeastern University
Fred J. Meyer , Texas A&M University
Avinash Munshi , Texas A&M University
pp. 146

C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications (Abstract)

T. Haniotakis , University of Patras
D. Nikolos , University of Patras
Y. Tsiatouhas , University of Athens
pp. 155

On the Complexity of Sequential Testing in Configurable FPGAs (Abstract)

Fabrizio Lombardi , Northeastern University
Fred J. Meyer , Texas A&M University
Wenyi Feng , Texas A&M University
Wei Kang Huang , Fudan University
pp. 164
Session 7: Concurrent Testing Techniques

Challenges of Built-In Current Sensor Designs (Abstract)

Jien-Chung Lo , The University of Rhode Island
Yu-Yau Guo , The University of Rhode Island
pp. 192
Session 8: Fault Diagnosis

On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis (Abstract)

Luc Boisvert , CAE ELECTRONIQUE LTEE
Claude Thibeault , ?cole de Technologie Sup?rieure
pp. 202

A Systematic Approach for Diagnosing Multiple Delay Faults (Abstract)

Nur A. Touba , University of Texas at Austin
Jayabrata Ghosh Dastidar , University of Texas at Austin
pp. 211

Diagnosis of Scan Chain Failures (Abstract)

Yuejian Wu , Nortern Telecom
pp. 217
Session 9: Fault-Tolerant Designs I

Error-Correcting Goldschmidt Dividers Using Time Shared TMR (Abstract)

W. Lynn Gallagher , The University of Texas at Austin
Earl E. Swartzlander, Jr. , The University of Texas at Austin
pp. 224

Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure (Abstract)

Yvon Savaria , Ecole Polytechnique de Montr?al
Steve Masson , Universit? du Qu?bec ? Chicoutimi
Daniel Audet , Universit? du Qu?bec ? Chicoutimi
pp. 241
Session 10: Fault-Tolerant Designs II

Transient and Intermittent Fault Recovery without Rollback (Abstract)

Samuel Norman Hamilton , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 252

Self-Reconfiguration Scheme of 3D-Mesh Arrays (Abstract)

Susumu Horiguchi , Japan Advanced Institute of Science and Technology
Issei Numata , Japan Advanced Institute of Science and Technology
pp. 276
Session 11: High-Level Synthesis of Reliable Systems

A System for Evaluating On-Line Testability at the RT-level (Abstract)

S. Chiusano , Politecnico di Torino
R. Vietti , Politecnico di Torino
F. Corno , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
pp. 284

High-level Synthesis of Data Paths with Concurrent Error Detection (Abstract)

Anna Antola , Politecnico di Milano
Mariagiovanna Sami , Politecnico di Milano
Vincenzo Piuri , Politecnico di Milano
pp. 292

Graceful Degradation in Synthesis of VLSI ICs (Abstract)

Alex Orailoglu , University of California at San Diego
pp. 301

Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis (Abstract)

M. Broglia , Politecnico di Milano
M.G. Sami , Politecnico di Milano
G. Buonanno , Politecnico di Milano
M. Selvini , Politecnico di Milano
pp. 312

High-Level BIST Synthesis for Delay Testing (Abstract)

Paul Y.S. Cheung , The University of Hong Kong
Xiaowei Li , The University of Hong Kong
pp. 318
Session 12: Yield and Reliability Issues of Analog and Mixed Signal Circuits

Specification-Driven Test Design for Analog Circuits (Abstract)

Pramodchandran N. Variyam , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 335

Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by Severity (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta.
Alfred V. Gomes , Georgia Institute of Technology, Atlanta.
Ramakrishna Voorakaranam , Georgia Institute of Technology, Atlanta.
pp. 341

BIST Module for Mixed-Signal Circuits (Abstract)

V. Yarmolik , Belarusian State University of Informatics and Radio Electronics
S. Demidenko , Singapore Polytechnic and National Academy of Sciences of Belarus
A. Shmidman , Belarusian State University of Informatics and Radio Electronics
V. Piuri , Politecnico di Milano
pp. 349

Author Index (PDF)

pp. 355
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