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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (1997)
Paris, FRANCE
Oct. 20, 1997 to Oct. 22, 1997
ISSN: 1063-6722
ISBN: 0-8186-8168-3
TABLE OF CONTENTS
Session 1: Critical Area

Improved Yield Model for Submicron Domain (Abstract)

Wojciech Maly , Carnegie Mellon University
Witold A. Pleskacz , Warsaw University of Technology
pp. 2

Application of a yield model merging critical areas and defectivity to industrial products (Abstract)

F. Duvivier , Central R&D, SGS-Thomson Microelectron., Crolles, France
S. Levasseur , Central R&D, SGS-Thomson Microelectron., Crolles, France
pp. 11

Efficient critical area estimation for arbitrary defect shapes (Abstract)

G.A. Allan , Dept. of Electr. Eng., Edinburgh Univ., UK
A.J. Walton , Dept. of Electr. Eng., Edinburgh Univ., UK
pp. 20

Crosstalk Minimization in Three-Layer HVH Channel Routing (Abstract)

Zhan Chen , University of Massachusetts, Amherst
Israel Koren , University of Massachusetts, Amherst
pp. 38
Session 2: Yield Management

An examination of empirically derived within-die local probabilities of failure (Abstract)

R. Harris , KLA-Tencor, Milpitas, CA, USA
S. Hall , KLA-Tencor, Milpitas, CA, USA
A. Gandhi , KLA-Tencor, Milpitas, CA, USA
pp. 53

Detection of Yield Trends (Abstract)

Witold A. Pleskacz , Warsaw University of Technology
Hans T. Heineken , Level One Communications
Wojciech Maly , Carnegie Mellon University
pp. 62

A Statistical Approach To Identify Semiconductor Process Equipment Related Yield Problems (Abstract)

Allan Y. Wong , Yield Management Consulting KLA-Tencor Corporation
pp. 69
Session 3: Test and Test Generation

Testing of programmable logic devices (PLD) with faulty resources (Abstract)

N. Park , Intel Corp., Santa Clara, CA, USA
F.J. Meyer , Intel Corp., Santa Clara, CA, USA
D.G. Ashen , Intel Corp., Santa Clara, CA, USA
F. Lombardi , Intel Corp., Santa Clara, CA, USA
pp. 76

Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays (Abstract)

F. Fummi , Politecnico di Milano
L. Pozzi , Politecnico di Milano
F. Ferrandi , Politecnico di Milano
M.G. Sami , Politecnico di Milano
pp. 85

Concurrent testing of VLSI digital signal processors using mutation based testing (Abstract)

C. Aktouf , LCIS-ESISAR, Valence, France
C. Robach , LCIS-ESISAR, Valence, France
G. Al-Hayek , LCIS-ESISAR, Valence, France
pp. 94
Panel Session
Session 4: Self Checking and Coding

Fast and area-time efficient Berger code checkers (Abstract)

Jien-Chung Lo , Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
Yu-Yau Guo , Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
C. Metra , Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
pp. 110

Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes (Abstract)

G. Sidiropoulos , University of Patras
X. Kavousianos , University of Patras
D. Nikolos , University of Patras
pp. 128

Compact and low power on-line self-testing voting scheme (Abstract)

M. Favalli , Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
C. Metra , Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
B. Ricco , Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 137
Session 5: Cost Modeling

A Cost Model for VLSI / MCM Systems (Abstract)

Michel Kafrouni , ?cole de Technologie Sup?rieure
Claude Thibeault , ?cole de Technologie Sup?rieure
pp. 148

Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model (Abstract)

Y. Gagnon , Dept. de Genie Phys., Ecole Polytech. de Montreal, Que., Canada
C. Thibeault , Dept. de Genie Phys., Ecole Polytech. de Montreal, Que., Canada
Y. Savaria , Dept. de Genie Phys., Ecole Polytech. de Montreal, Que., Canada
M. Meunier , Dept. de Genie Phys., Ecole Polytech. de Montreal, Que., Canada
pp. 157

Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs (Abstract)

Zahava Koren , University of Massachusetts
Israel Koren , University of Massachusetts
pp. 166

Validating fault tolerant designs using laser fault injection (LFI) (Abstract)

F. Falquez , Space & Strategic Syst. Operation, Honeywell Inc., USA
W. Moreno , Space & Strategic Syst. Operation, Honeywell Inc., USA
J.R. Samson, Jr. , Space & Strategic Syst. Operation, Honeywell Inc., USA
pp. 175
Session 6: Fault Tolerance

Multiple fault detection in logic resources of FPGAs (Abstract)

Wei Liang Huang , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
F. Lombardi , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
F.J. Meyer , Dept. of Electron. Eng., Fudan Univ., Shanghai, China
pp. 186

Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities (Abstract)

X. Wendling , Institut National Polytechnique de Grenoble / CSI
R. Leveugle , Institut National Polytechnique de Grenoble / CSI
L. Reveret , Institut National Polytechnique de Grenoble / CSI
R. Rochet , Institut National Polytechnique de Grenoble / CSI
H. Chauvet , Institut National Polytechnique de Grenoble / CSI
pp. 195

Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks (Abstract)

R. Stefanelli , Politecnico di Milano
M. Cozzini , Politecnico di Milano
G. Buonanno , Politecnico di Milano
D. Sciuto , Politecnico di Milano
C. Bolchini , Politecnico di Milano
pp. 204

Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments (Abstract)

M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
A. Benso , Politecnico di Torino
R. Ubar , Tallinn Technical University
P. Prinetto , Politecnico di Torino
J. Raik , Tallinn Technical University
pp. 212
Session 7: Fault Tolerance II

Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits (Abstract)

T. Horita , Dept. of Comput. Sci., Iwate Univ., Morioka, Japan
I. Takanami , Dept. of Comput. Sci., Iwate Univ., Morioka, Japan
pp. 218
Session 8: Error Recovery

Low-level error recovery mechanism for self-checking sequential circuits (Abstract)

C. Metra , Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
M. Favalli , Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 234

Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR (Abstract)

Earl E. Swartzlander, Jr. , The University of Texas at Austin
W. Lynn Gallagher , The University of Texas at Austin
pp. 243

Error Identification and Data Recovery in MISR-based Data Compaction (Abstract)

Wes Tutak , University of Alberta
Xiaoling Sun , University of Alberta
pp. 252

Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance (Abstract)

F. Distante , Informazione Politecnico di Milano
M. G. Sami , Informazione Politecnico di Milano
R. Stefanelli , Informazione Politecnico di Milano
pp. 261
Session 9: Error Detection

An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring (Abstract)

A.P. Henry , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
P.K. Lala , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
A. Walker , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
pp. 272

An IDDQ Sensor for Concurrent Timing Error Detection (Abstract)

Christopher G. Knight , Auburn University
Victor P. Nelson , Auburn University
Adit D. Singh , Auburn University
pp. 281

Designing Networks with Error Detection Properties through the Fault-Error Relation (Abstract)

C. Bolchini , Politecnico di Milano
F. Salice , CEFRIEL
D. Sciuto , Politecnico di Milano
pp. 290

Semi-Concurrent Error Detection in Data Paths (Abstract)

Vincenzo Piuri , Politecnico di Milano
Anna Antola , Politecnico di Milano
Mariagiovanna Sami , Politecnico di Milano
pp. 298

Author Index (PDF)

pp. 313
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