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Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (1996)
Boston, MA
Nov. 6, 1996 to Nov. 8, 1996
ISSN: 1063-6722
ISBN: 0-8186-7545-4
TABLE OF CONTENTS
Session 1: Defect Avoidance

The Teramac Custom Computer: Extending the Limits with Defect Tolerance (Abstract)

W.B. Culbertson , Hewlett-Packard Laboratories
R. Amerson , Hewlett-Packard Laboratories
R.J. Carter , Hewlett-Packard Laboratories
P. Kuekes , Hewlett-Packard Laboratories
G. Snider , Hewlett-Packard Laboratories
pp. 2

Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arrays (Abstract)

G.H. Chapman , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
B. Dufort , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 11
Session 2: Yield Prediction

Extraction of critical areas for opens in large VLSI circuits (Abstract)

C.H. Ouyang , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W.A. Pleskacz , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 21

Fatal Fault Probability Prediction for Array Based Designs (Abstract)

D. D. Gaitonde , Motorola Inc.
W. Maly , Carnegie Mellon University
D. M. H. Walker , Texas A&M University
pp. 30

Yield Prediction by Sampling with the EYES Tool (Abstract)

Gerard A. Allan , University of Edinburgh
Anthony J. Walton , University of Edinburgh
pp. 39

Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches (Abstract)

D. Nikolos , University of Patras
H. T. Vergos , University of Patras
A. Vazaios , University of Patras
S. Voulgaris , University of Patras
pp. 53
Session 3: Yield and Reliability Enhancement

Integration of DFM Techniques and Design Automation (Abstract)

Thomas G. Waring , University of Edinburgh
Gerard A. Allan , University of Edinburgh
and Anthony J. Walton , University of Edinburgh
pp. 59

Trade-offs between yield and reliability enhancement [VLSI] (Abstract)

A. Venkataraman , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 68

Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing (Abstract)

Zhan Chen , University of Massachusetts
Israel Koren , University of Massachusetts
pp. 77

Detection of an antenna effect in VLSI designs (Abstract)

W. Maly , Carnegie Mellon Univ., Pittsburgh, PA, USA
C. Ouyang , Carnegie Mellon Univ., Pittsburgh, PA, USA
S. Ghosh , Carnegie Mellon Univ., Pittsburgh, PA, USA
S. Maturi , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 86
Session 4: Layout-Driven Test

Layout-driven detection of bridge faults in interconnects (Abstract)

Tong Liu , Actel Corp., Sunnyvale, CA, USA
Xiaotao Chen , Actel Corp., Sunnyvale, CA, USA
F. Lombardi , Actel Corp., Sunnyvale, CA, USA
J. Salinas , Actel Corp., Sunnyvale, CA, USA
pp. 105

Test Sequence Generation for Realistic Faults in CMOS ICs Based on Standard Cell Library (Abstract)

Peilin Song , The University of Rhode Island
Jien-Chung Lo , The University of Rhode Island
pp. 114
Session 5: Process Data Analysis

A Statistical Parametric and Probe Yield Analysis Methodology (Abstract)

Allan Y. Wong , KLA - The Yield Management Company
pp. 131

The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes (Abstract)

Thomas Gneiting , Fachhochschule fuer Technik Esslingen
Ian P. Jalowiecki , Brunel University of West London
pp. 140

Maximum Likelihood Estimation for Yield Analysis (Abstract)

F. Joel Ferguson , University of California, Santa Cruz
Jianlin Yu , University of California, Santa Cruz
pp. 149
Session 6: Test And Diagnosis

Comprehensive Modeling of VLSI Test (Abstract)

Earl Swartzlander, Jr. , University of Texas at Austin
pp. 159

Experimental Results from Iddf Testing (Abstract)

C. Thibeault , Ecole de Technologie Superieure
A. Payeur , Ecole de Technologie Superieure
pp. 185
Session 7: Self-Test and Self-Checking Designs

A unified approach for off-line and on-line testing of VLSI systems (Abstract)

P.K. Lala , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
S. Yang , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
F. Busaba , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
pp. 195

Compact and Highly Testable Error Indicator for Self-Checking Circuits (Abstract)

Cecilia Metra , DEIS - Universita' di Bologna
Michele Favalli , DEIS - Universita' di Bologna
Bruno Ricco , DEIS - Universita' di Bologna
pp. 204

Tree Checkers for Applications with Low Power-Delay Requirements (Abstract)

Cecilia Metra , DEIS - Universita' di Bologna
Michele Favalli , DEIS - Universita' di Bologna
Bruno Ricco , DEIS - Universita' di Bologna
pp. 213
Session 8: Fault-Tolerant Structuies

Fault-Tolerant Shuffle-Exchange and de Bruijn Networks Capable of Quick Broadcasting (Abstract)

Nobuo Tsuda , NTT Information and Communication Systems Laboratories
pp. 231

Fault tolerant Newton-Raphson dividers using time shared TMR (Abstract)

W.L. Gallagher , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr. , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 240

Fault detection and fault tolerance issues at CMOS level through AUED encoding (Abstract)

C. Bolchini , Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
G. Buonanno , Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
D. Sciuto , Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
R. Stefanelli , Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
pp. 258
Session 9: Reliable Circuit Synthesis

Optimizing High-Level Synthesis for Self-Checking Arithmetic Circuits (Abstract)

A. Antola , Politecnico di Milano
V. Piuri , Politecnico di Milano
M.G. Sami , Politecnico di Milano
pp. 268

Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study (Abstract)

Jien-Chung Lo , The University of Rhode Island
Masato Kitakami , Tokyo Institute of Technology
Eiji Fujiwara , Tokyo Institute of Technology
pp. 286

Configurable Spare Processors: A New Approach to System Level-Fault Tolerance (Abstract)

Kyosun Kim , University of Massachusetts
Ramesh Karri , University of Massachusetts
Miodrag Potkonjak , University of California, Los Angeles
pp. 295

ROM-Based Synthesis of Fault-Tolerant Controllers (Abstract)

X. Wendling , Laboratoire INPG/CSI
R. Rochet , Laboratoire INPG/CSI
R. Leveugle , Laboratoire INPG/CSI
pp. 304
Session 10: Fault-Tolerance Approaches

Recovery Schemes for Mesh Arrays Utilizing Dedicated Spares (Abstract)

S. R. Goldberg , State University of New York at Buffalo
S. J. Upadhyaya , State University of New York at Buffalo
W. K. Fuchs , Purdue University
pp. 318

KITE: a behavioural approach to fault-tolerance in FPGA-based systems (Abstract)

G.A. Mojoli , Dipt. di Fisica, Milan Univ., Italy
D. Salvi , Dipt. di Fisica, Milan Univ., Italy
M.G. Sami , Dipt. di Fisica, Milan Univ., Italy
G.R. Sechi , Dipt. di Fisica, Milan Univ., Italy
R. Stefanelli , Dipt. di Fisica, Milan Univ., Italy
pp. 327

Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults (Abstract)

T. Horita , Dept. of Comput. & Inf. Sci., Iwate Univ., Morioka, Japan
I. Takanami , Dept. of Comput. & Inf. Sci., Iwate Univ., Morioka, Japan
pp. 335

Index of Authors (PDF)

pp. 341
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