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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (1995)
Lafayette, LA
Nov. 13, 1995 to Nov. 15, 1995
ISSN: 1063-6722
ISBN: 0-8186-7107-6
TABLE OF CONTENTS
Session 1: Critical Area Analysis

AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout (Abstract)

I. Bubel , Fraunhofer-Inst. fur Festkorpertechnologie, Munich, Germany
W. Maly , Fraunhofer-Inst. fur Festkorpertechnologie, Munich, Germany
T. Waas , Fraunhofer-Inst. fur Festkorpertechnologie, Munich, Germany
P.K. Nag , Fraunhofer-Inst. fur Festkorpertechnologie, Munich, Germany
H. Hartmann , Fraunhofer-Inst. fur Festkorpertechnologie, Munich, Germany
D. Schmitt-Landsiedel , Fraunhofer-Inst. fur Festkorpertechnologie, Munich, Germany
S. Griep , Fraunhofer-Inst. fur Festkorpertechnologie, Munich, Germany
pp. 10

Hierarchical extraction of critical area for shorts in very large ICs (Abstract)

P.K. Nag , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 19

Hierarchical critical area extraction with the EYE tool (Abstract)

G.A. Allan , Dept. of Electr. Eng., Edinburgh Univ., UK
A.J. Walton , Dept. of Electr. Eng., Edinburgh Univ., UK
pp. 28
Session 2: Defect Sensitivity and Reliability

Wafer-scale integration defect avoidance tradeoffs between laser links and Omega network switching (Abstract)

G.H. Chapman , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
D.E. Bergen , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
K. Fang , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 37

The effect of spot defects on the parametric yield of long interconnection lines (Abstract)

I.A. Wagner , Dept. of Comput. Sci., Technion-Israel Inst. of Technol., Haifa, Israel
I. Koren , Dept. of Comput. Sci., Technion-Israel Inst. of Technol., Haifa, Israel
pp. 46

Critical area extraction of extra material soft faults (Abstract)

G.A. Allan , Dept. of Electr. Eng., Edinburgh Univ., UK
A.J. Walton , Dept. of Electr. Eng., Edinburgh Univ., UK
pp. 55

Switch level hot-carrier reliability enhancement of VLSI circuits (Abstract)

A. Dasgupta , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
R. Karri , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 63
Session 3: Fault Tolerant Architectures

A model for the evaluation of fault tolerance in the FERMI system (Abstract)

A. Antola , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
L. Breveglieri , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 72

Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths (Abstract)

R. Narasimhan , Dept. of Comput. Sci., State Univ. of New York, Albany, NY, USA
D.J. Rosenkrantz , Dept. of Comput. Sci., State Univ. of New York, Albany, NY, USA
S.S. Ravi , Dept. of Comput. Sci., State Univ. of New York, Albany, NY, USA
pp. 81

Bit-modular defect/fault-tolerant convolvers (Abstract)

L. Dadda , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
V. Piuri , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 90
Session 4: Fault Tolerant Arrays

Reconfigurable architectures for mesh-arrays with PE and link faults (Abstract)

I. Takanami , Dept. of Comput. Sci., Iwate Univ., Morioka, Japan
T. Horita , Dept. of Comput. Sci., Iwate Univ., Morioka, Japan
pp. 108

Totally defect-tolerant arrays capable of quick broadcasting (Abstract)

N. Tsuda , NTT Inf. & Inf. Syst. Labs., Tokyo, Japan
T. Ishikawa , NTT Inf. & Inf. Syst. Labs., Tokyo, Japan
Y. Nakamura , NTT Inf. & Inf. Syst. Labs., Tokyo, Japan
pp. 117

ADTS: an array defect-tolerance scheme for wafer scale gate arrays (Abstract)

A.D. Singh , Dept. of Electr. Eng., Auburn Univ., AL, USA
pp. 126

An improved approach to fault tolerant rank order filtering on a SIMD mesh processor (Abstract)

Jai-Hoon Kim , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
N.H. Vaidya , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 137
Session 5: Yield Projection and Enhancement

Yield projection from defect monitors: the influence of gross defects [BiCMOS process] (Abstract)

N. Harrison , Northern Telecom Electron. Ltd., Nepean, Ont., Canada
pp. 146

Accurate yield estimation of circuits with redundancy (Abstract)

D.D. Gaitonde , Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
D.M.H. Walker , Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
W. Maly , Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
pp. 155

Layer assignment for yield enhancement (Abstract)

Zhan Chen , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 173
Session 6: Fault Tolerant Techniques

Analyzing and improving delay defect tolerance in pipelined combinational circuits (Abstract)

D. Wessels , Dept. of Comput. Sci., Victoria Univ., BC, Canada
J.C. Muzio , Dept. of Comput. Sci., Victoria Univ., BC, Canada
pp. 181

Cost analysis of a new algorithmic-based soft-error tolerant architecture (Abstract)

Y. Blaquiere , Dept. of Comput. Sci., Quebec Univ., Montreal, Que., Canada
G. Gagne , Dept. of Comput. Sci., Quebec Univ., Montreal, Que., Canada
Y. Savaria , Dept. of Comput. Sci., Quebec Univ., Montreal, Que., Canada
C. Evequoz , Dept. of Comput. Sci., Quebec Univ., Montreal, Que., Canada
pp. 189

Efficient time redundancy for error correcting inner-product units and convolvers (Abstract)

Yuang-Ming Hsu , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
V. Piuri , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr. , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 198

A study of time redundant fault tolerance techniques for superscalar processors (Abstract)

M. Franklin , Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
pp. 207

Repair algorithms for mirrored disk systems (Abstract)

H.H. Kari , Dept. of Comput. Sci., Helsinki Univ. of Technol., Espoo, Finland
K. Saikkonen , Dept. of Comput. Sci., Helsinki Univ. of Technol., Espoo, Finland
Sungsoo Kim , Dept. of Comput. Sci., Helsinki Univ. of Technol., Espoo, Finland
F. Lombardi , Dept. of Comput. Sci., Helsinki Univ. of Technol., Espoo, Finland
pp. 216
Session 7: Testing Techniques

A row-based FPGA for single and multiple stuck-at fault detection (Abstract)

X.T. Chen , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
W.K. Huang , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
X. Sun , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 225

Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis (Abstract)

S. Goldberg , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
S.J. Upadhyaya , Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 234

FFT-based test of a yield monitor circuit (Abstract)

C. Thibeault , Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
A. Payeur , Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
pp. 243

Design of defect-tolerant scan chains for MCMs with an active substrate (Abstract)

P. Brahic , Inst. Nat. Polytech. de Grenoble, France
R. Leveugle , Inst. Nat. Polytech. de Grenoble, France
G. Saucier , Inst. Nat. Polytech. de Grenoble, France
pp. 252

Characterization and analysis of errors in circuit test (Abstract)

T. Ziaja , IBM Corp., Austin, TX, USA
E. Swartzlander, Jr. , IBM Corp., Austin, TX, USA
pp. 261
Session 8: Self Checking and Coding Techniques

Self-checking FSMs based on a constant distance state encoding (Abstract)

C. Bolchini , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
R. Montandon , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
F. Salice , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
D. Sciuto , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 269

Constructions of the SbEC-DbED and DbEC codes, and their applications (Abstract)

G.L. Feng , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Sihai Xiao , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Xiaofa Shi , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
T.R.N. Rao , Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
pp. 278

Novel Berger code checker (Abstract)

C. Metra , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
M. Favalli , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
B. Ricco , Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 287

Single fault masking logic designs with error correcting codes (Abstract)

Jien-Chung Lo , Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
pp. 296

Index of Authors (PDF)

pp. 305
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