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Electronic Design, Test and Applications, IEEE International Workshop on (2004)
Perth, Australia
Jan. 28, 2004 to Jan. 30, 2004
ISBN: 0-7695-2081-2
pp: 231-236
F. Ferrandi , Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
P. Lanzi , Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
D. Sciuto , Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
M. Tanelli , Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
ABSTRACT
The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex applications on a single chip, while having to meet strict market demands which force to face always shortening design times. In general, the ideal design methodology shall support the exploration of the highest possible number of alternatives (in terms of HW-SW architectures) starting in the early design stages as this will prevent costly correction efforts in the deployment phase. The present paper will propose a new methodology for tackling the design exploration problem, with the aim of providing a solution in terms of optimal partitioning with respect of the overall system performance.
INDEX TERMS
Hardware, Application software, Embedded system, Computer architecture, Software performance, Performance analysis, Delay estimation, Design methodology, System performance, Modeling,
CITATION
F. Ferrandi, P. Lanzi, D. Sciuto, M. Tanelli, "System-level metrics for hardware/software architectural mapping", Electronic Design, Test and Applications, IEEE International Workshop on, vol. 00, no. , pp. 231-236, 2004, doi:10.1109/DELTA.2004.10060
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