Electronic Design, Test and Applications, IEEE International Workshop on (2002)

Christchurch, New Zealand

Jan. 29, 2002 to Jan. 31, 2002

ISBN: 0-7695-1453-7

pp: 504

S. M. Aziz , University of South Australia

C. N. Basheer , University of South Australia

J. Kamruzzaman , Monash University

ABSTRACT

This paper presents a synthesisable VHDL model for a generalised multiplier capable of performing multiplication of both sign-magnitude and two's complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand word-lengths thereby reducing automatic test generation, simulation and testing times. The model has been used successfully for generating multiplier macros of various operand lengths in different target technologies. A test generation program has been developed for automatic generation of vectors of variable lengths.

INDEX TERMS

C-Testable, Generic, Modified Booth, Multiplier, VHDL, Synthesis

CITATION

J. Kamruzzaman, C. N. Basheer and S. M. Aziz, "A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier,"

*Electronic Design, Test and Applications, IEEE International Workshop on(DELTA)*, Christchurch, New Zealand, 2002, pp. 504.

doi:10.1109/DELTA.2002.994685

CITATIONS