Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
Piia Simonen , Tampere University of Technology
Ilkka Saastamoinen , Tampere University of Technology
Mika Kuulusa , Tampere University of Technology
Jari Nurmi , Tampere University of Technology
On-chip memories can consume multiple times the area of a processor core, thus affecting to the chip costs dramatically. In this paper, three approaches for reducing program memory footprint in a DSP processor are analyzed: fully 16-bit and two versions of mixed 16/32-bit instruction encodings. A separate decompression logic is implemented between memory and core, so the 32-bit processor core is remained unchanged. Compared to the original 32-bit instruction set, the fully 16-bit ISA (Instruction Set Architecture) eliminates 22% of the program memory footprint with a 1.55 times the original runtime. Mixed 16/32-bit ISAs achieve virtually same memory size, but with a faster runtime of 1.29 times the original at best.
instruction memory, memory compression, DSP processor, ISA
J. Nurmi, P. Simonen, M. Kuulusa and I. Saastamoinen, "Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor," Electronic Design, Test and Applications, IEEE International Workshop on(DELTA), Christchurch, New Zealand, 2002, pp. 477.