Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
Y. Bonhomme , Universit? Montpellier II
P. Girard , Universit? Montpellier II
C. Landrault , Universit? Montpellier II
S. Pravossoudovitch , Universit? Montpellier II
Test power relates to the power consumed during test of integrated circuits or embedded cores. Test power is now a big concern in large System-on-Chip designs. In this work, we propose to shortly review the state-of-the-art in this domain. We first survey the recent approaches proposed for minimizing test power. Next, we propose some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied.
Low Power Testing, Test Power, BIST, Scan, DfT
C. Landrault, Y. Bonhomme, P. Girard and S. Pravossoudovitch, "Test Power: a Big Issue in Large SOC Designs," Electronic Design, Test and Applications, IEEE International Workshop on(DELTA), Christchurch, New Zealand, 2002, pp. 447.