Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
Yoshinobu Higami , Ehime University
Shin-ya Kobayashi , Ehime University
Yuzo Takamatsu , Ehime University
This paper presents a method to modify test vectors for reducing power dissipation in CMOS sequential circuits. Test vectors are modified by inverting values of primary inputs one by one. With respect to the reduction of power dissipation, we check if the average number of signal transition gates is decreased and if the maximum number of signal transition gates is not increased. Original fault coverage is guaranteed by logic simulation and fault simulation. The effectiveness of the proposed method is shown by experimental results for ISCAS'89 benchmark circuits.
CMOS circuit, Power dissipation, Test generation, Fault simulation
Y. Takamatsu, S. Kobayashi and Y. Higami, "Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits," Electronic Design, Test and Applications, IEEE International Workshop on(DELTA), Christchurch, New Zealand, 2002, pp. 431.