Electronic Design, Test and Applications, IEEE International Workshop on (2002)

Christchurch, New Zealand

Jan. 29, 2002 to Jan. 31, 2002

ISBN: 0-7695-1453-7

pp: 365

Seung Hoon Choi , Purdue University

Kaushik Roy , Purdue University

ABSTRACT

In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in high-speed circuits. Conventional DC noise analysis produces pessimistic results because it ignores the fact that a gate acts as a low-pass filter. In contrast, the dynamic noise model considers the temporal property of a noise waveform and analyzes its effect on functionality. In this model, both capacitive and inductive coupling are considered as the dominant source of noise in high-speed deep-submicron circuits. It is observed that in the case of the local interconnects (where wire lengths are short), the effect of inductive coupling is small; however, for long interconnects this effect may be considerable. Based on this noise model, we have developed an algorithm to verify high-speed circuits for functional failures due to crosstalk. Design of a 4-bit precharge-evaluate full adder circuit is verified, and many nodes which are susceptible to crosstalk noise are identified. It is observed and further verified by SPICE simulation that dynamic noise analysis is more realistic for verifying functional failures due to crosstalk than DC noise analysis.

INDEX TERMS

Noise Analysis, Crosstalk, Capacitance, Inductance, High Speed Circuit, Noise Margin

CITATION

S. H. Choi and K. Roy, "Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits,"

*Electronic Design, Test and Applications, IEEE International Workshop on(DELTA)*, Christchurch, New Zealand, 2002, pp. 365.

doi:10.1109/DELTA.2002.994651

CITATIONS