Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
P. Prinetto , Polytecnico de Torino
P. Faure , LIRMM - UM2
Y. Zorian , Logic Vision Inc.
M. Renovell , LIRMM - UM2
This paper proposes a new and original solution to test the uni-dimensionnal interconnect architecture of a RAM based FPGA by exploring the specific properties of these blocks. The method to find a reduced set of configurations is proposed and the sequence of test vectors required for each configuration is given.
P. Prinetto, P. Faure, Y. Zorian, M. Renovell, "Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA", Electronic Design, Test and Applications, IEEE International Workshop on, vol. 00, no. , pp. 297, 2002, doi:10.1109/DELTA.2002.994634