Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
Jen-Chieh Yeh , National Tsing Hua University
Chi-Feng Wu , National Tsing Hua University
Kuo-Liang Cheng , National Tsing Hua University
Yung-Fa Chou , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Flash memories are a type of non-volatile memory based on floating-gate transistors. The use of commodity and embedded flash memories are growing rapidly as we enter the system-on-chip (SOC) era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. We propose improved March-like algorithms (i.e., March FT) for both bit-oriented and word-oriented flash memory, to cover the disturbance faults derived from the IEEE 1005 Standard, as well as conventional faults. A noval flash memory fault simulator is used to analyze and generate the test algorithms. In addition, we present BIST designs for two industrial flash memories. The area overhead is only about 3% for a medium-sized flash memory.
C. Huang, Y. Chou, C. Wu, K. Cheng, C. Wu and J. Yeh, "Flash Memory Built-In Self-Test Using March-Like Algorithms," Electronic Design, Test and Applications, IEEE International Workshop on(DELTA), Christchurch, New Zealand, 2002, pp. 137.