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Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
ISBN: 0-7695-1453-7
pp: 128
Ivo Schanstra , Infineon Technologies AG
Ad. J. van de Goor , Delft University of Technology
The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a large impact on the effectiveness of the used tests. This paper presents an analysis of address and data scrambling for memory chips, at the layout and at the electrical level. A method is presented to determine the data backgrounds to be used for the different memory tests. It will be shown that the required data backgrounds are fault model, and hence, also test specific. Industrial results will show the influence of the used data backgrounds on the fault coverage of the tests.
Address-scrambling, data-scrambling, data backgrounds, fault models, memory tests
Ivo Schanstra, Ad. J. van de Goor, "Address and Data Scrambling: Causes and Impact on Memory Tests", Electronic Design, Test and Applications, IEEE International Workshop on, vol. 00, no. , pp. 128, 2002, doi:10.1109/DELTA.2002.994601
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