Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
I. Saastamoinen , Tampere University of Technology
D. Sigüenza-Tortosa , Tampere University of Technology
J. Nurmi , Tampere University of Technology
In this paper an interconnect IP (Intellectual Property) node architecture for flexible on-chip communication is introduced. This architecture is targeted for communication in future gigatransistor SoC (System-on-Chip) designs. The interconnect IP will be used as a testing platform when the efficiency of network topologies and routing schemes are investigated for on-chip environment. The interconnect node uses packet based communication and forms a reusable component itself. The node is constructed from a collection of parameterized and reusable hardware blocks. Those blocks include components such as FIFO buffers, routing controllers and standardized interface wrappers. A node can be tuned to fulfill the desired characteristics of communication by selecting the internal architecture of the node properly. In the future the IP node forms a basic building component in SoC implementations.
System-on-Chip, on-chip communication, packet network, reuse
D. Sigüenza-Tortosa, J. Nurmi and I. Saastamoinen, "Interconnect IP Node for Future System-on-Chip Designs," Electronic Design, Test and Applications, IEEE International Workshop on(DELTA), Christchurch, New Zealand, 2002, pp. 116.