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Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
ISBN: 0-7695-1453-7
pp: 111
Chie Dou , National Yunlin University of Science and Technology
Shing-Jeh Jiang , Computer & Communications Research Laboratories
Kuo-Cheng Leu , Computer & Communications Research Laboratories
This paper proposes an integrated CAM/RAM based buffer manager for next-generation IP routers. Buffer allocation is accomplished by inspecting the length field in the IP header of an incoming packet, the wasted buffer area is optimized, and the hardware implementation is simple. The data buffer is configured according to the cumulative packet size distribution observed from the underlying network thus increases the efficiency of the memory utilization. The buffer manager also supports the multicast management in an elaborate manner. In addition, it supports different-sized block movement of the packet data between the data buffer and the transmission media. Finally, it need not have to maintain the free buffer list, i.e., enormous and repeated 'insert' and 'delete' operations of pointers in a linked list are eliminated.
buffer manager, content addressable memory, IP router, CAM/RAM integration

S. Jiang, K. Leu and C. Dou, "A Novel CAM/RAM Based Buffer Manager for Next Generation IP Routers," Electronic Design, Test and Applications, IEEE International Workshop on(DELTA), Christchurch, New Zealand, 2002, pp. 111.
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