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Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
ISBN: 0-7695-1453-7
pp: 92
Kazuya Shimizu , Osaka University
Masaya Takamura , Osaka University
Takanori Shirai , Osaka University
Kozo Kinoshita , Osaka University
Noriyoshi Itazaki , Osaka University
In recent years, domino logic circuits have received much attention as high-speed circuits by taking place of static CMOS circuits. However, in case of standard domino logic, only non-inverting gates are allowed. Then, clock-delayed (CD) domino logic that provides any logic function is proposed in order to overcome such domino's drawback. In addition, domino circuits are more sensitive to circuit noises compared with static CMOS circuits. In particular, crosstalk can induce critical problems. Therefore, we focus our attention on faulty operations induced by crosstalk in CD domino circuits and propose a new fault simulation method. We realize CD domino logic in VHDL and simulate on a VHDL simulator. We performed experiments for the combinational part of some benchmark circuits of ISCAS'89. And fault coverage for random vectors was obtained from s27 to s1494 under the limitation of simulation time.
crosstalk fault, Clock-delayed domino circuit, Fault simulation
Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Kozo Kinoshita, Noriyoshi Itazaki, "Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits", Electronic Design, Test and Applications, IEEE International Workshop on, vol. 00, no. , pp. 92, 2002, doi:10.1109/DELTA.2002.994595
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