Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
J. Geoffrey Chase , University of Canterbury
Christopher Pretty , University of Canterbury
Alex Bedarida , Infineon Technologies Corp.
Philippe Bettler , Infineon Technologies Corp.
The current trend in DSP architecture is to widen the data path and augment computational power, often at the expense of issues that significantly impact the ability to utilize its computation. With today's highly parallel architectures and complex application spaces DSP selection has become overly complicated and the addition of special instructions that support intensive algorithms, while maximizing parallelism, has further complicated the issue. Typically, a system designer may rely on simple cycle counts, discounting the impact of architecture, efficiency and power consumption. The simple cycle efficiency metric presented clearly illustrates that the ability to utilize the theoretically available computation is a significant measure of DSP performance for a given application. This metric is presented as an application-oriented design tool and is employed to compare the dual-execution unit, dynamically reconfigurable Carmel DSP with similar architectures.
Signal Processing, DSP Architecture, Application Analysis, Reconfigurable DSP
J. G. Chase, P. Bettler, C. Pretty and A. Bedarida, "An Applications-Based Approach to Measuring DSP Efficiency," Electronic Design, Test and Applications, IEEE International Workshop on(DELTA), Christchurch, New Zealand, 2002, pp. 59.