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Electronic Design, Test and Applications, IEEE International Workshop on (2002)
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
ISBN: 0-7695-1453-7
pp: 3
Y.S. Lee , The Hong Kong Polytechnic University
Mike W. T. Wong , The Hong Kong Polytechnic University
K. Y. Ko , The Hong Kong Polytechnic University
ABSTRACT
This paper describes a test approach for Intellectual Property (IP) analog or mixed-signal cores, which may be used in core-based System-on-Chip (SOC) designs. The proposed method comprises a two-phase test design process. Given an analog/mixed-signal IP core, an equivalent fault analysis is carried out in the initial phase. The main aim is to extract useful insights for improving the BIST and DfT designs which to be conducted in the second phase. An early built-in self-test (BIST) method [9] was able to achieve high fault coverage comparable to the traditional scan techniques. In the second phase, we propose to apply an improved version of this method based on the weighted sum of selected node voltages. Besides high fault coverage, the proposed BIST technique only needs an extra testing output pin and only a single DC stimulus is needed to feed at the primary input of the circuit under test (CUT). Hence, the proposed BIST technique is especially suitable for the testing environment of IP cores.
INDEX TERMS
SOCs, mixed-signal design, analog circuit testing
CITATION
Y.S. Lee, Mike W. T. Wong, K. Y. Ko, "Analog and Mixed-Signal IP Cores Testing", Electronic Design, Test and Applications, IEEE International Workshop on, vol. 00, no. , pp. 3, 2002, doi:10.1109/DELTA.2002.994579
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