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2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (2014)
Warsaw, Poland
April 23, 2014 to April 25, 2014
ISBN: 978-1-4799-4560-3
TABLE OF CONTENTS

Front cover (PDF)

pp. c1

Title page (PDF)

pp. 1

Copyright (PDF)

pp. 1

Design and testing of integrated circuit of pixel architecture for fast x-ray imaging applications (PDF)

Pawel Grybos , Department of Measurement and Electronics, AGH University of Science and Technology, Cracow, Poland
Piotr Kmon , Department of Measurement and Electronics, AGH University of Science and Technology, Cracow, Poland
Piotr Maj , Department of Measurement and Electronics, AGH University of Science and Technology, Cracow, Poland
Robert Szczygiel , Department of Measurement and Electronics, AGH University of Science and Technology, Cracow, Poland
pp. 11

SiP design flow and 3D DRC for MEMS (PDF)

A. Mehdaoui , Coventor SARL, France
J. Pagazani , Université Paris-Est, ESYCOM, UPEMLV, ESIEE, CNAM, France
G. Schropfer , Coventor SARL, France
G. Lissorgues , Université Paris-Est, ESYCOM, UPEMLV, ESIEE, CNAM, France
pp. 12-13

Development of 3D space partitioning and design rule check for smart system solutions (PDF)

Stefano Pettazzi , Silvaco, United Kingdom
Andrew Plews , Silvaco, United Kingdom
Anatoly Rudenko , Silvaco, United Kingdom
Ahmed Nejim , Silvaco, United Kingdom
pp. 14

Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs (Abstract)

Muhammad Aamir Khan , Testable Design and Test of Integrated Systems (TDT) Group, University of Twente, Centre of Telematics and Information Technology (CTIT), Enschede, the Netherlands
Hans G. Kerkhoff , Testable Design and Test of Integrated Systems (TDT) Group, University of Twente, Centre of Telematics and Information Technology (CTIT), Enschede, the Netherlands
pp. 15-20

Automatically connecting hardware blocks via light-weight matching techniques (Abstract)

Jan Malburg , Institute of Computer Science, University of Bremen, 28359, Germany
Niklas Krafczyk , Institute of Computer Science, University of Bremen, 28359, Germany
Gorschwin Fey , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 21-26

A double-path intra prediction architecture for the hardware H.265/HEVC encoder (Abstract)

Andrzej Abramowski , Institute of Radioelectronics, Warsaw University of Technology, Poland 00-665
Grzegorz Pastuszak , Institute of Radioelectronics, Warsaw University of Technology, Poland 00-665
pp. 27-32

Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic (Abstract)

Jurgen Maier , Institute of Computer Engineering, Vienna University of Technology, Austria
Andreas Steininger , Institute of Computer Engineering, Vienna University of Technology, Austria
pp. 33-38

Quality assurance in memory built-in self-test tools (Abstract)

Albert Au , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Artur Pogiel , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Piotr Sydow , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Jerzy Tyszer , Poznań University of Technology, 60-965, Poland
Justyna Zawada , Poznań University of Technology, 60-965, Poland
pp. 39-44

Generic built-in self-repair architectures for SoC logic cores (Abstract)

Marcel Balaz , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovak Republic
Stefan Kristofik , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovak Republic
Maria Fischerova , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovak Republic
pp. 45-50

A 64-MHz∼640-MHz 64-phase clock generator (Abstract)

Hong-Yi Huang , Department of Electrical Engineering, National Taipei University, Taiwan
Jen-Chieh Liu , Information and Communications Research Laboratories, Industrial Technology Research Institute, Taiwan
Shi-Jia Sun , Department of Electrical Engineering, National Taipei University, Taiwan
Cheng-Hao Fu , Department of Electrical Engineering, National Taipei University, Taiwan
Kuo-Hsing Cheng , Department of Electrical Engineering, National Central University, Taiwan
pp. 51-54

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology (Abstract)

Woorham Bae , Inter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Korea
Deog-Kyoon Jeong , Inter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Korea
Byoung-Joo Yoo , System LSI Division, Samsung Electronics, Hwasung, Korea
pp. 55-58

Burst-pulse Generator based on transmission line toward sub-MMW (Abstract)

Parit Kanjanavirojkul , VLSI Design and Education Center (VDEC), The University of Tokyo, Japan
Nguyen Ngoc Mai Khanh , Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan
Toru Nakura , Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan
Kunihiro Asada , Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan
pp. 59-64

A 120V high voltage DAC array for a tunable antenna in communication system (Abstract)

Jing Ning , Integrated Electronic System Lab, TU Darmstadt, Germany
Klaus Hofmann , Integrated Electronic System Lab, TU Darmstadt, Germany
pp. 65-70

Fast time-parallel C-based event-driven RTL simulation (Abstract)

Tariq Bashir Ahmad , ECE Department, University of Massachusetts Amherst, USA
Maciej Ciesielski , ECE Department, University of Massachusetts Amherst, USA
pp. 71-76

Lower bounds of the size of Shared Structurally Synthesized BDDs (Abstract)

Raimund Ubar , Tallinn University of Technology, Estonia
Dmitri Mironov , Tallinn University of Technology, Estonia
pp. 77-82

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching (Abstract)

Roel Jordans , Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
Erkan Diken , Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
Lech Jozwiak , Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
Henk Corporaal , Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands
pp. 83-88

Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators (Abstract)

Harish Balasubramaniam , Integrated Electronic Systems Lab, TU Darmstadt, Merckstr.25, 64283, Germany
Klaus Hofmann , Integrated Electronic Systems Lab, TU Darmstadt, Merckstr.25, 64283, Germany
pp. 89-92

Multistage low ripple charge pump (Abstract)

Andrzej Grodzicki , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
Witold Pleskacz , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
pp. 93-98

A novel impedance calculation method and its time efficiency evaluation (Abstract)

Juraj Brenkus , Department of IC Design and Test, Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
Viera Stopjakova , Department of IC Design and Test, Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
Daniel Arbet , Department of IC Design and Test, Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
Gabor Gyepes , Department of IC Design and Test, Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
Libor Majer , Department of IC Design and Test, Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
pp. 99-103

Test-data compression with low number of channels and short test time (Abstract)

Ondrej Novak , Institute of Information Technologies and Electronics, Technical University in Liberec, Czech Republic
Jiri Jenicek , Institute of Information Technologies and Electronics, Technical University in Liberec, Czech Republic
Martin Rozkovec , Institute of Information Technologies and Electronics, Technical University in Liberec, Czech Republic
pp. 104-109

Test data compression based on reuse and bit-flipping of parts of dictionary entries (Abstract)

Panagiotis Sismanoglou , Dept. of Computer Engineering and Informatics, University of Patras, Greece
Dimitris Nikolos , Dept. of Computer Engineering and Informatics, University of Patras, Greece
pp. 110-115

Timing-aware ATPG for critical paths with multiple TSVs (Abstract)

C. Metzler , LIRMM UMR 5506 - University of Montpellier 2/CNRS, France
A. Todri-Sanial , LIRMM UMR 5506 - University of Montpellier 2/CNRS, France
A. Bosio , LIRMM UMR 5506 - University of Montpellier 2/CNRS, France
L. Dilillo , LIRMM UMR 5506 - University of Montpellier 2/CNRS, France
P. Girard , LIRMM UMR 5506 - University of Montpellier 2/CNRS, France
A. Virazel , LIRMM UMR 5506 - University of Montpellier 2/CNRS, France
pp. 116-121

A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips (Abstract)

Pranab Roy , School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India
Hafizur Rahaman , School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India
Parthasarathi Dasgupta , Indian Institute of Management, Calcutta, India
pp. 122-128

Optimizing DD-based synthesis of reversible circuits using negative control lines (Abstract)

Eleonora Schonborn , Institute of Computer Science, University of Bremen, 28359, Germany
Kamalika Datta , Department of Information Technology, Bengal Engineering & Science University, Shibpur, Howrah 711103, India
Robert Wille , Institute of Computer Science, University of Bremen, 28359, Germany
Indranil Sengupta , Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur 721301, India
Hafizur Rahaman , Department of Information Technology, Bengal Engineering & Science University, Shibpur, Howrah 711103, India
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 129-134

Evolutionary design of approximate multipliers under different error metrics (Abstract)

Zdenek Vasicek , Brno University of Technology, Faculty of Information Technology, IT4Innovations Centre of Excellence, Czech Republic
Lukas Sekanina , Brno University of Technology, Faculty of Information Technology, IT4Innovations Centre of Excellence, Czech Republic
pp. 135-140

Online testing of many-core systems in the Dark Silicon era (Abstract)

Mohammad-Hashem Haghbayan , Department of Information Technology, University of Turku, Finland
Amir-Mohammad Rahmani , Department of Information Technology, University of Turku, Finland
Pasi Liljeberg , Department of Information Technology, University of Turku, Finland
Juha Plosila , Department of Information Technology, University of Turku, Finland
Hannu Tenhunen , Department of Information Technology, University of Turku, Finland
pp. 141-146

Reliable execution of statechart-generated correct embedded software under soft errors (Abstract)

Ronaldo R. Ferreira , Instituto de Informática - Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Thomas Klotz , Fraunhofer Institute for Integrated Circuits, Dresden, Germany
Thilo Vortler , Fraunhofer Institute for Integrated Circuits, Dresden, Germany
Jean da Rolt , Instituto de Informática - Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Gabriel L. Nazar , Instituto de Informática - Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Alvaro F. Moreira , Instituto de Informática - Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Luigi Carro , Instituto de Informática - Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Karsten Einwich , Fraunhofer Institute for Integrated Circuits, Dresden, Germany
pp. 147-152

Combining fault tolerance and self repair at minimum cost in power and hardware (Abstract)

Tobias Koal , Brandenburg University of Technology Cottbus-Senftenberg, Computer Engineering Group, Germany
Mario Scholzel , Brandenburg University of Technology Cottbus-Senftenberg, Computer Engineering Group, Germany
Heinrich T. Vierhaus , Brandenburg University of Technology Cottbus-Senftenberg, Computer Engineering Group, Germany
pp. 153-158

Self-managing power management unit (Abstract)

Dominik Macko , Faculty of Informatics and Information Technologies, Slovak University of Technology, Bratislava, Slovakia
Katarina Jelemenska , Faculty of Informatics and Information Technologies, Slovak University of Technology, Bratislava, Slovakia
pp. 159-162

A low supply voltage synchronous mirror delay with quadrature phase output (Abstract)

Yo-Hao Tu , Department of Electrical Engineering, National Central University, Taiwan, Republic of China (R.O.C)
Kuo-Hsing Cheng , Department of Electrical Engineering, National Central University, Taiwan, Republic of China (R.O.C)
Chih-Hsun Hsu , Department of Electrical Engineering, National Central University, Taiwan, Republic of China (R.O.C)
Hong-Yi Huang , Graduate Institute of Electrical Engineering, National Taipei University, Taiwan, Republic of China (R.O.C)
pp. 163-166

High throughput architecture for the Advanced Encryption Standard Algorithm (Abstract)

Salma Hesham , Electronics Department, German University in Cairo, Egypt
Mohamed A. Abd El Ghany , Electronics Department, German University in Cairo, Egypt
Klaus Hofmann , Integrated Electronic Systems Lab, TU Darmstadt, Germany
pp. 167-170

Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA (Abstract)

Lukas Miculka , Brno University of Technology, Faculty of Information Technology, Bozetechova 2, 612 66, Czech Republic
Zdenek Kotasek , Brno University of Technology, Faculty of Information Technology, Bozetechova 2, 612 66, Czech Republic
pp. 171-174

Low latency book handling in FPGA for high frequency trading (Abstract)

Milan Dvorak , Faculty of Information Technology, Brno University of Technology, Boǧetěchova 2, 612 66, Czech Republic
Jan Korenek , Faculty of Information Technology, Brno University of Technology, Božetěchova 2, 612 66, Czech Republic
pp. 175-178

CRC based hashing in FPGA using DSP blocks (Abstract)

Tomas Zavodnik , Faculty of Information Technology, Brno University of Technology, Božetěchova 2, 612 66, Czech Republic
Lukas Kekely , CESNET a. l. e., Zikova 4, 160 00 Prague, Czech Republic
Viktor Pus , CESNET a. l. e., Zikova 4, 160 00 Prague, Czech Republic
pp. 179-182

The LSI implementation of a memory based field programmable device for MCU peripherals (Abstract)

Tetsuya Matsumura , College of Engineering, Nihon University, Koriyama, Japan
Naoya Okada , College of Science and Engineering, Kanazawa University, Kanazawa, Japan
Yoshifumi Kawamura , 1st Solution Business Unit, Renesas Electronics Corporation, Kodaira, Japan
Koji Nii , 1st Solution Business Unit, Renesas Electronics Corporation, Kodaira, Japan
Kazutami Arimoto , Faculty of Computer and Systems Engineering, Okayama Prefectural University, Soja, Japan
Hiroshi Makino , Faculty of Information Science and Technology, Osaka Institute of Technology, Hirakata, Japan
Yoshio Matsuda , College of Science and Engineering, Kanazawa University, Kanazawa, Japan
pp. 183-188

Design methodology of configurable high performance packet parser for FPGA (Abstract)

Viktor Pus , CESNET a. l. e., Zikova 4, 160 00 Prague, Czech Republic
Lukas Kekely , CESNET a. l. e., Zikova 4, 160 00 Prague, Czech Republic
Jan Korenek , IT4Innovations Centre of Excellence, Faculty of Information Technology, Brno University of Technology, Božetěchova 2, 612 66, Czech Republic
pp. 189-194

A study on fast pipelined pseudo-random number generator based on chaotic logistic map (Abstract)

Pawel Dabal , Faculty of Electronics, Military University of Technology, Warsaw, Poland
Ryszard Pelka , Faculty of Electronics, Military University of Technology, Warsaw, Poland
pp. 195-200

Modeling timing constraints for automatic generation of embedded test instruments (Abstract)

S. Ostendorff , Integrated Communication Systems Group, Technische Universität Ilmenau, Germany
J.-H. Meza Escobar , Integrated Communication Systems Group, Technische Universität Ilmenau, Germany
H.-D. Wuttke , Integrated Communication Systems Group, Technische Universität Ilmenau, Germany
T. Sasse , Institute of Optimization and Operations Research, Universität Ulm, Germany
S. Richter , Department of Matematics, Technische Universität Chemnitz, Germany
pp. 201-206

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce (Abstract)

A. Asokan , LIRMM - University of Montpellier II/CNRS, France
A. Todri-Sanial , LIRMM - University of Montpellier II/CNRS, France
A. Bosio , LIRMM - University of Montpellier II/CNRS, France
L. Dilillo , LIRMM - University of Montpellier II/CNRS, France
P. Girard , LIRMM - University of Montpellier II/CNRS, France
S. Pravossoudovitch , LIRMM - University of Montpellier II/CNRS, France
A. Virazel , LIRMM - University of Montpellier II/CNRS, France
pp. 207-212

Test and diagnosis of power switches (Abstract)

M. Valka , LIRMM, University of Montpellier II / CNRS, France
A. Bosio , LIRMM, University of Montpellier II / CNRS, France
L. Dilillo , LIRMM, University of Montpellier II / CNRS, France
A. Todri , LIRMM, University of Montpellier II / CNRS, France
A. Virazel , LIRMM, University of Montpellier II / CNRS, France
P. Girard , LIRMM, University of Montpellier II / CNRS, France
P. Debaud , ST-Microelectronics, Grenoble, France
S. Guilhot , ST-Microelectronics, Grenoble, France
pp. 213-218

Fast lookup for dynamic packet filtering in FPGA (Abstract)

Lukas Kekely , IT4Innovations Centre of Excellence, Brno University of Technology, Czech Republic
Martin Zadnik , IT4Innovations Centre of Excellence, Brno University of Technology, Czech Republic
Jiri Matousek , IT4Innovations Centre of Excellence, Brno University of Technology, Czech Republic
Jan Korenek , IT4Innovations Centre of Excellence, Brno University of Technology, Czech Republic
pp. 219-222

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults (Abstract)

I. Wali , LIRMM - University of Montpellier 2 / CNRS, France
A. Virazel , LIRMM - University of Montpellier 2 / CNRS, France
A. Bosio , LIRMM - University of Montpellier 2 / CNRS, France
L. Dilillo , LIRMM - University of Montpellier 2 / CNRS, France
P. Girard , LIRMM - University of Montpellier 2 / CNRS, France
A. Todri , LIRMM - University of Montpellier 2 / CNRS, France
pp. 223-225

Stabilization methods for integrated high voltage charge pumps (Abstract)

Lufei Shen , Integrated Electronic Systems Lab, Technische Universität (TU) Darmstadt, Germany
Ferdinand Keil , Integrated Electronic Systems Lab, Technische Universität (TU) Darmstadt, Germany
Klaus Hofmann , Integrated Electronic Systems Lab, Technische Universität (TU) Darmstadt, Germany
pp. 226-229

FPGA design of the computation unit for the semi-global stereo matching algorithm (Abstract)

Mikolaj Roszkowski , Institute of Radioelectronics, Warsaw University of Technology, Poland
Grzegorz Pastuszak , Institute of Radioelectronics, Warsaw University of Technology, Poland
pp. 230-233

System design for enhanced forward-engineering possibilities of safety critical embedded systems (Abstract)

Martin Krammer , Virtual Vehicle Research Center, Graz Austria
Michael Karner , Virtual Vehicle Research Center, Graz Austria
Anton Fuchs , Virtual Vehicle Research Center, Graz Austria
pp. 234-237

Mismatch effects and their correction in large area ASICs (Abstract)

Piotr Maj , Department of Measurement and Electronics, AGH University of Science and Electronics, Krakow, Poland
pp. 238-241

A unified CMOS inverter model for planar and FinFET nanoscale technologies (Abstract)

Panagiotis Chaourani , Physics Department, Aristotle University of Thessaloniki, Greece
Spyridon Nikolaidis , Physics Department, Aristotle University of Thessaloniki, Greece
pp. 242-245

A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems (Abstract)

Victor Tomashevich , Faculty of Mathematics and Computer Science, University of Passau, Germany, Innstr. 41, 94032
Christina Gimmler-Dumont , Fachbereich Elektrotechnik und Informationstechnik, Technische Universitaet Kaiserslautern, Germany, Erwin-Schroedinger-Str
Christian Fesl , Faculty of Mathematics and Computer Science, University of Passau, Germany, Innstr. 41, 94032
Norbert Wehn , Fachbereich Elektrotechnik und Informationstechnik, Technische Universitaet Kaiserslautern, Germany, Erwin-Schroedinger-Str
Ilia Polian , Faculty of Mathematics and Computer Science, University of Passau, Germany, Innstr. 41, 94032
pp. 246-249

Dedicated hardware architecture for object tracking preprocessing implemented in FPGA (Abstract)

Peter Malik , Institute of Informatics, Slovak Academy of Sciences, Dubravska cesta 9, 845 07 Bratislava, Slovak Republic
pp. 250-253

Emulation based fault injection on UHF RFID transponder (Abstract)

Omar Abdelmalek , Grenoble Institute of Technology, Valence, France
David Hely , Grenoble Institute of Technology, Valence, France
Vincent Beroulle , Grenoble Institute of Technology, Valence, France
pp. 254-257

Sources of bias in EDA tools and its influence (Abstract)

Petr Fiser , Faculty of Information Technology, Czech Technical University in Prague, Czech Republic
Jan Schmidt , Faculty of Information Technology, Czech Technical University in Prague, Czech Republic
Jiri Balcarek , Faculty of Information Technology, Czech Technical University in Prague, Czech Republic
pp. 258-261

Automatic and reliable electrical characterization of MOSFETs (Abstract)

Z. Stamenkovic , System Design, IHP GmbH, Frankfurt (Oder), Germany
N. D. Vasovic , Faculty of Electronic Engineering, University of Niš, Serbia
G. S. Ristic , Faculty of Electronic Engineering, University of Niš, Serbia
pp. 262-265

An approach towards selection of the oscillation frequency for oscillation test of analog ICs (Abstract)

Martin Kovac , Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
Daniel Arbet , Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
Gabriel Nagy , Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
Viera Stopjakova , Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia
pp. 266-267

Customer return detection with features selection (Abstract)

Domenico Bertoncelli , Department of Information Engineering, Computer Science and Mathematics, University of L'Aquila, Italy
Pasquale Caianiello , Department of Information Engineering, Computer Science and Mathematics, University of L'Aquila, Italy
pp. 268-269

Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections (Abstract)

Tomasz Garbolino , Institute of Electronics, Silesian University of Technology, Gliwice, Poland
pp. 270-273

On NFA-split architecture optimizations (Abstract)

Vlastimil Kosar , IT4Innovations Centre of Excellence, Faculty of Information Technology, Brno University of Technology, Božetěchova 2, 612 66, Czech Republic
Jan Korenek , IT4Innovations Centre of Excellence, Faculty of Information Technology, Brno University of Technology, Božetěchova 2, 612 66, Czech Republic
pp. 274-277

ADCs in deep submicron technologies for ASICs of pixel architecture (Abstract)

Piotr Otfinowski , Department of Measurement and Electronics, AGH University of Science and Technology, Cracow, Poland
Pawel Grybos , Department of Measurement and Electronics, AGH University of Science and Technology, Cracow, Poland
Robert Szczygiel , Department of Measurement and Electronics, AGH University of Science and Technology, Cracow, Poland
Piotr Maj , Department of Measurement and Electronics, AGH University of Science and Technology, Cracow, Poland
pp. 278-281

Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits (Abstract)

Kevin Ngari Muriithi , Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan
Toru Nakura , VLSI Design and Education Center (VDEC), The University of Tokyo, Japan
Kunihiro Asada , VLSI Design and Education Center (VDEC), The University of Tokyo, Japan
pp. 282-285

On the in-field test of Branch Prediction Units using the correlated predictor mechanism (Abstract)

M. Gaudesi , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
S. Saleem , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
E. Sanchez , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
E. Tanowe , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
pp. 286-289

FPGA architectures of the quantization and the dequantization for video encoders (Abstract)

Grzegorz Pastuszak , Institute of Radioelectronics, Warsaw University of Technology, Nowowiejska 15/19, 00-665, Poland
pp. 290-293

An efficient hardware architecture for inter-prediction in H.264/AVC encoders (Abstract)

Nam-Khanh Dang , SIS Laboratory, VNU University of Engineering and Technology, 144 Xuan Thuy road, Cau Giay, Hanoi, Vietnam
Xuan-Tu Tran , SIS Laboratory, VNU University of Engineering and Technology, 144 Xuan Thuy road, Cau Giay, Hanoi, Vietnam
Alain Merirot , University Paris Sud XI, 91192 Gif-sur-Yvette Cedex, France
pp. 294-297

An intra-cell defect grading tool (Abstract)

A. Bosio , LIRMM-UM2/CNRS, France
L. Dilillo , LIRMM-UM2/CNRS, France
P. Girard , LIRMM-UM2/CNRS, France
A. Todri-Sanial , LIRMM-UM2/CNRS, France
A. Virazel , LIRMM-UM2/CNRS, France
S. Bernabovi , Politecnico di Torino, Italy
P. Bernardi , Politecnico di Torino, Italy
pp. 298-301

Heuristic algorithm of two-level minimization of fuzzy logic functions (Abstract)

Andrzej Wielgus , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland
pp. 302-305

Verifying robust frequency domain properties of non linear oscillators using SMT (Abstract)

Hafiz ul Asad , City University London, EC1 0HB, UK
Kevin D. Jones , City University London, EC1 0HB, UK
Frederic Surre , City University London, EC1 0HB, UK
pp. 306-309

Modeling and analysis of cracked through silicon via (TSV) interconnections (Abstract)

Vasileios Gerakis , Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Greece
Christina Avdikou , Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Greece
Alexandros Liolios , Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Greece
Alkis Hatzopoulos , Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Greece
pp. 310-313

Case study: BISR for a processor multiplier (Abstract)

Andrej Kincel , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovak Republic
Marcel Balaz , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovak Republic
pp. 314-317

Efficient VHDL implementation of symbol synchronization for software radio based on FPGA (Abstract)

Pavel Fiala , Faculty of Electrical Engineering, University of West Bohemia, Plzen, Czech Republic
Richard Linhart , Faculty of Electrical Engineering, University of West Bohemia, Plzen, Czech Republic
pp. 318-321

Author index (PDF)

pp. 322-323

Sponsors (PDF)

pp. 324-325
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