The Community for Technology Leaders
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (2011)
Cottbus Germany
Apr. 13, 2011 to Apr. 15, 2011
ISBN: 978-1-4244-9755-3
TABLE OF CONTENTS

Design technology and the cloud (PDF)

Raul Camposano , CEO Physware, Mountain View, CA, USA
pp. 1

Cost effective scaling to 22nm and below technology nodes (PDF)

Andrzej J. Strojwas , PDF Solutions, Inc. and Carnegie Mellon University, Pittsburgh, PA15213, USA
pp. 2

Future of EDA: Usual suspect or silent hero for successful semiconductor business? (PDF)

Jurgen Alt , Intel Mobile Communications GmbH, Neubiberg, Germany
pp. 3

SiGe BiCMOS platform - baseline technology for More Than Moore process module integration (PDF)

Bernd Tillack , IHP, Im Technlogiepark 25, 15236, Frankfurt (Oder), Germany
pp. 4

Introduction to the SystemC AMS extension standard (PDF)

Karsten Einwich , Fraunhofer IIS/EAS, Dresden, Germany
pp. 6-8

Conversion and interfacing techniques for asynchronous circuits (PDF)

Markus Ferringer , Department of Computer Engineering, Vienna University of Technology, Austria
pp. 11-16

A system-level platform for dependability enhancement and its analysis for mixed-signal SoCs (PDF)

Muhammad A. Khan , Testable Design and Test of Integrated Systems (TDT) Group, University of Twente, Centre of Telematics and Information Technology (CTIT), Enschede, the Netherlands
Hans G. Kerkhoff , Testable Design and Test of Integrated Systems (TDT) Group, University of Twente, Centre of Telematics and Information Technology (CTIT), Enschede, the Netherlands
pp. 17-22

PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications (PDF)

Krzysztof Siwiec , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
Tomasz Borejko , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
Witold A. Pleskacz , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
pp. 29-34

Design-for-Test method for high-speed ADCs: Behavioral description and optimization (PDF)

Y. Lechuga , Microelectronics Engineering Group, University of Cantabria, Av. de los Castros s/n E-39005 Santander (Spain)
R. Mozuelos , Microelectronics Engineering Group, University of Cantabria, Av. de los Castros s/n E-39005 Santander (Spain)
M. Martinez , Microelectronics Engineering Group, University of Cantabria, Av. de los Castros s/n E-39005 Santander (Spain)
S. Bracho , Microelectronics Engineering Group, University of Cantabria, Av. de los Castros s/n E-39005 Santander (Spain)
pp. 35-40

High performance adaptive sensor interface design through model based estimation of analog non-idealities (PDF)

Sumit Adhikari , Institute for Computer Technology, Vienna University of Technology, Gusshausstrasse 27-29/384, 1040 Vienna, Austria
Muhammad Farooq , Institute for Computer Technology, Vienna University of Technology, Gusshausstrasse 27-29/384, 1040 Vienna, Austria
Jan Haase , Institute for Computer Technology, Vienna University of Technology, Gusshausstrasse 27-29/384, 1040 Vienna, Austria
Christoph Grimm , Institute for Computer Technology, Vienna University of Technology, Gusshausstrasse 27-29/384, 1040 Vienna, Austria
pp. 41-46

Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encoders (PDF)

Xuan-Tu Tran , SIS Laboratory, University of Engineering and Technology, VNU Hanoi. 144 Xuan Thuy road, 10000, Vietnam
Van-Huan Tran , SIS Laboratory, University of Engineering and Technology, VNU Hanoi. 144 Xuan Thuy road, 10000, Vietnam
pp. 47-52

Towards an unified IP verification and robustness analysis platform (PDF)

David Hely , LCIS, Grenoble Institute of Technology, Valence, France
Vincent Beroulle , LCIS, Grenoble Institute of Technology, Valence, France
Feng Lu , LCIS, Grenoble Institute of Technology, Valence, France
Jose Ramon Oya Garcia , GTE, University of Seville, Spain
pp. 53-58

An example of DISPLAY-CTRL IP Component verification in SCE-MI based emulation platform (PDF)

Wlodzimierz Wrona , Evatronix S.A., Bielsko-Biala, Poland
Pawel Duc , Evatronix S.A., Bielsko-Biala, Poland
Lukasz Barcik , Evatronix S.A., Bielsko-Biala, Poland
Wojciech Pietrasina , Evatronix S.A., Bielsko-Biala, Poland
pp. 59-63

An analog perspective on device reliability in 32nm high-κ metal gate technology (PDF)

Florian Raoul Chouard , Lehrstuhl für Technische Elektronik, Technische Universität München, Germany
Shailesh More , Lehrstuhl für Technische Elektronik, Technische Universität München, Germany
Michael Fulde , Intel Mobile Communications GmbH, Villach, Austria
Doris Schmitt-Landsiedel , Lehrstuhl für Technische Elektronik, Technische Universität München, Germany
pp. 65-70

Increasing the efficiency of analog OBIST using on-chip compensation of technology variations (PDF)

Daniel Arbet , Department of Microelectronic, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Bratislava, Slovakia
Juraj Brenkus , Department of Microelectronic, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Bratislava, Slovakia
Gabor Gyepes , Department of Microelectronic, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Bratislava, Slovakia
Viera Stopjakova , Department of Microelectronic, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Bratislava, Slovakia
pp. 71-74

A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations (PDF)

Michal Lukaszewicz , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
Tomasz Borejko , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
Witold A. Pleskacz , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
pp. 75-79

Defect-oriented module-level fault diagnosis in digital circuits (PDF)

Sergei Kostin , Department of Computer Engineering, Tallinn University of Technology, Estonia
Raimund Ubar , Department of Computer Engineering, Tallinn University of Technology, Estonia
Jaan Raik , Department of Computer Engineering, Tallinn University of Technology, Estonia
pp. 81-86

Efficient diagnostics algorithms for regular computing structures (PDF)

Miroslav Manik , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia
Elena Gramatova , Slovak University of Technology, Faculty of Informatics and Information Technologies, Bratislava, Slovakia
pp. 87-92

SAT-based analysis of sensitisable paths (PDF)

Matthias Sauer , Albert-Ludwigs-University Freiburg, Georges-Köhler-Allee 051, 79110, Germany
Alexander Czutro , Albert-Ludwigs-University Freiburg, Georges-Köhler-Allee 051, 79110, Germany
Tobias Schubert , Albert-Ludwigs-University Freiburg, Georges-Köhler-Allee 051, 79110, Germany
Stefan Hillebrecht , Albert-Ludwigs-University Freiburg, Georges-Köhler-Allee 051, 79110, Germany
Ilia Polian , University of Passau, Innstraße 43, 94032, Germany
Bernd Becker , Albert-Ludwigs-University Freiburg, Georges-Köhler-Allee 051, 79110, Germany
pp. 93-98

Wireless wafer-level testing of integrated circuits via capacitively-coupled channels (PDF)

Dae Young Lee , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
David D. Wentzloff , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
John P. Hayes , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
pp. 99-104

Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip (PDF)

Thomas Canhao Xu , Department of Information Technology, University of Turku, 20014, Finland
Pasi Liljeberg , Department of Information Technology, University of Turku, 20014, Finland
Hannu Tenhunen , Department of Information Technology, University of Turku, 20014, Finland
pp. 105-110

Decoupling capacitance boosting for on-chip resonant supply noise reduction (PDF)

Jinmyoung Kim , Dept. of Electrical Engineering and Information Systems, The University of Tokyo 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
Toru Nakura , VLSI Design and Education Center, The University of Tokyo 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
Hidehiro Takata , Design Platform Development Division, Renesas Electronics Corporation, The University of Tokyo 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
Koichiro Ishibashi , Design Platform Development Division, Renesas Electronics Corporation, The University of Tokyo 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
Makoto Ikeda , Dept. of Electrical Engineering and Information Systems, The University of Tokyo 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
Kunihiro Asada , Dept. of Electrical Engineering and Information Systems, The University of Tokyo 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
pp. 111-114

An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator (PDF)

Tetsuya Iizuka , Department of Electrical Engineering and Information Systems, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
Kunihiro Asada , Department of Electrical Engineering and Information Systems, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
pp. 115-120

Low-complexity integrated circuit aging monitor (PDF)

Aleksandar Simevski , Brandenburg University of Technology, Konrad-Wachsmann-Allee 1, D-03046 Cottbus, Germany
Rolf Kraemer , Brandenburg University of Technology, Konrad-Wachsmann-Allee 1, D-03046 Cottbus, Germany
Milos Krstic , IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany
pp. 121-125

A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology (PDF)

Jakub Kopanski , Evatronix, Al. Ujazdowskie 18/15, 00-478 Warsaw, POLAND
Witold A. Pleskacz , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662, POLAND
Dariusz Pienkowski , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662, POLAND
pp. 131-134

Fault tolerance of SRAM-based FPGA via configuration frames (PDF)

Farid Lahrach , ICD/LM2S, STMR, UMR CNRS 6279, Université de Technologie de Troyes, 12 rue Marie Curie BP 2060, 10010 Cedex, France
Abderrahim Doumar , ICD/LM2S, STMR, UMR CNRS 6279, Université de Technologie de Troyes, 12 rue Marie Curie BP 2060, 10010 Cedex, France
Eric Chatelet , ICD/LM2S, STMR, UMR CNRS 6279, Université de Technologie de Troyes, 12 rue Marie Curie BP 2060, 10010 Cedex, France
pp. 139-142

A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors (PDF)

Markus Ulbricht , Computer Engineering Group, Brandenburg University of Technology, Cottbus, Germany
Mario Scholzel , Computer Engineering Group, Brandenburg University of Technology, Cottbus, Germany
Tobias Koal , Computer Engineering Group, Brandenburg University of Technology, Cottbus, Germany
Heinrich Theodor Vierhaus , Computer Engineering Group, Brandenburg University of Technology, Cottbus, Germany
pp. 143-146

A chaos-based pseudo-random bit generator implemented in FPGA device (PDF)

Pawel Dabal , Department of Electronic Engineering, Military University of Technology, Warsaw, Poland
Ryszard Pelka , Department of Electronic Engineering, Military University of Technology, Warsaw, Poland
pp. 151-154

Software defined radio - design and implementation of complete platform (PDF)

P. Pawlowski , Division of Signal Processing and Electronic Systems, Chair of Control and System Engineering, Department of Computing, Poznań University of Technology, Poland
A. Dabrowski , Division of Signal Processing and Electronic Systems, Chair of Control and System Engineering, Department of Computing, Poznań University of Technology, Poland
P. Skrzypek , Division of Signal Processing and Electronic Systems, Chair of Control and System Engineering, Department of Computing, Poznań University of Technology, Poland
P. Roszak , Division of Signal Processing and Electronic Systems, Chair of Control and System Engineering, Department of Computing, Poznań University of Technology, Poland
A. Palejko , Division of Signal Processing and Electronic Systems, Chair of Control and System Engineering, Department of Computing, Poznań University of Technology, Poland
T. Walenciak , Division of Signal Processing and Electronic Systems, Chair of Control and System Engineering, Department of Computing, Poznań University of Technology, Poland
M. Mor , Division of Signal Processing and Electronic Systems, Chair of Control and System Engineering, Department of Computing, Poznań University of Technology, Poland
pp. 155-158

Influence of parasitic memory effect on single-cell faults in SRAMs (PDF)

Sandra Irobi , CE Laboratory, EEMCS faculty, Delft University of Technology, The Netherlands
Zaid Al-Ars , CE Laboratory, EEMCS faculty, Delft University of Technology, The Netherlands
Said Hamdioui , CE Laboratory, EEMCS faculty, Delft University of Technology, The Netherlands
Michel Renovell , LIRMM-UMR C5506 CNRS. 161, Rue Ada 34392 Montpellier Cedex 5 France
pp. 159-162

Behavioral model of TRNG based on oscillator rings implemented in FPGA (PDF)

Knut Wold , Gjøvik University College, NISlab, Department of Computer Science and Media Technology, Norway
Slobodan Petrovic , Gjøvik University College, NISlab, Department of Computer Science and Media Technology, Norway
pp. 163-166

Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemC (PDF)

Oliver Stecklina , IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Frank Vater , IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Thomas Basmer , IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Erik Bergmann , IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
Hannes Menzel , Brandenburg University of Technologie, Distributed Systems/Operating Systems Group, 03046 Cottbus, Germany
pp. 167-170

Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations (PDF)

Tsuyoshi Iwagaki , School of Information Science, Japan Advanced Institute of Science and Technology (JAIST), Japan
Kewal K. Saluja , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA
pp. 175-178

Decomposition of multi-output logic function in Reed-Muller spectral domain (PDF)

Stefan Kolodzinski , Pratt & Whitney, Kalisz, Poland
Edward Hrynkiewicz , Institute of Electronics, Silesian University of Technology, Gliwice, Poland
pp. 179-182

Functional enhancements of TMR for power efficient and error resilient ASIC designs (PDF)

Hagen Samrow , Department of Electrical Engineering, University of Rostock, Germany
Claas Cornelius , Department of Electrical Engineering, University of Rostock, Germany
Philipp Gorski , Department of Electrical Engineering, University of Rostock, Germany
Jakob Salzmann , Department of Electrical Engineering, University of Rostock, Germany
Andreas Tockhorn , Department of Electrical Engineering, University of Rostock, Germany
Dirk Timmermann , Department of Electrical Engineering, University of Rostock, Germany
pp. 183-188

A study of path delay variations in the presence of uncorrelated power and ground supply noise (PDF)

A. Todri , LIRMM - University of Montpellier II / CNRS, France
A. Bosio , LIRMM - University of Montpellier II / CNRS, France
L. Dilillo , LIRMM - University of Montpellier II / CNRS, France
P. Girard , LIRMM - University of Montpellier II / CNRS, France
S. Pravossoudovitch , LIRMM - University of Montpellier II / CNRS, France
A. Virazel , LIRMM - University of Montpellier II / CNRS, France
pp. 189-194

Muller C-elements based on minority-3 functions for ultra low voltage supplies (PDF)

Hans Kristian Otnes Berge , Department of Informatics, University of Oslo, P.B. 1080 Blindern, 0316, Norway
Amir Hasanbegovic , Department of Informatics, University of Oslo, P.B. 1080 Blindern, 0316, Norway
Snorre Aunet , Department of Informatics, University of Oslo, P.B. 1080 Blindern, 0316, Norway
pp. 195-200

Power consumption traces realignment to improve differential power analysis (PDF)

G. Di Natale , LIRMM (Université Montpellier II /CNRS UMR 5506), France
M.L. Flottes , LIRMM (Université Montpellier II /CNRS UMR 5506), France
B. Rouzeyre , LIRMM (Université Montpellier II /CNRS UMR 5506), France
M. Valka , LIRMM (Université Montpellier II /CNRS UMR 5506), France
D. Real , DGA CELAR, La Roche Marguerite, 35174 Bruz, France
pp. 201-206

Fault injection analysis of transient faults in clustered VLIW processors (PDF)

L. Sterpone , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
D. Sabena , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
S. Campagna , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
M. Sonza Reorda , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
pp. 207-212

Implementation of Selective Fault Tolerance with conventional synthesis tools (PDF)

Michael Augustin , BTU Cottbus, Computer Science Institute, Erich-Weinert-Straße 1, 03046, Germany
Michael Gossel , Potsdam University, Computer Science Institute, August-Bebel-Straße 89, 14482, Germany
Rolf Kraemer , IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
pp. 213-218

Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair (PDF)

Tobias Koal , Computer Science, Technical University of Brandenburg, Cottbus, Germany
Heinrich Theodor Vierhaus , Computer Science, Technical University of Brandenburg, Cottbus, Germany
pp. 219-224

An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors (PDF)

Abdelmajid Bouajila , Institute for Integrated Systems, Technische Universitaet Muenchen, Arcisstr. 21, Munich, Germany
Johannes Zeppenfeld , Institute for Integrated Systems, Technische Universitaet Muenchen, Arcisstr. 21, Munich, Germany
Walter Stechele , Institute for Integrated Systems, Technische Universitaet Muenchen, Arcisstr. 21, Munich, Germany
Andreas Herkersdorf , Institute for Integrated Systems, Technische Universitaet Muenchen, Arcisstr. 21, Munich, Germany
pp. 225-230

Hardware architecture for packet classification with prefix coloring (PDF)

Viktor Pus , Faculty of Information Technology, Brno University of Technology, Božetěchova 2, Czech Republic
Michal Kajan , Faculty of Information Technology, Brno University of Technology, Božetěchova 2, Czech Republic
Jan Korenek , Faculty of Information Technology, Brno University of Technology, Božetěchova 2, Czech Republic
pp. 231-236

Communication modelling and synthesis for NoC-based systems with real-time constraints (PDF)

Mihkel Tagel , Department of Computer Engineering, Tallinn University of Technology, Estonia
Peeter Ellervee , Department of Computer Engineering, Tallinn University of Technology, Estonia
Thomas Hollstein , Department of Computer Engineering, Tallinn University of Technology, Estonia
Gert Jervan , Department of Computer Engineering, Tallinn University of Technology, Estonia
pp. 237-242

Optimization of message encryption for distributed embedded systems with real-time constraints (PDF)

Ke Jiang , Department of Computer and Information Science, Linköping University, Sweden
Petru Eles , Department of Computer and Information Science, Linköping University, Sweden
Zebo Peng , Department of Computer and Information Science, Linköping University, Sweden
pp. 243-248

Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario (PDF)

Carmen Garcia , Electronic Engineering Department, UPC, BarcelonaTECH, Spain
Antonio Rubio , Electronic Engineering Department, UPC, BarcelonaTECH, Spain
pp. 249-254

Characterization of digital cells for statistical test (PDF)

Fabian Hopsch , Fraunhofer IIS/EAS Dresden, Germany
Michael Lindig , Fraunhofer IIS/EAS Dresden, Germany
Bernd Straube , Fraunhofer IIS/EAS Dresden, Germany
Wolfgang Vermeiren , Fraunhofer IIS/EAS Dresden, Germany
pp. 255-260

A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring (PDF)

Martin Wirnshofer , Institute for Technical Electronics, Technische Universität München, Munich, Germany
Leonhard Heiss , Institute for Technical Electronics, Technische Universität München, Munich, Germany
Georg Georgakos , Infineon Technologies AG, Neubiberg, Germany
Doris Schmitt-Landsiedel , Institute for Technical Electronics, Technische Universität München, Munich, Germany
pp. 261-266

Receiver OEIC using a bipolar translinear loop (PDF)

A. Marchlewski , Institute for Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology, Gusshausstr. 25/354, A-1040, Austria
H. Zimmermann , Institute for Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology, Gusshausstr. 25/354, A-1040, Austria
I. Jonak-Auer , Austriamicrosystems AG, Tobelbaderstr. 30, A-8141 Unterpremstätten, Austria
E. Wachmann , Austriamicrosystems AG, Tobelbaderstr. 30, A-8141 Unterpremstätten, Austria
pp. 267-270

DODT: Increasing requirements formalism using domain ontologies for improved embedded systems development (PDF)

Stefan Farfeleder , Institute of Computer Languages, Vienna University of Technology, Austria
Thomas Moser , CDL Flex, Vienna University of Technology, Austria
Andreas Krall , Institute of Computer Languages, Vienna University of Technology, Austria
Tor Stalhane , Department of Computer and Information Science, Norwegian University of Science and Technology, Norway
Herbert Zojer , Infineon Technologies Austria AG, Austria
Christian Panis , Catena Radio Design bv, the Netherlands
pp. 271-274

Abstract modeling and simulation based selective estimation (PDF)

Yaseen Zaidi , Institute of Computer Technology, Vienna University of Technology, A-1040, Austria
Sumit Adhikari , Institute of Computer Technology, Vienna University of Technology, A-1040, Austria
Christoph Grimm , Institute of Computer Technology, Vienna University of Technology, A-1040, Austria
pp. 275-278

Fast just-in-time translated simulator for ASIP design (PDF)

Zdenek Prikryl , Faculty of Information Technology, Brno University of Technology, Czech Republic
Jakub Kroustek , Faculty of Information Technology, Brno University of Technology, Czech Republic
Tomas Hruska , Faculty of Information Technology, Brno University of Technology, Czech Republic
Dusan Kolar , Faculty of Information Technology, Brno University of Technology, Czech Republic
pp. 279-282

CAD tool for PLL Design (PDF)

Krzysztof Siwiec , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662, POLAND
Tomasz Borejko , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662, POLAND
Witold A. Pleskacz , Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662, POLAND
pp. 283-286

Verification of JPEG2000 encoder based on rate and distortion curve analysis (PDF)

Damian Modrzyk , Evatronix SA, Gliwice, Poland
Michal Staworko , Institute of Telecommunications, Warsaw University of Technology, Poland
pp. 289-292

Failure probability of SRAM-FPGA systems with Stochastic Activity Networks (PDF)

Cinzia Bernardeschi , Department of Information Engineering, University of Pisa, Italy
Luca Cassano , Department of Information Engineering, University of Pisa, Italy
Andrea Domenici , Department of Information Engineering, University of Pisa, Italy
pp. 293-296

Improving performance of robust Self Adaptive Caches by optimizing the switching algorithm (PDF)

Liviu Agnola , Department of Computer Science and Engineering, “Politehnica”, University Timisoara, Romania
Mircea Vladutiu , Department of Computer Science and Engineering, “Politehnica”, University Timisoara, Romania
Mihai Udrescu , Department of Computer Science and Engineering, “Politehnica”, University Timisoara, Romania
Lucian Prodan , Department of Computer Science and Engineering, “Politehnica”, University Timisoara, Romania
pp. 297-300

Sample synchronization of multiple multiplexed DA and AD converters in FPGAs (PDF)

Thilo Ohlemueller , IHP GmbH, Frankfurt (Oder), Germany
Markus Petri , IHP GmbH, Frankfurt (Oder), Germany
pp. 301-304

Hardware efficient design of Variable Length FFT Processor (PDF)

Vinay Gautam , Department of Computer and Information Science, NTNU, Trondheim, Norway-7491
Kailash Chandra Ray , Department of Electrical Engineering, Indian Institute of Technology, Patna, India-800013
Pauline Haddow1 , Department of Computer and Information Science, NTNU, Trondheim, Norway-7491
pp. 309-312

High-performance hardware accelerators for sorting and managing priorities (PDF)

Valery Sklyarov , DETI/IEETA, University of Aveiro, Portugal
Iouliia Skliarova , DETI/IEETA, University of Aveiro, Portugal
Dmitri Mihhailov , Department of computer Engineering, Tallinn University of Technology, Estonia
Alexander Sudnitson , Department of computer Engineering, Tallinn University of Technology, Estonia
pp. 313-318

Precise IPv4/IPv6 packet generator based on NetCOPE platform (PDF)

Jiri Matousek , Faculty of Information Technology, Brno University of Technology, Božetěchova 2, 612 66, Czech Republic
Pavol Korcek , Faculty of Information Technology, Brno University of Technology, Božetěchova 2, 612 66, Czech Republic
pp. 319-324

Effective hash-based IPv6 longest prefix match (PDF)

Jiri Tobola , Faculty of Information Technology, Brno University of Technology, Czech Republic
Jan Korenek , Faculty of Information Technology, Brno University of Technology, Czech Republic
pp. 325-328

Stacking order impact on overall 3D die-to-wafer Stacked-IC cost (PDF)

Mottaqiallah Taouil , Computer Engineering Laboratory, Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
Said Hamdioui , Computer Engineering Laboratory, Delft University of Technology, Faculty of EE, Mathematics and CS, Mekelweg 4, 2628 CD, The Netherlands
pp. 335-340

A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits (PDF)

Yiorgos I. Bontzios , Department of Electrical & Computer Eng., Aristotle Univ. of Thessaloniki, Greece
Michael G. Dimopoulos , Dept. of Electronics, Alexander Technological Educational Inst. of Thessaloniki, Greece
Alkis A. Hatzopoulos , Department of Electrical & Computer Eng., Aristotle Univ. of Thessaloniki, Greece
pp. 341-346

Optimized embedded memory diagnosis (PDF)

M. de Carvalho , Politecnico di Torino, Dip. di Automatica e Informatica, Italy
P. Bernardi , Politecnico di Torino, Dip. di Automatica e Informatica, Italy
M. Sonza Reorda , Politecnico di Torino, Dip. di Automatica e Informatica, Italy
N. Campanelli , NplusT, Semiconductor Application Center, Montecastrilli (TR), Italy
T. Kerekes , NplusT, Semiconductor Application Center, Montecastrilli (TR), Italy
D. Appello , STMicroelectronics, Agrate Brianza (MI), Italy
M. Barone , STMicroelectronics, Agrate Brianza (MI), Italy
V. Tancorre , STMicroelectronics, Agrate Brianza (MI), Italy
M. Terzi , STMicroelectronics, Agrate Brianza (MI), Italy
pp. 347-352

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling (PDF)

L. B. Zordan , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34095 Cedex 5, France
A. Bosio , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34095 Cedex 5, France
L. Dilillo , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34095 Cedex 5, France
P. Girard , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34095 Cedex 5, France
S. Pravossoudovitch , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34095 Cedex 5, France
A. Virazel , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34095 Cedex 5, France
N. Badereddine , Infineon Technologies France, 2600, route des Crêtes - 06560 Sophia-Antipolis, France
pp. 353-358

On using a SPICE-like TSTAC™ eFlash model for design and test (PDF)

P.-D. Mauroux , LIRMM - University of Montpellier / CNRS, France
A. Virazel , LIRMM - University of Montpellier / CNRS, France
A. Bosio , LIRMM - University of Montpellier / CNRS, France
L. Dilillo , LIRMM - University of Montpellier / CNRS, France
P. Girard , LIRMM - University of Montpellier / CNRS, France
S. Pravossoudovitch , LIRMM - University of Montpellier / CNRS, France
B. Godard , ATMEL, Embedded Non-Volatile Memory Group, Rousset, France
G. Festes , ATMEL, Embedded Non-Volatile Memory Group, Rousset, France
L. Vachez , ATMEL, Embedded Non-Volatile Memory Group, Rousset, France
pp. 359-364

Statistical analysis of 6T SRAM data retention voltage under process variation (PDF)

Elena I. Vatajelu , Department of Electronic Engineering, Universitat Politecnica de Catalunya (UPC), Barcelona, Spain
Joan Figueras , Department of Electronic Engineering, Universitat Politecnica de Catalunya (UPC), Barcelona, Spain
pp. 365-370

Decreasing test time by scan chain reorganization (PDF)

Pavel Bartos , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66, Czech Republic
Zdenek Kotasek , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66, Czech Republic
Jan Dohnal , ON Design Czech s.r.o., (On Semiconductor), Videnska 204/125, Brno, 619 00, Czech Republic
pp. 371-374

Max-Fill: A method to generate high quality delay tests (PDF)

X. Fan , Department of ECE, University of Iowa, USA
S.M. Reddy , Department of ECE, University of Iowa, USA
I. Pomeranz , School of ECE, Purdue University, West Lafayette, USA
pp. 375-380

Measurement point selection for in-operation wear-out monitoring (PDF)

Urban Ingelsson , Department of Computer and Information Science, Linköpings universitet, Sweden
Shih-Yen Chang , Department of Computer and Information Science, Linköpings universitet, Sweden
Erik Larsson , Department of Computer and Information Science, Linköpings universitet, Sweden
pp. 381-386

Test vector overlapping based compression tool for narrow test access mechanism (PDF)

Jiri Jenicek , Technical University Liberec, Hálkova 6, 461 17 Liberec I, Czech Republic
Martin Rozkovec , Technical University Liberec, Hálkova 6, 461 17 Liberec I, Czech Republic
Ondrej Novak , Technical University Liberec, Hálkova 6, 461 17 Liberec I, Czech Republic
pp. 387-392

A 20 pJ/b (10 µW) digital receiver based on a new modulation (SAS) for retinal prosthesis application (PDF)

F. Goodarzy , Department of Electrical and Electronic Engineering and NICTA, University of Melbourne, Parkville, Victoria 3010, Australia
E. Skafidas , Department of Electrical and Electronic Engineering and NICTA, University of Melbourne, Parkville, Victoria 3010, Australia
pp. 393-394

Advanced fault tolerant bus for multicore system implemented in FPGA (PDF)

Martin Straka , Brno University of Technology, Bozetechova 2, 612 66, Czech Republic
Jan Kastil , Brno University of Technology, Bozetechova 2, 612 66, Czech Republic
Jaroslav Novotny , Brno University of Technology, Bozetechova 2, 612 66, Czech Republic
Zdenek Kotasek , Brno University of Technology, Bozetechova 2, 612 66, Czech Republic
pp. 397-398

Validation and optimization of TMR protections for circuits in radiation environments (PDF)

O. Ruano , Universidad Antonio Nebrija, Madrid, Spain
J.A. Maestro , Universidad Antonio Nebrija, Madrid, Spain
P. Reviriego , Universidad Antonio Nebrija, Madrid, Spain
pp. 399-400

Reduction of FPGA resources for regular expression matching by relation similarity (PDF)

Vlastimil Kosar , Brno University of Technology, Bozetechova 2, 612 66, Czech Republic
Jan Korenek , Brno University of Technology, Bozetechova 2, 612 66, Czech Republic
pp. 401-402

Low-power quadrature VCO design for medical implant communication service (PDF)

Jeong Ki Kim , Bradley Department of Electrical and Computer Eng., Virginia Tech, Blacksburg, 24061 USA
Jihoon Jeong , Bradley Department of Electrical and Computer Eng., Virginia Tech, Blacksburg, 24061 USA
Dong Sam Ha , Bradley Department of Electrical and Computer Eng., Virginia Tech, Blacksburg, 24061 USA
Hyung-soo Lee , Green Computing Research Division, Electronics and Telecommunications Research Institute, (ETRI) Daejeon, 307-700 KOREA
pp. 403-404

Current sensing methodology for completion detection in self-timed systems (PDF)

Lukas Nagy , Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia
Viera Stopjakova , Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia
pp. 405-406

A wireless ECG sensor node based on Huffman data encoder (PDF)

Uros Pesovic , Technical Faculty Čačak, University of Kragujevac, Serbia
Sinisa Randic , Technical Faculty Čačak, University of Kragujevac, Serbia
Zoran Stamenkovic , IHP, Frankfurt (Oder), Germany
pp. 411-412

Advanced rectifier and driver for analog VU meter (PDF)

Martin Pospisilik , Faculty of Applied Informatics, Tomas Bata University in Zlin, Czech Republic
Milan Adamek , Faculty of Applied Informatics, Tomas Bata University in Zlin, Czech Republic
pp. 413-414

Automatic property generation for the formal verification of bus bridges (PDF)

Mathias Soeken , University of Bremen, 28359, Germany
Ulrich Kuhne , LSV ENS de Cachan, 94235, France
Martin Freibothe , OneSpin Solutions GmbH, 80339 Munich, Germany
Gorschwin Fe , University of Bremen, 28359, Germany
Rolf Drechsler , University of Bremen, 28359, Germany
pp. 417-422

Probabilistic equivalence checking based on high-level decision diagrams (PDF)

Anton Karputkin , Tallinn University of Technology, Estonia
Raimund Ubar , Tallinn University of Technology, Estonia
Mati Tombak , Tallinn University of Technology, Estonia
Jaan Raik , Tallinn University of Technology, Estonia
pp. 423-428

Proof certificates and non-linear arithmetic constraints (PDF)

S. Kupferschmid , University of Freiburg, Germany
B. Becker , University of Freiburg, Germany
T. Teige , University of Oldenburg, Germany
M. Franzle , University of Oldenburg, Germany
pp. 429-434

TLM protocol compliance checking at the Electronic System Level (PDF)

Mohamed Bawadekji , Institute of Computer Science, University of Bremen, 28359, Germany
Daniel Grosse , Institute of Computer Science, University of Bremen, 28359, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 435-440

Error recovery technique for coarse-grained reconfigurable architectures (PDF)

Muhammad Moazam Azeem , Orange Labs, Issy les Moulineaux, France
Stanislaw J. Piestrak , IRISA/INRIA, Lannion, France
Olivier Sentieys , Univ of Rennes 1/IRISA, Lannion, France
Sebastien Pillement , Univ of Rennes 1/IRISA, Lannion, France
pp. 441-446

Behavior of CMOS polymorphic circuits in high temperature environment (PDF)

Richard Ruzicka , Faculty of Information Technology, Brno University of Technology, Czech Republic
Vaclav Simek , Faculty of Information Technology, Brno University of Technology, Czech Republic
Lukas Sekanina , Faculty of Information Technology, Brno University of Technology, Czech Republic
pp. 447-452

Dynamic placement applications into Self Adaptive network on FPGA (PDF)

Petr Honzik , ČIP plus, s.r.o., Milínská 130, Příbram, 26101, Czech Republic
Jiri Kadlec , Department of Signal Processing, UTIA AV CR v.v.i., Pod vodárenskou věží 4, Praha 8, 182 08, Czech Republic
pp. 453-456

Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms (PDF)

Andre Seffrin , Center for Advanced Security Research Darmstadt, Germany
Sorin A. Huss , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
pp. 457-462
99 ms
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