The Community for Technology Leaders
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (2009)
Liberec, Czech Republic
Apr. 15, 2009 to Apr. 17, 2009
ISBN: 978-1-4244-3341-4
TABLE OF CONTENTS
Papers

Sponsors (PDF)

pp. 278-281

Sponsors (PDF)

pp. 285

Title page (PDF)

pp. i

Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS (PDF)

Georges Gielen , Katholieke Universiteit Leuven, Departement Elektrotechniek, ESAT-MICAS, Kardinaal Mercierlaan 94, B-3001, Belgium
pp. 1

Cognitive self-adaptive computing and communication systems: Test, control and adaptation (PDF)

Abhijit Chatterjee , Georgia Institute of Technology, 777 Atlantic Drive NW, Atlanta, USA
pp. 2

Challenges for test and design for test (PDF)

Anton Chichkov , On Semiconductor Corp, Oudenaarde, Belgium
pp. 3

An SOC platform for ADC test and measurement (Abstract)

Thomas Fleischmann , Department of Electronic and Computer Engineering (Mixed-Signal Integrated Circuit Group), University of Limerick, Ireland
Brendan Mullane , Department of Electronic and Computer Engineering (Mixed-Signal Integrated Circuit Group), University of Limerick, Ireland
Vincent O'Brien , Department of Electronic and Computer Engineering (Mixed-Signal Integrated Circuit Group), University of Limerick, Ireland
Ciaran MacNamee , Department of Electronic and Computer Engineering (Mixed-Signal Integrated Circuit Group), University of Limerick, Ireland
pp. 4-7

A scheme of logic self repair including local interconnects (Abstract)

T. Koal , Brandenburg University of Technology Cottbus, Computer Science Institute, P. O. Box 10 13 44, D-03013, Germany
H. T. Vierhaus , Brandenburg University of Technology Cottbus, Computer Science Institute, P. O. Box 10 13 44, D-03013, Germany
D. Scheit , Brandenburg University of Technology Cottbus, Computer Science Institute, P. O. Box 10 13 44, D-03013, Germany
pp. 8-11

Investigating the linearity of MOSFET-only switched-capacitor ?S modulators under low-voltage condition (Abstract)

Farhad Alibeygi Parsan , Electrical Engineering Department, Iran University of Science&Technology (IUST), Tehran, Iran
Ahmad Ayatollahi , Electrical Engineering Department, Iran University of Science&Technology (IUST), Tehran, Iran
Adib Abrishamifar , Electrical Engineering Department, Iran University of Science&Technology (IUST), Tehran, Iran
pp. 12-15

Comparison of different test strategies on a mixed-signal circuit (Abstract)

Viera Stopjakova , Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia
Ronny Vanhooren , Test Methodology Team, ON Semiconductor, Oudenaarde, Belgium
Anton Chichkov , Test Methodology Team, ON Semiconductor, Oudenaarde, Belgium
Juraj Brenkus , Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia
pp. 16-19

Case Study : A class E power amplifier for ISO-14443A (Abstract)

Wim Aerts , ESAT-COSIC, K.U.Leuven, Kasteelpark Arenberg 10 bus 2446, B-3001 Heverlee, Belgium
Elke De Mulder , ESAT-COSIC, K.U.Leuven, Kasteelpark Arenberg 10 bus 2446, B-3001 Heverlee, Belgium
Ingrid Verbauwhede , ESAT-COSIC, K.U.Leuven, Kasteelpark Arenberg 10 bus 2446, B-3001 Heverlee, Belgium
Bart Preneel , ESAT-COSIC, K.U.Leuven, Kasteelpark Arenberg 10 bus 2446, B-3001 Heverlee, Belgium
Guy Vandenbosch , ESAT-TELEMIC, K.U.Leuven, Kasteelpark Arenberg 10 bus 2446, B-3001 Heverlee, Belgium
pp. 20-23

Fast congestion-aware timing-driven placement for island FPGA (Abstract)

Jinpeng Zhao , EDA Lab, Department of Computer Science, Tsinghua University, Beijing 100084, China
Qiang Zhou , EDA Lab, Department of Computer Science, Tsinghua University, Beijing 100084, China
Yici Cai , EDA Lab, Department of Computer Science, Tsinghua University, Beijing 100084, China
pp. 24-27

Analysis and optimization of ring oscillator using sub-feedback scheme (Abstract)

Fu-Chien Tsai , Graduate Institute of Electrical Engineering, National Taipei University, Taiwan
Hong-Yi Huang , Graduate Institute of Electrical Engineering, National Taipei University, Taiwan
pp. 28-29

Improve clock gating through power-optimal enable function selection (Abstract)

Yunjian Jiang , Magma Design Automation, Inc., USA
Juanjuan Chen , Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
Xing Wei , Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
Qiang Zhou , Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
pp. 30-33

An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions (Abstract)

Edward Hrynkiewicz , Institute of Electronics, Silesian University of Technology, Gliwice, Poland
Stefan Kolodzinski , Pratt&Whitney, Kalisz, Poland
pp. 34-37

A fast untestability proof for SAT-based ATPG (Abstract)

Daniel Tille , Institute of Computer Science, University of Bremen, 28359, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 38-43

The impact of EFSM composition on functional ATPG (Abstract)

Davide Bresolin , Department of Computer Science, University of Verona, Italy
Tiziano Villa , Department of Computer Science, University of Verona, Italy
Graziano Pravadelli , Department of Computer Science, University of Verona, Italy
Giuseppe Di Guglielmo , Department of Computer Science, University of Verona, Italy
Franco Fummi , Department of Computer Science, University of Verona, Italy
pp. 44-49

An efficient fault simulation technique for transition faults in non-scan sequential circuits (Abstract)

S. Pravossoudovich , LIRMM, Université de Montpellier 2/CNRS, Montpellier, France
M. Sonza Reorda , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
P. Bernardi , Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy
P. Girard , LIRMM, Université de Montpellier 2/CNRS, Montpellier, France
A. Bosio , LIRMM, Université de Montpellier 2/CNRS, Montpellier, France
pp. 50-55

Self-timed full adder designs based on hybrid input encoding (Abstract)

P. Balasubramanian , School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, United Kingdom
C. Brej , School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, United Kingdom
D.A. Edwards , School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, United Kingdom
pp. 56-61

Optimization concepts for self-healing asynchronous circuits (Abstract)

Werner Friesenbichler , RUAG Aerospace Austria GmbH, Austria
Martin Delvai , Institute of Computer Engineering, Vienna University of Technology, Austria
Thomas Panhofer , RUAG Aerospace Austria GmbH, Austria
pp. 62-67

Asynchronous two-level logic of reduced cost (Abstract)

Igor Lemberski , Baltic International Academy, Riga, Latvia
Petr Fiser , Dept. of Computer Science&Engineering, Czech Technical University in Prague, Czech Republic
pp. 68-73

Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS (Abstract)

Kurt Schweiger , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Austria, 1040
Horst Zimmermann , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Austria, 1040
Heimo Uhrmann , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Austria, 1040
pp. 74-77

Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS (Abstract)

Tomasz Borejko , Institute of Microelectronics&Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
Jacek Gradzki , Institute of Microelectronics&Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
Witold A. Pleskacz , Institute of Microelectronics&Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND
pp. 78-83

BIST assisted wideband digital compensation for MB-UWB transmitters (Abstract)

Abhijit Chatterjee , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
Shreyas Sen , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
Shyam Kumar Devarakond , School of Electrical Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
pp. 84-89

Architecture model for approximate palindrome detection (Abstract)

Matej Lexa , Faculty of Informatics, Masaryk University, Botanická 68a, Brno, 602 00, Czech Republic
Tomas Martinek , Faculty of Information Technology, Brno University of Technology, Bo¿et¿chova 2, 612 66, Czech Republic
Jan Vozenilek , Faculty of Information Technology, Brno University of Technology, Bo¿et¿chova 2, 612 66, Czech Republic
pp. 90-95

Packet header analysis and field extraction for multigigabit networks (Abstract)

Petr Kobiersky , Faculty of Information Technology, Brno University of Technology, Bo¿et¿chova 2, 612 66, Czech Republic
Libor Polcak , CESNET z. s. p. o., Zikova 4, 160 00, Prague, Czech Republic
Jan Korenek , Faculty of Information Technology, Brno University of Technology, Bo¿et¿chova 2, 612 66, Czech Republic
pp. 96-101

A symbolic RTL synthesis for LUT-based FPGAs (Abstract)

Stanislaw Deniziak , Dept. of Computer Engineering, Cracow University of Technology, Warszawska 24, 31-155, Poland
Mariusz Wisniewski , Dept of Computer Science, Kielce University of Technology, Al. 1000-lecia PP 7, 25-314, Poland
pp. 102-107

Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing (Abstract)

Yiorgos Sfikas , University of Ioannina, Department of Computer Science, P.O. Box 1186, 45110, Greece (Hellas)
Yiorgos Tsiatouhas , University of Ioannina, Department of Computer Science, P.O. Box 1186, 45110, Greece (Hellas)
pp. 108-113

Using 3-valued memory representation for state space reduction in embedded assembly code model checking (Abstract)

Martin Horauer , Institute of Embedded Systems, University of Applied Sciences Technikum Wien, Höchstädtplatz 5, A-1200 Vienna, Austria
Bastian Schlich , Embedded Software Laboratory - Informatik 11, RWTH Aachen University, Ahornstraße 55, D-52074, Germany
Thomas Reinbacher , Institute of Embedded Systems, University of Applied Sciences Technikum Wien, Höchstädtplatz 5, A-1200 Vienna, Austria
pp. 114-119

An on-line testing scheme for repairing purposes in Flash memories (Abstract)

Jean-Michel Portal , Université de Provence (Aix-Marseille I), IM2NP-UMR CNRS 6242, 13451 Cedex 20, France
Hassen Aziza , Université de Provence (Aix-Marseille I), IM2NP-UMR CNRS 6242, 13451 Cedex 20, France
Olivier Ginez , Université de Provence (Aix-Marseille I), IM2NP-UMR CNRS 6242, 13451 Cedex 20, France
pp. 120-123

Power devices current monitoring using horizontal and vertical magnetic force sensor (Abstract)

Martin Donoval , Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia
Juraj Marek , Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia
Martin Daricek , Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia
Viera Stopjakova , Department of Microelectronics, Slovak University of Technology, Bratislava, Slovakia
pp. 124-127

Measurement of power supply noise tolerance of self-timed processor (Abstract)

Makoto Ikeda , Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
Kunihiro Asada , Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
Toru Nakura , VLSI Design and Education Center (VDEC), 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan
Taku Sogabe , Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
pp. 128-131

Test scheme for switched-capacitor circuits by digital analyses (Abstract)

Yun-Che Wen , Department of Aeronautics and Astronautics, National Cheng Kung University, Aerospace Science and Technology Research Center, National Cheng Kung University, No.1, University Road,
pp. 132-135

Structural test of programmed FPGA circuits (Abstract)

Martin Rozkovec , Institute of Information technologies and electronics, Technical University in Liberec, Faculty of Mechatronics, Czech Republic
Ondrej Novak , Institute of Information technologies and electronics, Technical University in Liberec, Faculty of Mechatronics, Czech Republic
pp. 136-139

Low voltage precharge CMOS logic (Abstract)

Omid Mirmotahari , Microelectronic systems, Department of Informatics, University of Oslo, Norway
Yngvar Berg , Microelectronic systems, Department of Informatics, University of Oslo, Norway
pp. 140-143

MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio (Abstract)

Arkadiusz W. Luczyk , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland
Michal Ufnal , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland
Peter Malik , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia
Marcel Balaz , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia
Witold A. Pleskacz , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland
pp. 144-147

Effective mars rover platform design with Hardware / Software co-design (Abstract)

Gyula Horvath , Department of Electron Devices, Budapest University of Technology and Economics, BUTE, Hungary
Gabor Marosy , Department of Electron Devices, Budapest University of Technology and Economics, BUTE, Hungary
Zoltan Kovacs , Department of Electron Devices, Budapest University of Technology and Economics, BUTE, Hungary
pp. 148-151

On the role of the power supply as an entry for common cause faults (Abstract)

Peter Tummeltshammer , Vienna University of Technology - Embedded Computing Systems Group, Treitlstrasse 3, A-1040, Austria
Andreas Steininger , Vienna University of Technology - Embedded Computing Systems Group, Treitlstrasse 3, A-1040, Austria
pp. 152-157

An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions (Abstract)

F. Azais , LIRMM, CNRS/Univ. Montpellier II, 161 rue Ada - 34392 Cedex - France
Y. Bertrand , LIRMM, CNRS/Univ. Montpellier II, 161 rue Ada - 34392 Cedex - France
M. Renovell , LIRMM, CNRS/Univ. Montpellier II, 161 rue Ada - 34392 Cedex - France
pp. 158-163

Effective BIST for crosstalk faults in interconnects (Abstract)

Andrzej Hlawiczka , Institute of Electronics, Silesian University of Technology, Gliwice, Poland
Tomasz Rudnicki , Institute of Electronics, Silesian University of Technology, Gliwice, Poland
Krzysztof Gucwa , Institute of Electronics, Silesian University of Technology, Gliwice, Poland
Tomasz Garbolino , Institute of Electronics, Silesian University of Technology, Gliwice, Poland
pp. 164-169

MTPP - Modular Traffic Processing Platform (Abstract)

Sven Ubik , CESNET, Czech Republic
Jiri Halak , CESNET, Czech Republic
pp. 170-173

Simulation and planning method for on-chip power distribution (Abstract)

Vincent Bars , Chameleon Systems Inc., 7848 Pineville Circle, Castro Valley, CA 94552, USA
Qing K. Zhu , Chameleon Systems Inc., 7848 Pineville Circle, Castro Valley, CA 94552, USA
pp. 174-177

Experience in Virtual Testing of RSD cyclic A/D converters (Abstract)

Jiri Jakovenko , Faculty of Electrical Engineering, Czech Technical University in Prague, Czech Republic
Ondrej Subrt , ASICentrum, Prague, Czech Republic
Miloslav Kubar , ASICentrum, Prague, Czech Republic
Pravoslav Martinek , Faculty of Electrical Engineering, Czech Technical University in Prague, Czech Republic
pp. 178-181

A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS (Abstract)

Horst Zimmermann , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Austria
Kurt Schweiger , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Austria
Franz Schlogl , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Austria
Heimo Uhrmann , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Austria
pp. 182-185

0.5V 160-MHz 260uW all digital phase-locked loop (Abstract)

Hong-Yi Huang , Graduate Institute of Electrical Engineering, National Taipei University, Taiwan
Wei-Bin Yang , Department of Electrical Engineering, Tamkang University, Taiwan
Kuo-Hsing Cheng , Department of Electrical Engineering, National Central University, Taiwan
Jen-Chieh Liu , Department of Electrical Engineering, National Central University, Taiwan
pp. 186-193

0.18 (Abstract)

Nemai C. Karmakar , Dept. of Electrical and Computer Systems Engineering, Monash University, Australia
H. L. Kao , Dept. of Electronic Engineering, Chang Gung Univ., Tao-Yuan, Taiwan
L. C. Chang , Dept. of Materials Engineering, Mingchi University of Technology, Taipei, Taiwan
C. H. Yang , Dept. of Electronic Engineering, Chang Gung Univ., Tao-Yuan, Taiwan
Jeffrey S. Fu , Dept. of Electronic Engineering, Chang Gung Univ., Tao-Yuan, Taiwan
Y. C. Chang , Dept. of Electronic Engineering, Chang Gung Univ., Tao-Yuan, Taiwan
C. H. Kao , Dept. of Accounting Information, Takming College, Taipei, Taiwan
pp. 194-197

Hardware solution of chaos based image encryption (Abstract)

Karel Vlcek , Department of Applied Informatics, Tomas Bata University in Zlin, Nas Stranemi 4511, 760 05 Czech Republic
Jiri Giesl , Department of Applied Informatics, Tomas Bata University in Zlin, Nas Stranemi 4511, 760 05 Czech Republic
Ladislav behal , Department of Applied Informatics, Tomas Bata University in Zlin, Nas Stranemi 4511, 760 05 Czech Republic
pp. 198-201

Diagnosis of faulty units in regular graphs under the PMC model (Abstract)

E. Gramatova , Institute of Informatics of the Slovak Academy of Sciences, Bratislava, Slovakia
M. Manik , Institute of Informatics of the Slovak Academy of Sciences, Bratislava, Slovakia
pp. 202-205

Contactless characterization of MEMS devices using optical microscopy (Abstract)

Gyorgy Bognar , Department of Electron Devices, Technical University of Budapest, Hungary
Andras Timar , Department of Electron Devices, Technical University of Budapest, Hungary
pp. 210-213

A comprehensive approach for soft error tolerant Four State Logic (Abstract)

Werner Friesenbichler , RUAG Aerospace Austria GmbH, Austria
Martin Delvai , Vienna University of Technology, Embedded Computing Systems Group, Austria
Thomas Panhofer , RUAG Aerospace Austria GmbH, Austria
pp. 214-217

High-level symbolic simulation for automatic model extraction (Abstract)

Katell Morin-Allory , TIMA Laboratory, Grenoble INP, UJF, CNRS, France
Dominique Borrione , TIMA Laboratory, Grenoble INP, UJF, CNRS, France
Florent Ouchet , TIMA Laboratory, Grenoble INP, UJF, CNRS, France
Laurence Pierre , TIMA Laboratory, Grenoble INP, UJF, CNRS, France
pp. 218-221

Global parametric faults identification with the use of Differential Evolution (Abstract)

P. Jantos , Silesian University of Technology Gliwice, POLAND
D. Grzechca , Silesian University of Technology Gliwice, POLAND
J. Rutkowski , Silesian University of Technology Gliwice, POLAND
pp. 222-225

Forward and backward guarding in early output logic (Abstract)

Doug Edwards , School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, UK
Charlie Brej , School of Computer Science, The University of Manchester, Oxford Road, M13 9PL, UK
pp. 226-229

Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories (Abstract)

Bogdan J. Falkowski , School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Grzegorz Borowik , Institute of Telecommunications, Warsaw University of Technology, Poland
Tadeusz Luba , Institute of Telecommunications, Warsaw University of Technology, Poland
pp. 230-233

Contention-avoiding custom topology generation for network-on-chip (Abstract)

Robert Tomaszewski , Dept. of Computer Science, Kielce University of Technology, Poland
Stanislaw Deniziak , Dept. of Computer Engineering, Cracow University of Technology, Poland
pp. 234-237

Enhanced LEON3 core for superscalar processing (Abstract)

Witold A. Pleskacz , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662, Poland
Arkadiusz W. Luczyk , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662, Poland
Krzysztof Marcinek , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662, Poland
pp. 238-241

Ultra low-voltage switched current mirror (Abstract)

Yngvar Berg , Microelectronic systems, Department of Informatics, University of Oslo, Norway
Omid Mirmotahari , Microelectronic systems, Department of Informatics, University of Oslo, Norway
pp. 242-245

Self-timed thermal sensing and monitoring of multicore systems (Abstract)

Pasi Liljeberg , Department of Information Technology, University of Turku, Finland
Kameswar Rao Vaddina , Department of Information Technology, University of Turku, Finland
Ethiopia Nigussie , Department of Information Technology, University of Turku, Finland
Juha Plosila , Department of Information Technology, University of Turku, Finland
pp. 246-251

A CMOS bio-impedance measurement system (Abstract)

Adoracion Rueda , Instituto de Microelectrónica de Sevilla (IMSE), Centro Nacional de Microelectrónica (CNM-CSIC), Universidad de Sevilla, Av. Américo Vespucio s/n. 41092. SPAIN
Alberto Yufera , Instituto de Microelectrónica de Sevilla (IMSE), Centro Nacional de Microelectrónica (CNM-CSIC), Universidad de Sevilla, Av. Américo Vespucio s/n. 41092. SPAIN
pp. 252-257

An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs (Abstract)

M. Bruno , Politecnico di Torino, Italy
F. Abate , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
L. Ciganda , Universidad de la Republica Uruguay, Montevideo, Uruguay
P. Bernardi , Politecnico di Torino, Italy
pp. 258-263

Comprehensive bridging fault diagnosis based on the SLAT paradigm (Abstract)

Y. Benabboud , Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, LIRMM - Université Montpellier II / CNRS, France
L. Bouzaida , STMICROELECTRONICS, Crolles, France
L. Dilillo , Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, LIRMM - Université Montpellier II / CNRS, France
S. Pravossoudovitch , Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, LIRMM - Université Montpellier II / CNRS, France
I. Izaute , STMICROELECTRONICS, Crolles, France
A. Bosio , Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, LIRMM - Université Montpellier II / CNRS, France
A. Virazel , Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, LIRMM - Université Montpellier II / CNRS, France
P. Girard , Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, LIRMM - Université Montpellier II / CNRS, France
pp. 264-269

Round-level concurrent error detection applied to Advanced Encryption Standard (Abstract)

Mircea Vladutiu , ¿Politehnica¿ University of Timisoara, Vasile Parvan 2, 1900, Romania
Flavius Opritoiu , ¿Politehnica¿ University of Timisoara, Vasile Parvan 2, 1900, Romania
Lucian Prodan , ¿Politehnica¿ University of Timisoara, Vasile Parvan 2, 1900, Romania
Mihai Udrescu , ¿Politehnica¿ University of Timisoara, Vasile Parvan 2, 1900, Romania
pp. 270-275

Author index (PDF)

pp. 276-277
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