The Community for Technology Leaders
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (2008)
Bratislava, Slovakia
Apr. 16, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-2276-0
TABLE OF CONTENTS
Papers

The Guiding Light for Chip Testing (PDF)

Sandip Kundu , University of Massachusetts, Amherst, Department of Electrical&Computer Engineering, USA
pp. 1

The Wall Ahead is Made of Rubber (PDF)

Krisztian Flautner , Research&Development, ARM Ltd., Cambridge, United Kingdom
pp. 1

The Quest for Test: Will Redundancy Cover All? (PDF)

Hans Manhaeve , Q-Star Test nv, Lieven Bauwensstraat 20, B-8200 Brugge, Belgium
pp. 1

Deep-Submicron MOS Transistor Matching: A Case Study (Abstract)

Dimitar P. Dimitrov , Melexis-Bulgaria Ltd, ddi@melexis.com
pp. 1-4

Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology (Abstract)

Havard Pedersen Alstad , Dept. of Informatics, University of Oslo, P.b. 1080 Blindern, 0316 Oslo, Norway, Email: haavarpa@ifi.uio.no
Snorre Aunet , Dept. of Informatics, University of Oslo, P.b. 1080 Blindern, 0316 Oslo, Norway, Email: aunet@ieee.org
pp. 1-4

Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation (Abstract)

Havard Pedersen Alstad , Dept. of Informatics, University of Oslo, P.B. 1080 Blindern, 0316 Oslo, Norway
Snorre Aunet , Dept. of Informatics, University of Oslo, P.B. 1080 Blindern, 0316 Oslo, Norway
pp. 1-2

Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures (Abstract)

Arkadiusz W. Luczyk , Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, ul. Koszykowa 65, 00-661 Warsaw, Poland, A.Luczyk@elka.pw.edu.pl
Artur L. Sobczyk , Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, ul. Koszykowa 65, 00-661 Warsaw, Poland, Twinteq, ul. Ostrobramska 101, 04-041, Warsaw, Poland,
Witold A. Pleskacz , Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, ul. Koszykowa 65, 00-661 Warsaw, Poland, W.Pleskacz@imio.pw.edu.pl
pp. 1-4

Computation of a nonlinear squashing function in digital neural networks (Abstract)

Vladimir Havel , Department of Computer Science, VSB - Technical University of Ostrava, 17. listopadu 15, 708 33, Ostrava-Poruba, Czech Republic, vladimir.havel@vsb.cz
Karel Vlcek , Department of Computer Science, VSB - Technical University of Ostrava, 17. listopadu 15, 708 33, Ostrava-Poruba, Czech Republic, karel.vlcek@vsb.cz
pp. 1-4

An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs (Abstract)

Mariusz Wisniewski , Dept of Computer Science, Kielce University of Technology, Al. 1000-lecia PP 7, 25-314 Kielce, Poland, e-mail: kinmw@eden.tu.kielce.pl
Stanislaw Deniziak , Dept. of Computer Engineering, Cracow University of Technology, Warszawska 24, 31-155 Cracow, Poland, e-mail: S.Deniziak@computer.org
pp. 1-4

Portable Measurement Equipment for Continuous Biomedical Monitoring using Microelectrodes (Abstract)

V. Stopjakova , Department of Microelectronics, Slovak University of Technology, Ilkovic¿ova 3, SK-812 19 Bratislava, Slovakia
L. Majer , Department of Microelectronics, Slovak University of Technology, Ilkovic¿ova 3, SK-812 19 Bratislava, Slovakia, E-mail: libor.majer@stuba.sk
pp. 1-4

Design of Erasure Codes for Digital Multimedia Transmitting (Abstract)

K. V. Shinkarenko , Tomas Bata University, Nad Stranemi 4511, Zlin 76001 Czech Republic
K. Vlcek , Tomas Bata University, Nad Stranemi 4511, Zlin 76001 Czech Republic
pp. 1-4

Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits (Abstract)

F. Vargas , PUCRS, Brazil, vargas@computer.org
J. Semiao , Univ. of Algarve, Portugal, jsemiao@ualg.pt
I. Teixeira , IST / INESC-ID, Portugal
J. J. Rodriguez-Andina , Univ. of Vigo, Spain, jjrdguez@uvigo.es
P. Teixeira , IST / INESC-ID, Portugal, paulo.teixeira@ist.utl.pt
M. Santos , IST / INESC-ID, Portugal
pp. 1-4

A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations (Abstract)

Witold A. Pleskacz , Institute of Microelectronics&Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND, e-mail: W.Pleskacz@imio.pw.edu.pl
Tomasz Borejko , Institute of Microelectronics&Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa, POLAND, e-mail: T.Borejko, W.Pleskacz@imio.pw.edu.pl, Inside
pp. 1-6

Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling (Abstract)

A. Andrei , Embedded Systems Laboratory, Department of Computer and Information Science, Linkoping University, Sweden, SE-581 83, Email: alean@ida.liu.se
P. Eles , Embedded Systems Laboratory, Department of Computer and Information Science, Linkoping University, Sweden, SE-581 83, Email: petel@ida.liu.se
Z. Peng , Embedded Systems Laboratory, Department of Computer and Information Science, Linkoping University, Sweden, SE-581 83, Email: zebpe@ida.liu.se
M. Bao , Embedded Systems Laboratory, Department of Computer and Information Science, Linkoping University, Sweden, SE-581 83, Email: minba@ida.liu.se
pp. 1-6

Gain reduction by gate-leakage currents in regulated cascodes (Abstract)

H. Zimmermann , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/354, 1040 Vienna, Austria
F. Schlogl , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/354, 1040 Vienna, Austria
K. Schneider-Hornstein , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/354, 1040 Vienna, Austria
pp. 1-4

A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles (Abstract)

D. Zaum , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany, zaum@ims.uni-hannover.de
E. Barke , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany, eb@ims.uni-hannover.de
T. Jambor , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany, jambor@ims.uni-hannover.de
M. Olbrich , Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany, olbrich@ims.uni-hannover.de
pp. 1-5

Continuous-Time Common-Mode Feedback Circuit for Applications with Large Output Swing and High Output Impedance (Abstract)

Weixun Yan , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/E354, 1040 Vienna, Austria, Email: yweixun@emst.tuwien.ac.at
Horst Zimmermann , Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/E354, 1040 Vienna, Austria, Email: horst.zimmermann@ieee.org
pp. 1-5

A Spread-Spectrum Clock Generator Using Fractional (Abstract)

Kuo-Hsing Cheng , Department of Electrical Engineering, National Central University, Jung-Li, Taoyuan, Taiwan, R.O.C., Email: cheng@ee.ncu.edu.tw
Yu-Lung Lo , Department of Electrical Engineering, National Central University, Jung-Li, Taoyuan, Taiwan, R.O.C.
Cheng-Liang Hung , Department of Electrical Engineering, National Central University, Jung-Li, Taoyuan, Taiwan, R.O.C.
Jiunn-Way Miaw , Dept. of SOC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan R.O.C., Email: jwmiaw@itri.org.tw
Chih-Hsien Chang , Department of Electrical Engineering, National Central University, Jung-Li, Taoyuan, Taiwan, R.O.C.
Wei-Bin Yang , Department of Electrical Engineering, Tamkang University, Tamsui, Taipei, Taiwan R.O.C., Email: robin@ee.tku.edu.tw
pp. 1-4

Incremental SAT Instance Generation for SAT-based ATPG (Abstract)

Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany, drechsle@informatik.uni-bremen.de
Daniel Tille , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany, tille@informatik.uni-bremen.de
pp. 1-6

Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs (Abstract)

Andrzej Krasniewski , Warsaw University of Technology, Institute of Telecommunications, andrzej@tele.pw.edu.pl
pp. 1-6

Analysis of the influence of intermittent faults in a microcontroller (Abstract)

L.J. Saiz , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Departamento de Informática de Sistemas y Computadores (DISCA), Universidad Politécnica de Valencia, Spain, e-mail: ljsaiz@disca.upv.
J. Gracia , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Departamento de Informática de Sistemas y Computadores (DISCA), Universidad Politécnica de Valencia, Spain, e-mail: jgracia@disca.upv
J.C. Baraza , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Departamento de Informática de Sistemas y Computadores (DISCA), Universidad Politécnica de Valencia, Spain, e-mail: jcbaraza@disca.up
P.J. Gil , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Departamento de Informática de Sistemas y Computadores (DISCA), Universidad Politécnica de Valencia, Spain, e-mail: pgil@disca.upv.es
D. Gil , Grupo de Sistemas Tolerantes a Fallos (GSTF) - Departamento de Informática de Sistemas y Computadores (DISCA), Universidad Politécnica de Valencia, Spain, e-mail: dgil@disca.upv.es
pp. 1-6

Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform (Abstract)

H. Cappelle , IMEC Lab., Kapeldreef 75, 3001 Leuven, Belgium
M. Glassee , IMEC Lab., Kapeldreef 75, 3001 Leuven, Belgium
L. van der Perre , IMEC Lab., Kapeldreef 75, 3001 Leuven, Belgium
B. Bougard , IMEC Lab., Kapeldreef 75, 3001 Leuven, Belgium
M. Palkovic , IMEC Lab., Kapeldreef 75, 3001 Leuven, Belgium
pp. 1-6

Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip (Abstract)

Axel Jantsch , Dept. of Electronic, Computer and Software Systems, Royal Institute of Technology (KTH), Stockholm, Sweden, axel@kth.se
Lei Xia , Dept. of Electronic, Computer and Software Systems, Royal Institute of Technology (KTH), Stockholm, Sweden, leix@kth.se
Zhonghai Lu , Dept. of Electronic, Computer and Software Systems, Royal Institute of Technology (KTH), Stockholm, Sweden, zhonghai@kth.se
pp. 1-6

MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC (Abstract)

Rishad A. Shafik , School of ECS, University of Southampton, Southampton, UK, SO17 1BJ, Email: ras06r@ecs.soton.ac.uk
Paul Rosinger , School of ECS, University of Southampton, Southampton, UK, SO17 1BJ, Email: pmr@ecs.soton.ac.uk
Bashir M. Al-Hashimi , School of ECS, University of Southampton, Southampton, UK, SO17 1BJ, Email: bmah@ecs.soton.ac.uk
pp. 1-6

Rapid Prototyping of NoC Architectures from a SystemC Specification (Abstract)

Robert Tomaszewski , Kielce University of Technology, Dept. of Computer Science, Kielce, Poland, email: r.tomaszewski@tu.kielce.pl
Stanislaw Deniziak , Cracow University of Technology, Dept. of Computer Engineering, Cracow, Poland, email: s.deniziak@computer.org
pp. 1-6

Novel Hardware Implementation of Adaptive Median Filters (Abstract)

Lukas Sekanina , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, E-mail: sekanina@fit.vutbr.cz
Zdenek Vasicek , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, E-mail: vasicek@fit.vutbr.cz
pp. 1-6

A New Design Technique for Weakly Indicating Function Blocks (Abstract)

D.A. Edwards , School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom. E-mail: doug@cs.man.ac.uk.
P. Balasubramanian , School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom. E-mail: padmanab@cs.man.ac.uk.
pp. 1-6

Fast Boolean Minimizer for Completely Specified Functions (Abstract)

Petr Fiser , Dept. of Computer Science and Engineering, Czech Technical University, Karlovo nam. 13, CZ-121 35 Prague 2, e-mail: fiserp@fel.cvut.cz
Irena Vanova , UTIA, CAS, Pod Vodarenskou vezi 4, CZ-182 08, Prague 8, e-mail: vanovai@utia.cas.cz
Premysl Rucky , Dept. of Computer Science and Engineering, Czech Technical University, Karlovo nam. 13, CZ-121 35 Prague 2, e-mail: ruckyp@fel.cvut.cz
pp. 1-6

The HDL and FE Thermal Modeling of Heterogeneous Systems (Abstract)

G. Janczyk , Institute of Electron Technology, Al. Lotnikow 32/46, 02-668, Warsaw, POLAND
T. Bieniek , Institute of Electron Technology, Al. Lotnikow 32/46, 02-668, Warsaw, POLAND
pp. 1-4

A System-On-Chip for Wireless Body Area Sensor Network Node (Abstract)

G. Schoof , IBP GmbH, Im Technologiepark 25, 15236 Frankfurt (Oder), GERMANY
G. Panic , IBP GmbH, Im Technologiepark 25, 15236 Frankfurt (Oder), GERMANY
Z. Stamenkovic , IBP GmbH, Im Technologiepark 25, 15236 Frankfurt (Oder), GERMANY
pp. 1-4

Mixed-Signal DFT for fully testable ASIC (Abstract)

Frantisek Reznicek , AMI Semiconductor Czech s.r.o., Víde¿iská 125, 619 00, Brno, Czech Republic, frantisek.reznicek@amis.com
pp. 1-4

On Minimizing RTOS Aperiodic Tasks Server Energy Consumption (Abstract)

Karel Dudacek , University of West Bohemia, Dept. Computer Science and Engineering, Univerzitni 8, Pilsen, Czech Republic
pp. 1-4

Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor Systems (Abstract)

E. Gramatova , Institute of Informatics of the Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava, 845 07 Slovakia
M. Manik , Institute of Informatics of the Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava, 845 07 Slovakia
pp. 1-2

A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units (Abstract)

Alexandru Amaricai , Department of Computer Science and Engineering, University Politehnica of Timisoara, alexandru.amaricai@cs.upt.ro
Mircea Vladutiu , Department of Computer Science and Engineering, University Politehnica of Timisoara, mvlad@cs.upt.ro
Virgil E. Petcu , Department of Computer Science and Engineering, University Politehnica of Timisoara, virgil.e.petcu@gmail.com
pp. 1-4

Design of Time-to-Digital Converter Output Interface (Abstract)

Marek Miskowicz , AGH University of Science and Technology, Department of Electronics, Al. Mickiewicza 30, 30-059 Cracow, Poland
pp. 1-4

Design and Simulation of Runtime Reconfigurable Systems (Abstract)

Thilo Pionteck , Institute of Computer Engineering, University of Lübeck, 23538 Lübeck, Germany, Email: pionteck@iti.uni-luebeck.de
Roman Koch , Institute of Computer Engineering, University of Lübeck, 23538 Lübeck, Germany, Email: koch@iti.uni-luebeck.de
Torben Brix , Institute of Computer Engineering, University of Lübeck, 23538 Lübeck, Germany, Email: brix@iti.uni-luebeck.de
Erik Maehle , Institute of Computer Engineering, University of Lübeck, 23538 Lübeck, Germany, Email: maehle@iti.uni-luebeck.de
Carsten Albrecht , Institute of Computer Engineering, University of Lübeck, 23538 Lübeck, Germany, Email: albrecht@iti.uni-luebeck.de
pp. 1-4

Modeling and observing the jitter in ring oscillators implemented in FPGAs (Abstract)

Viktor Fischer , Laboratoire Hubert Curien, UMR CNRS 5516, Université Jean Monnet, France, e-mail: fischer@univ-st-etienne.fr
Alain Aubert , Laboratoire Hubert Curien, UMR CNRS 5516, Université Jean Monnet, France, e-mail: alain.aubert@univ-st-etienne.fr
Boyan Valtchanov , Laboratoire Hubert Curien, UMR CNRS 5516, Université Jean Monnet, France, e-mail: boyan.valtchanov@univ-st-etienne.fr
Florent Bernard , Laboratoire Hubert Curien, UMR CNRS 5516, Université Jean Monnet, France, e-mail: florent.bernard@univ-st-etienne.fr
pp. 1-6

Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator (Abstract)

Michal Varchola , Department of Electronics and Multimedia Communications, Technical University of Kosice, Park Komenskeho 13, Kosice 041 20, Slovak Republic, E-mail: Miso.Varchola@tuke.sk
Milos Drutarovsky , Department of Electronics and Multimedia Communications, Technical University of Kosice, Park Komenskeho 13, Kosice 041 20, Slovak Republic, E-mail: Milos.Drutarovsky@tuke.sk
pp. 1-6

Various MDCT implementations in 0.35 (Abstract)

Peter Malik , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia, p.malik@savba.sk
Marcel Balaz , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia, marcel.balaz@savba.sk
Arkadiusz Luczyk , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland, aluczyk@elka@imio.pw.edu.pl
Witold Pleskacz , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland, w.pleskacz@imio.pw.edu.pl
Martin Simlastik , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia, martin.simlastik@savba.sk
pp. 1-4

Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology (Abstract)

Horst Zimmermann , Institute of Electrical Measurement and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/35, 1040 Vienna, Austria, horst.zimmermann@ieee.org
Kurt Schweiger , Institute of Electrical Measurement and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/35, 1040 Vienna, Austria, kurt.schweiger@tuwien.ac.at
pp. 1-4

Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs (Abstract)

Leos Kafka , Department of Signal Processing, UTIA AV CR v.v.i., Pod Vodarenskou vezi 4, 182 08 Praha 8, Czech Republic, leos.kafka@utia.cas.cz
pp. 1-4

Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits (Abstract)

Martin Rozkovec , Institute of Information Technologies and Electronics, Technical University in Liberec, Liberec, Czech Republic, martin.rozkovec@tul.cz
pp. 1-4

A Partial Scan Based Test Generation for Asynchronous Circuits (Abstract)

D.P. Vasudevan , ICSA, School of Informatics, University of Edinburgh, UK, e-mail: aefthymi@inf.ed.ac.uk
A. Efthymiou , ICSA, School of Informatics, University of Edinburgh, UK, e-mail:aefthymi@inf.ed.ac.uk
pp. 1-4

Efficient Allocation of Verification Resources using Revision History Information (Abstract)

Andrea Iabrudi Tavares , Jasper Design Automation, Mountain View, CA, USA, Email: iabrudi@jasper-da.com
Claudionor N. Coelho , Computer Science Department, Universidade Federal de Minas Gerais, Belo Horizonte, MG, Brazil, Jasper Design Automation, Mountain View, CA, USA, Email: coelho@dcc.ufmg.br
Antonio O. Fernandes , Computer Science Department, Universidade Federal de Minas Gerais, Belo Horizonte, MG, Brazil, Email: otavio@dcc.ufmg.br
Thiago Silva , Computer Science Department, Universidade Federal de Minas Gerais, Belo Horizonte, MG, Brazil, Email: thiagosf@dcc.ufmg.br
Jose Augusto Nacif , Computer Science Department, Universidade Federal de Minas Gerais, Belo Horizonte, MG, Brazil, Email: jnacif@dcc.ufmg.br
pp. 1-5

Ad-Hoc Translations to Close Verilog Semantics Gap (Abstract)

Christian Haufe , AMD Saxony LLC&Co. KG, Dresden Design Center, Germany, christian.haufe@amd.com
Frank Rogin , Fraunhofer Institute for Integrated Circuits, Division Design Automation, Germany, frank.rogin@eas.iis.fraunhofer.de
pp. 1-6

Code Coverage Analysis using High-Level Decision Diagrams (Abstract)

Raimund Ubar , Department of Computer Engineering, Tallinn University of Technology, Raja 15, 12618 Tallinn, Estonia, raiub@pld.ttu.ee
Maksim Jenihhin , Department of Computer Engineering, Tallinn University of Technology, Raja 15, 12618 Tallinn, Estonia, maksim@pld.ttu.ee
Peeter Ellervee , Department of Computer Engineering, Tallinn University of Technology, Raja 15, 12618 Tallinn, Estonia, LRV@cc.ttu.ee
Uljana Reinsalu , Department of Computer Engineering, Tallinn University of Technology, Raja 15, 12618 Tallinn, Estonia, uljana@pld.ttu.ee
Jaan Raik , Department of Computer Engineering, Tallinn University of Technology, Raja 15, 12618 Tallinn, Estonia, jaan@pld.ttu.ee
pp. 1-6

Probabilistic Model Checking and Reliability of Results (Abstract)

Ralf Wimmer , Institute of Computer Science, Albert-Ludwigs-University, 79110 Freiburg im Breisgau, Germany, wimmer@informatik.uni-freiburg.de
Alexander Kortus , Institute of Computer Science, Albert-Ludwigs-University, 79110 Freiburg im Breisgau, Germany, kortus@informatik.uni-freiburg.de
Marc Herbstritt , Institute of Computer Science, Albert-Ludwigs-University, 79110 Freiburg im Breisgau, Germany, herbstri@informatik.uni-freiburg.de
Bernd Becker , Institute of Computer Science, Albert-Ludwigs-University, 79110 Freiburg im Breisgau, Germany, becker@informatik.uni-freiburg.de
pp. 1-6

Network Probe for Flexible Flow Monitoring (Abstract)

Petr Kobiersky , CESNET z.s.p.o., Zikova 4, Prague, 160 00, Czech Republic, Email: kobiersky@liberouter.org
Jan Korenek , Faculty of Information Technology, Brno University of Technology, Bo¿et¿chova 2, Brno, 612 66, Czech Republic, Email: korenek@fit.vutbr.cz
Martin Zadnik , Faculty of Information Technology, Brno University of Technology, Bo¿et¿chova 2, Brno, 612 66, Czech Republic, Email: izadnik@fit.vutbr.cz
Ondrej Lengal , CESNET z.s.p.o., Zikova 4, Prague, 160 00, Czech Republic, Email: lengal@liberouter.org
pp. 1-6

NetCOPE: Platform for Rapid Development of Network Applications (Abstract)

Martin Kosek , CESNET z.s.p.o., Zikova 4, Prague, 160 00, Czech Republic, Email: kosek@liberouter.org
Tomas Martinek , Faculty of Information Technology, Brno University of Technology, Bo¿et¿hova 2, Brno, 612 66, Czech Republic, Email: martinto@fit.vutbr.cz
pp. 1-6

IP-based Systematic Design of Power-and Matching-limited Circuits (Abstract)

Ludek Pantucek , AMI Semiconductor Czech, s.r.o., Víde¿ská 125, 619 00, Brno, Czech Republic
David Smola , AMI Semiconductor Czech, s.r.o., Víde¿ská 125, 619 00, Brno, Czech Republic, david_smola@amis.com
pp. 1-6

A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID Applications (Abstract)

Marco Bucci , Infineon Technologies AG, Babenbergerstrasse 10, A-8020 Graz, AUSTRIA
Raimondo Luzzi , Infineon Technologies AG, Babenbergerstrasse 10, A-8020 Graz, AUSTRIA
Santos Torres Vargas , Continental AG, Ringlerstrasse 17, 85057 Ingolstadt, GERMANY
pp. 1-4

Interconnect Faults Identification and Localization Using Modified Ring LFSRs (Abstract)

Michal Kopec , Silesian University of Technology, mkopec@onet.pl
Tomasz Garbolino , Silesian University of Technology, tgarbolino@polsl.pl
Andrzej Hlawiczka , Silesian University of Technology, ahlawiczka@polsl.pl
Krzysztof Gucwa , Silesian University of Technology, kgucwa@polsl.pl
pp. 1-4

Testing an Emergency Luminaire Circuit Using a Fault Dictionary Approach (Abstract)

Dimitris K. Papakostas , Dept. of Electronics, Alexander Technological Educational Inst. of Thessaloniki, Greece
Alexios Spyronasios , Dept. of Electrical&Computer Eng., Aristotle Univ. of Thessaloniki, Greece
Michael G. Dimopoulos , Olympia Electronics S.A., Research&Development Dept, 60061 Kolindros-Pieria, Greece
Dimitrios K. Konstantinou , Dept. of Electrical&Computer Eng., Aristotle Univ. of Thessaloniki, Greece
Alkis A. Hatzopoulos , Dept. of Electrical&Computer Eng., Aristotle Univ. of Thessaloniki, Greece
pp. 1-4

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration (Abstract)

Lukas Sekanina , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, Email: sekanina@fit.vutbr.cz
Lukas Starecek , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, Email: starecek@fit.vutbr.cz
Zdenek Kotasek , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, Email: kotasek@fit.vutbr.cz
pp. 1-4

Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology (Abstract)

Tomasz Borejko , Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, ul.Koszykowa 7, 00-662 Warsaw, Poland, T.Borejko@imio.pw.edu.pl
Marcin J. Beresinski , Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, ul.Koszykowa 7, 00-662 Warsaw, Poland, Twinteq, ul. Ostrobramska 101, 04-041 Warsaw, Poland, M.B
Witold A. Pleskacz , Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, ul.Koszykowa 7, 00-662 Warsaw, Poland, W.Pleskacz@imio.pw.edu.pl
Viera Stopjakova , Slovak University of Technology, Department of Microelectronics, Ilkovicova 3, 812 19 Bratislava, Slovakia, viera.stopjakova@stuba.sk
pp. 1-4

Diagnosis of Realistic Defects Based on the X-Fault Model (Abstract)

Kohei Miyase , Faculty of Computer Science and Systems Eng., Kyushu Institute of Technology, lizuka-shi, 820-8502, Japan, k.miyase@cse.kyutech.ac.jp
Xiaoqing Wen , Faculty of Computer Science and Systems Eng., Kyushu Institute of Technology, lizuka-shi, 820-8502, Japan, wen@cse.kyutech.ac.jp
Ilia Polian , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-791 10 Freiburg i. Br., Germany, polian@informatik.uni-freiburg.de
Yusuke Nakamura , Faculty of Computer Science and Systems Eng., Kyushu Institute of Technology, lizuka-shi, 820-8502, Japan, yusuke.kyutech@gmail.com
Seiji Kajihara , Faculty of Computer Science and Systems Eng., Kyushu Institute of Technology, lizuka-shi, 820-8502, Japan, kajihara@cse.kyutech.ac.jp
Piet Engelke , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-791 10 Freiburg i. Br., Germany, engelke@informatik.uni-freiburg.de
Bernd Becker , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-791 10 Freiburg i. Br., Germany, becker@informatik.uni-freiburg.de
Stefan Spinner , Institute for Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, D-791 10 Freiburg i. Br., Germany, stspinne@informatik.uni-freiburg.de
pp. 1-4

Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits (Abstract)

Thomas Panhofer , Austrian Aerospace GmbH, Stachegasse 16, 1120 Vienna, Austria, pan@space.at
Werner Friesenbichler , Austrian Aerospace GmbH, Stachegasse 16, 1120 Vienna, Austria, fri@space.at
Martin Delvai , Vienna University of Technology, Embedded Computing Systems Group, Treitlstrasse 3, 1040 Vienna, Austria, delvai@ecs.tuwien.ac.at
pp. 1-4

Calculation of LFSR Seed and Polynomial Pair for BIST Applications (Abstract)

A. Jutman , Tallinn University of Technology, Raja 15, 12618, Tallinn, ESTONIA, artur@pld.ttu.ee
A. Tsertov , Tallinn University of Technology, Raja 15, 12618, Tallinn, ESTONIA, antonchertov@gmail.com
R. Ubar , Tallinn University of Technology, Raja 15, 12618, Tallinn, ESTONIA, raiub@pld.ttu.ee
pp. 1-4

Excitation optimization in fault diagnosis of analog electronic circuits (Abstract)

J. Rutkowski , SILESIAN UNIVERSITY OF TECHNOLOGY, INSTITUTE OF ELECTRONICS, GLIWICE, POLAND
L. Chruszczyk , SILESIAN UNIVERSITY OF TECHNOLOGY, INSTITUTE OF ELECTRONICS, GLIWICE, POLAND
pp. 1-4

Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform (Abstract)

Petr Struhovsky , Department of Circuit Theory FEE CTU Prague, Technická 2, 166 27 Prague, Czech Republic, Struhovsky@centrum.cz@fel.cvut.cz
Pravoslav Martinek , Department of Circuit Theory FEE CTU Prague, Technická 2, 166 27 Prague, Czech Republic, Martinek@fel.cvut.cz
Ondrej Subrt , ASICentrum, Novodvorská 994, 142 21 Prague, Czech Republic, Department of Circuit Theory FEE CTU Prague, Technick
Jiri Hospodka , Department of Circuit Theory FEE CTU Prague, Technická 2, 166 27 Prague, Czech Republic, Hospodka@fel.cvut.cz
pp. 1-4

Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm (Abstract)

Amir Zjajo , NXP Semiconductors Research, High Tech Campus 37, 5656 AE Eindhoven, The Netherlands, e-mail: amir.zjajo@nxp.com
Jose Pineda de Gyvez , NXP Semiconductors Research, High Tech Campus 37, 5656 AE Eindhoven, The Netherlands, Eindhoven University of Technology, Den Dolech 2, 5612 AZ Eindhoven, The Netherlands
Shaji Krishnan , NXP Semiconductors Research, High Tech Campus 37, 5656 AE Eindhoven, The Netherlands
pp. 1-6

Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation (Abstract)

J. Mihalov , Department of Microelectronics, Slovak University of Technology, Ilkovicova 3, 812 19 Bratislava, Slovak Republic
J. Brenkus , Department of Microelectronics, Slovak University of Technology, Ilkovicova 3, 812 19 Bratislava, Slovak Republic, juraj.brenkus@stuba.sk
V. Stopjakova , Department of Microelectronics, Slovak University of Technology, Ilkovicova 3, 812 19 Bratislava, Slovak Republic
pp. 1-6

The Influence of Global Parametric Faults on Analogue Electronic Circuits Time Domain Response Features (Abstract)

J. Rutkowski , Silesian University of Technology, Gliwice, POLAND
T. Golonek , Silesian University of Technology, Gliwice, POLAND
D. Grzechca , Silesian University of Technology, Gliwice, POLAND
P. Jantos , Silesian University of Technology, Gliwice, POLAND
pp. 1-5

A novel method for test and calibration of capacitive accelerometers with a fully electrical setup (Abstract)

F. Mailly , Université Montpellier 2 / CNRS, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), 161 Rue Ada, 34392 Montpellier Cedex 5, France
F. Azais , Université Montpellier 2 / CNRS, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), 161 Rue Ada, 34392 Montpellier Cedex 5, France
A. Richardson , Lancaster University, Centre for Microsystems, Lancaster, LAI 4YR, UK
N. Dumas , Université Montpellier 2 / CNRS, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), 161 Rue Ada, 34392 Montpellier Cedex 5, France
P. Nouet , Université Montpellier 2 / CNRS, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier (LIRMM), 161 Rue Ada, 34392 Montpellier Cedex 5, France
pp. 1-6

On-chip Integration of Magnetic Force Sensing Current Monitors (Abstract)

Juraj Marek , Slovak University of Technology, Department of Microelectronics, Ilkovicova 3, 812 19 Bratislava, Slovakia
Martin Donoval , Slovak University of Technology, Department of Microelectronics, Ilkovicova 3, 812 19 Bratislava, Slovakia, martin.donoval@stuba.sk
Martin Daricek , Slovak University of Technology, Department of Microelectronics, Ilkovicova 3, 812 19 Bratislava, Slovakia
Viera Stopjakova , Slovak University of Technology, Department of Microelectronics, Ilkovicova 3, 812 19 Bratislava, Slovakia
pp. 1-4

A Cost Effective BIST Second-Order (Abstract)

Sheng-Chuan Liang , Department of Electrical and Control Engineering, National Chiao Tung University, Hsin-Chu, Taiwan 300
Hong-Chin Song , Department of Electrical and Control Engineering, National Chiao Tung University, Hsin-Chu, Taiwan 300
Hao-Chiao Hong , Department of Electrical and Control Engineering, National Chiao Tung University, Hsin-Chu, Taiwan 300, Telephone: +886-3-571-2121 ext. 54375, Fax: +886-3-571-5998 Email: hchong@cn
pp. 1-6

SoC Symbolic Simulation: a case study on delay fault testing (Abstract)

S. Pravossoudovich , LIRMM, Montpellier, FR
P. Bemardi , Politecnico di Torino, I
A. Bosio , LIRMM, Montpellier, FR
P. Girard , LIRMM, Montpellier, FR
pp. 1-6

SoCECT: System on Chip Embedded Core Test (Abstract)

Brendan Mullane , Department of Electronic&Computer Engineering (Mixed Signal Integrated Circuit Group), University of Limerick, Ireland
Michael Higgins , Department of Electronic&Computer Engineering (Mixed Signal Integrated Circuit Group), University of Limerick, Ireland. Michael.Higgins@ul.ie
Ciaran MacNamee , Department of Electronic&Computer Engineering (Mixed Signal Integrated Circuit Group), University of Limerick, Ireland
pp. 1-6

Optimal Backgrounds Selection for Multi Run Memory Testing (Abstract)

Ireneusz Mrozek , Bialystok Technical University, Computer Science Department, Wiejska 45A, 15-351 Bialystok, POLAND, imrozek@ii.pb.bialystok.pl
Vyacheslav Yarmolik , Bialystok Technical University, Computer Science Department, Wiejska 45A, 15-351 Bialystok, POLAND, yarmolik@ii.pb.bialystok.pl
pp. 1-7

Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs (Abstract)

J. Velasco Medina , Universidad del Valle, Grupo de Bionanoelectrónica, Cali, Colombia, jvelasco@univalle.edu.co
E. Sanchez , Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy, Dip. Automatica e Informatica. Politecnico, di Torino. Cso. Duca degli Abruzzi 24, 10129, Torino, It
D. Ravotto , Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy, danilo.ravotto@polito.it
W. J. Perez H. , Universidad del Valle, Grupo de Bionanoelectrónica, Cali, Colombia, wjperezh@univalle.edu.co
M. Sonza Reorda , Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy, matteo.sonzareorda@polito.it
pp. 1-6

Author Index (PDF)

pp. 1-2
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