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2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (2008)
Bratislava, Slovakia
Apr. 16, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-2276-0
pp: 1-4
Lukas Starecek , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, Email: starecek@fit.vutbr.cz
Lukas Sekanina , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, Email: sekanina@fit.vutbr.cz
Zdenek Kotasek , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, Email: kotasek@fit.vutbr.cz
ABSTRACT
In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (but some of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increase in transistors is moderate.
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CITATION

L. Sekanina, L. Starecek and Z. Kotasek, "Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration," 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems(DDECS), Bratislava, Slovakia, 2008, pp. 1-4.
doi:10.1109/DDECS.2008.4538796
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