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2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (2008)
Bratislava, Slovakia
Apr. 16, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-2276-0
pp: 1-6
D.A. Edwards , School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom. E-mail: doug@cs.man.ac.uk.
P. Balasubramanian , School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom. E-mail: padmanab@cs.man.ac.uk.
ABSTRACT
This paper presents a novel technique for gate-level design of combinatorial logic as weakly indicating function blocks. The input state space associated with a function block expands exponentially with a gradual increase in the number of inputs. As a result, large area overhead would incur for an asynchronous realization. Hence, a novel design methodology for realizing combinational logic as a function block is developed under the discipline of quasi-delay-insensitivity with four-phase handshaking and dual-rail encoding, whilst trying to mitigate the area overhead. The focus is on design adhering to the weakly indicating timing regime. Based on analysis with some combinational benchmarks and widely used logic circuit functionality, the proposed method is found to enable compact realizations and appears to be promising for weakly indicating function block design comprising many inputs and outputs.
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CITATION
D.A. Edwards, P. Balasubramanian, "A New Design Technique for Weakly Indicating Function Blocks", 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), vol. 00, no. , pp. 1-6, 2008, doi:10.1109/DDECS.2008.4538767
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