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2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (2008)
Bratislava, Slovakia
Apr. 16, 2008 to Apr. 18, 2008
ISBN: 978-1-4244-2276-0
pp: 1-6
Zdenek Vasicek , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, E-mail: vasicek@fit.vutbr.cz
Lukas Sekanina , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic, E-mail: sekanina@fit.vutbr.cz
ABSTRACT
A new FPGA implementation for adaptive median filters is proposed. Adaptive median filters exhibit better filtering properties than standard median filters; however, their implementation cost is higher. Proposed architecture was optimized for throughput allowing 300M pixels to be filtered per second. The best performance/cost ratio exhibits the adaptive median filter which utilizes filtering window 7
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CITATION

L. Sekanina and Z. Vasicek, "Novel Hardware Implementation of Adaptive Median Filters," 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems(DDECS), Bratislava, Slovakia, 2008, pp. 1-6.
doi:10.1109/DDECS.2008.4538766
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