2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (2007)
Krakow, Poland
Apr. 11, 2007 to Apr. 13, 2007
ISBN: 1-4244-1161-0
TABLE OF CONTENTS
New Strategies for System-Level Design (PDF)
D.D. Gajski , Univ. of California Irvine, Irvine
pp. 15
Papers
Covers (PDF)
pp. C1
Covers (PDF)
pp. C2
Papers
Foreword to the IEEE DDECS 2007 Workshop (PDF)
pp. 4
Workshop Committees (PDF)
pp. 5-6
Table of contents (PDF)
pp. 7-12
A Testable Random Bit Generator based on a High Resolution Phase Noise Detection (Abstract)
Marco Bucci , Infineon Technologies AG, Babenbergerstrasse 10, A-8020 Graz, AUSTRIA
Raimondo Luzzi , Infineon Technologies AG, Babenbergerstrasse 10, A-8020 Graz, AUSTRIA
pp. 1-5
Test Pattern Compression Based on Pattern Overlapping (Abstract)
Jiri Jenicek , Technical University Liberec, H?lkova 6, 461 17 Liberec I, Czech Republic
Ondrej Novak , Technical University Liberec, H?lkova 6, 461 17 Liberec I, Czech Republic. E-mail: ondrej.novak@tul.cz
pp. 1-6
Layout to Logic Defect Analysis for Hierarchical Test Generation (Abstract)
Jaan Raik , Tallinn University of Technology. jaan@pld.ttu.ee
Maksim Jenihhin , Tallinn University of Technology. maksim@pld.ttu.ee
Witold A. Pleskacz , Warsaw University of Technology. W.Pleskacz@imio.pw.edu.pl
Michal Rakowski , Warsaw University of Technology. M.Rakowski@elka.pw.edu.pl
Raimund Ubar , Tallinn University of Technology. raiub@pld.ttu.ee
pp. 1-6
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips (Abstract)
Wojciech Sakowski , Institute of Electronics, Silesian University of Technology, Akademicka 16 Gliwice, Poland. Wojciech.Sakowski@polsl.pl
Bartosz Wojciechowski , Virtual Component Lab, Evatronix SA, Dubois 16 Gliwice, Poland. Bartosz.Wojciechowski@evatronix.pl
Tomasz Kowalczyk , Virtual Component Lab, Evatronix SA, Dubois 16 Gliwice, Poland. Tomasz.Kowalczyk@evatronix.pl
pp. 1-5
Resource Constrained Co-synthesis of Self-reconfigurable SOPCs (Abstract)
Stanislaw Deniziak , Cracow University of Technology, Warszawska 24, 31-155 Krak?w, POLAND. E-mail: pedenizi@cyf-kr.edu.pl
Radoslaw Czarnecki , Cracow University of Technology, Warszawska 24, 31-155 Krak?w, POLAND. E-mail: czarneck@pk.edu.pl
pp. 1-6
Extended Fault Detection Techniques for Systems-on-Chip (Abstract)
M. Sonza Reorda , Politecnico di Torino, Dipartimento di Automatica e Informatica Torino, Italy
L. Bolzani , Politecnico di Torino, Dipartimento di Automatica e Informatica Torino, Italy
P. Bernardi , Politecnico di Torino, Dipartimento di Automatica e Informatica Torino, Italy
pp. 1-6
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing (Abstract)
Petru Eles , Embedded Systems Laboratory, Link?pings Universitet, SE-582 83 Link?ping, Sweden
Zebo Peng , Embedded Systems Laboratory, Link?pings Universitet, SE-582 83 Link?ping, Sweden
Anders Larsson , Embedded Systems Laboratory, Link?pings Universitet, SE-582 83 Link?ping, Sweden
Erik Larsson , Embedded Systems Laboratory, Link?pings Universitet, SE-582 83 Link?ping, Sweden
pp. 1-6
Qikai Chen , Dept of ECE, Purdue University, West Lafayette, IN-47907, USA. qikaichen@ecn.purdue.ed
Saibal Mukhopadhyay , Dept of ECE, Purdue University, West Lafayette, IN-47907, USA. sm@ecn.purdue.ed
Kaushik Roy , Dept of ECE, Purdue University, West Lafayette, IN-47907, USA. kaushik@ecn.purdue.ed
pp. 1-6
Architecture for Highly Reliable Embedded Flash Memories (Abstract)
Jean-Michel Daga , Libraries and Design Tools Department - Embedded Non-Volatile Memory Group, ATMEL Rousset - 13106 Rousset Cedex, France. jean-michel.daga@rfo.atmel.com
Lionel Torres , Montpellier Laboratory of Computer Science, Robotics, and Microelectronics - LIRMM, Universit? de Montpellier II / UMR5506 CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France. to
Benoit Godard , Libraries and Design Tools Department - Embedded Non-Volatile Memory Group, ATMEL Rousset - 13106 Rousset Cedex, France; Montpellier Laboratory of Computer Science, Robotics, and M
Gilles Sassatelli , Montpellier Laboratory of Computer Science, Robotics, and Microelectronics - LIRMM, Universit? de Montpellier II / UMR5506 CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France. sa
pp. 1-6
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology (Abstract)
Kunihiro Asada , Department of Electronic Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, JAPAN; VLSI Design and Education Center(VDEC), The University of Tokyo, 7-3-1
Zhicheng Liang , Department of Electronic Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, JAPAN. liang@silicon.u-tokyo.ac.jp
Makoto Ikeda , Department of Electronic Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, JAPAN; VLSI Design and Education Center(VDEC), The University of Tokyo, 7-3-1
pp. 1-6
Accurately Determining Bridging Defects from Layout (Abstract)
Rohit Kapur , Synopsys, Inc.
Maria Gkatziani , Synopsys, Inc.
Salvatore Talluto , Synopsys, Inc.
T. W. Williams , University of Calgary
Laura Tarantini , STMicroelectronics Srl.
Ben Mathew , Synopsys, Inc.
Qing Su , Synopsys, Inc.
Cy Hay , Synopsys, Inc.
Roberto Mattiuzzo , STMicroelectronics Srl.
pp. 1-4
FPGA Implementaton of Strongly Parallel Histogram Equalization (Abstract)
Ernest Jamro , AGH University of Science and Technology, al. Mickiewicz 30, 30-051, Poland. Academic Computer Center CYFRONET, ul. Nawojki 11, Krak?w 30-950, Poland. email: jamro@agh.edu.pl
Kazimierz Wiatr , AGH University of Science and Technology, al. Mickiewicz 30, 30-051, Poland. Academic Computer Center CYFRONET, ul. Nawojki 11, Krak?w 30-950, Poland. email: wiatr@agh.edu.pl
Maciej Wielgosz , AGH University of Science and Technology, al. Mickiewicz 30, 30-051, Poland. Academic Computer Center CYFRONET, ul. Nawojki 11, Krak?w 30-950, Poland. email: wielgosz@agh.edu.pl
pp. 1-6
Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's (Abstract)
Bogdan Falkowski , Nanyang Technological University, School of Electrical and Electronic Engineering, 50 Nanyang Avenue, Singapore 639798
Tadeusz Luba , Warsaw University of Technology, Institute of Telecommunications, Nowowiejska 15/19, 00-665 Warsaw, Poland
Grzegorz Borowik , Warsaw University of Technology, Institute of Telecommunications, Nowowiejska 15/19, 00-665 Warsaw, Poland
pp. 1-6
Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder (Abstract)
Erno Salminen , Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, Korkeakoulunkatu 1, FI-33101 Tampere, Finland
Timo D. Hamalainen , Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, Korkeakoulunkatu 1, FI-33101 Tampere, Finland
Ari Kulmala , Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, Korkeakoulunkatu 1, FI-33101 Tampere, Finland. ari.kulmala@tut.fi
pp. 1-6
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling (Abstract)
Dongsoo Kim , Department of Electrical and Electronic Engineering, Yonsei University, Seoul Korea. Email: soo@yonsei.ac.kr
Gunhee Han , Department of Electrical and Electronic Engineering, Yonsei University, Seoul Korea. Email: gunhee@yonsei.ac.kr
pp. 1-3
A PMT interface for the Optical Module front-end of a neutrino underwater telescope (Abstract)
N. Randazzo , Istituto Nazionale di Fisica Nucleare, Sezione di Catania, Italy
L. Caponetto , Istituto Nazionale di Fisica Nucleare, Sezione di Catania, Italy
D. Lo Presti , Istituto Nazionale di Fisica Nucleare, Sezione di Catania, Italy; Universit? degli studi di Catania - Dipartimento di Fisica, Catania, Italy. domenico.lopresti@ct.infn.it
V. Sipala , Istituto Nazionale di Fisica Nucleare, Sezione di Catania, Italy
pp. 1-4
A proposal for ASM++ diagrams (Abstract)
Santiago de Pablo , University of Valladolid, Valladolid, Spain. Email: sanpab@eis.uva.es
Manuel Berrocal , eZono GmbH, Jena, Germany. Email: manuel@ezono.com
Santiago Caceres , University of Valladolid, Valladolid, Spain. Email: sancac@eis.uva.es
Jesus A. Cebrian , University of Valladolid, Valladolid, Spain. Email: jesceb@eis.uva.es
pp. 1-4
Lightweight Multi-threaded Network Processor Core in FPGA (Abstract)
Piotr Buciak , Warsaw University of Technology pbuciak
Jakub Botwicz , Warsaw University of Technology pbuciak, jbotwiczka@elka.pw.edu.pl
pp. 1-5
Parts Obsolescence Challenges for the Electronics Industry (Abstract)
Thor Arne Lovland , Department of Informatics, University of Oslo, P.O. Box 1080 Blindern, N-0316 Oslo, Norway. Phone: +47 2285 2454, Fax: +47 2285 2401
Jim Torresen , Department of Informatics, University of Oslo, P.O. Box 1080 Blindern, N-0316 Oslo, Norway. Phone: +47 2285 2454, Fax: +47 2285 2401, E-mail: jimtoer@ifi.uio.no
pp. 1-4
F. Adepoju , Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland. francis.adepoju@ul.ie
E. Jafer , Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland. essa.jafer@ul.ie
K. Arshak , Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland. khalil.arshak@ul.ie
pp. 1-4
Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation (Abstract)
I. Brzozowski , AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Krak?w, POLAND
A. Kos , AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Krak?w, POLAND
pp. 1-6
V.A. Vardanian , Virage Logic, 15/1 Khorenatsi str., Yerevan, 375010, Armenia
G. Harutunyan , Virage Logic, 15/1 Khorenatsi str., Yerevan, 375010, Armenia
Y. Zorian , Virage Logic, 47100 Bayside Parkway, Fremont, CA, 94538
pp. 1-4
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing (Abstract)
A. Hlawiczka , Institute of Electronics, Silesian University of Technology in Gliwice, POLAND. e-mail: ahlawiczka@polsl.pl
M. Kopec , Institute of Electronics, Silesian University of Technology in Gliwice, POLAND. e-mail: mkopec@onet.pl
T. Garbolino , Institute of Electronics, Silesian University of Technology in Gliwice, POLAND. e-mail: tgarbolino@polsl.pl
K. Gucwa , Institute of Electronics, Silesian University of Technology in Gliwice, POLAND. e-mail: kgucwa@polsl.pl
pp. 1-4
Instance Generation for SAT-based ATPG (Abstract)
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany. drechsle@informatik.uni-bremen.de
Daniel Tille , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany. tille@informatik.uni-bremen.de
Gorschwin Fey , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany. fey@informatik.uni-bremen.de
pp. 1-4
Power Testing of an FPGA based System Using Modelsim Code Coverage capability (Abstract)
Christian Ibala , CAE Logic Drive, XILINX, Dublin, Ireland. Christian.Ibala@xilinx.com
Khalil Arshak , Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland. Khalil.arshak@ul.ie
Essa Jafer , Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland. Essa.jafer@ul.ie
pp. 1-4
Kishore K. Duganapalli , University of Bremen ITEM, Otto-Hahn-Allee-1 D-28359 Bremen, Germany. E-mail: kishore@item.uni-bremen.de
Ajoy K. Palit , University of Bremen ITEM, Otto-Hahn-Allee-1 D-28359 Bremen, Germany. E-mail: palit@item.uni-bremen.de
Walter Anheier , University of Bremen ITEM, Otto-Hahn-Allee-1 D-28359 Bremen, Germany. E-mail: anheier@item.uni-bremen.de
pp. 1-4
Built in Defect Prognosis for Embedded Memories (Abstract)
Akhil Garg , STMicroelectronics India Pvt Ltd., Plot No.1, Knowledge Park III, Greater Noida, India. Tel: +911204003156, Fax: +911204003160, akhil.garg@st.com
Sravan Kumar Bhaskarani , STMicroelectronics India Pvt Ltd., Plot No.1, Knowledge Park III, Greater Noida, India. Tel: +911204003156, Fax: +911204003160, sravan.bhaskarani@st.com
Prashant Dubey , STMicroelectronics India Pvt Ltd., Plot No.1, Knowledge Park III, Greater Noida, India. Tel: +911204003156, Fax: +911204003160, prashant.dubey@st.com
pp. 1-6
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories (Abstract)
Bashir M. Al-Hashimi , University of Southampton - Electronics and Computer Science (ECS) Department, Mountbatten Building, Highfield, Southampton, SO17 1BJ, United Kingdom. Email: bmh@ecs.soton.ac.uk
Luigi Dilillo , University of Southampton - Electronics and Computer Science (ECS) Department, Mountbatten Building, Highfield, Southampton, SO17 1BJ, United Kingdom. Email: ld3@ecs.soton.ac.uk, l
pp. 1-6
Manifestation of Precharge Faults in High Speed DRAM Devices (Abstract)
Zaid Al-Ars , Delft University of Technology, Faculty of EE, Mathematics and CS, Laboratory of Computer Engineering, Mekelweg 4, 2628 CD Delft, The Netherlands. E-mail: z.al-ars@tudelft.nl
Georgi Gaydadjiev , Delft University of Technology, Faculty of EE, Mathematics and CS, Laboratory of Computer Engineering, Mekelweg 4, 2628 CD Delft, The Netherlands
Said Hamdioui , Delft University of Technology, Faculty of EE, Mathematics and CS, Laboratory of Computer Engineering, Mekelweg 4, 2628 CD Delft, The Netherlands
pp. 1-6
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair (Abstract)
Philipp Ohler , University of Paderborn Germany
Sybille Hellebrand , University of Paderborn Germany
Hans-Joachim Wunderlich , University of Stuttgart Germany
pp. 1-6
An Improved MDCT IP Core Generator with Architectural Model Simulation (Abstract)
Martin Simlastik , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia. martin.simlastik@savba.sk
Marcel Balaz , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia. marcel.balaz@savba.sk
Tomas Pikula , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia. tomas.pikula@savba.sk
Peter Malik , Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia. p.malik@savba.sk
pp. 1-6
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System (Abstract)
Yu-Cherng Hung , Department of Electronic Engineering, National Chinyi University of Technology, Taichung, Taiwan, R.O.C. ychung@ncut.edu.tw
Chiou-Kou Tung , Department of Electronic Engineering, National Chinyi University of Technology, Taichung, Taiwan, R.O.C. tungck@ncut.edu.tw
Shao-Hui Shieh , Department of Electronic Engineering, National Chinyi University of Technology, Taichung, Taiwan, R.O.C. ssh@ncut.edu.tw
Guo-Shing Huang , Department of Electronic Engineering, National Chinyi University of Technology, Taichung, Taiwan, R.O.C. hgs@ncut.edu.tw
pp. 1-4
Automatic generation of circuits for approximate string matching (Abstract)
Tomas Martinek , Faculty of Information Technology, Brno University of Technology, Bo?et?chova 2, Brno, 612 66, Czech Republic. Email: martinto@fit.vutbr.cz
Patrik Beck , CESNET z.s.p.o., Zikova 4, Praque, 160 00, Czech Republic. Email: beck@liberouter.org
Otto Fucik , Faculty of Information Technology, Brno University of Technology, Bo?et?chova 2, Brno, 612 66, Czech Republic. Email: fucik@fit.vutbr.cz
Matej Lexa , Faculty of Informatics, Masaryk University, Botanick? 68a, Brno, 602 00, Czech Republic. Email: lexa@fi.muni.cz
pp. 1-6
About the Efficiency of Real Time Sequences FFT Computing (Abstract)
Sorin Dan Grigorescu , Politehnica University of Bucharest, Romania, Electrical Engineering Faculty, sgrig@electro.masuri.pub.ro
Mircea Covrig , Politehnica University of Bucharest, Romania, Electrical Engineering Faculty, m_cov@amotion.pub.ro
Horia Andrei , Valahia University of Targoviste, Romania, Electrical Engineering Faculty, handrei@valahia.ro
Costin Cepisca , Politehnica University of Bucharest, Romania, Electrical Engineering Faculty, costin@wing.ro
pp. 1-4
Clockless Implementation of LEON2 for Low-Power Applications (Abstract)
Viera Stopjakova , Department of Microelectronics, Slovak University of Technology, Ilkovi?ova 3, 812 19 Bratislava, Slovakia. viera.stopjakova@stuba.sk
Martin Simlastik , Department of Microelectronics, Slovak University of Technology, Ilkovi?ova 3, 812 19 Bratislava, Slovakia. martin.simlastik@stuba.sk
Peter Malik , Institute of Informatics, Slovak Academy of Sciences, D?bravsk? cesta 9, 845 07 Bratislava, Slovakia
Libor Majer , Department of Microelectronics, Slovak University of Technology, Ilkovi?ova 3, 812 19 Bratislava, Slovakia
pp. 1-4
Decomposition of Logic Functions in Reed-Muller Spectral Domain (Abstract)
Stefan Kolodzinski , Pratt&Whitney, Kalisz, Poland
Edward Hrynkiewicz , Institute of Electronics, Silesian University of Technology, Gliwice, Poland
pp. 1-4
Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor (Abstract)
Lucian Prodan , Advanced Computing Systems and Architectures (ACSA) Research Group, Computer Science and Engineering Department, "Politehnica" University of Timisoara. E-mail: lprodan@cs.upt.ro
Mircea Vladutiu , Advanced Computing Systems and Architectures (ACSA) Research Group, Computer Science and Engineering Department, "Politehnica" University of Timisoara. E-mail: mvlad@cs.upt.ro
Alexandru Amaricai , Advanced Computing Systems and Architectures (ACSA) Research Group, Computer Science and Engineering Department, "Politehnica" University of Timisoara. E-mail: alexandru.amaricai@c
Mihai Udrescu , Advanced Computing Systems and Architectures (ACSA) Research Group, Computer Science and Engineering Department, "Politehnica" University of Timisoara. E-mail: mudrescu@cs.upt.ro
Oana Boncalo , Advanced Computing Systems and Architectures (ACSA) Research Group, Computer Science and Engineering Department, "Politehnica" University of Timisoara. E-mail: oana.boncalo@cs.upt.
pp. 1-4
Establishing a New Course in Reconfigurable Logic System Design (Abstract)
Jorgen Norendal , Department of Informatics, University of Oslo, P.O. Box 1080 Blindern, N-0316 Oslo, Norway. Phone: +47 2285 2454, Fax: +47 2285 2401
Jim Torresen , Department of Informatics, University of Oslo, P.O. Box 1080 Blindern, N-0316 Oslo, Norway. Phone: +47 2285 2454, Fax: +47 2285 2401, E-mail: jimtoer@ifi.uio.no
Kyrre Glette , Department of Informatics, University of Oslo, P.O. Box 1080 Blindern, N-0316 Oslo, Norway. Phone: +47 2285 2454, Fax: +47 2285 2401
pp. 1-4
Power Dissipation in Basic Global Clock Distribution Networks (Abstract)
Artur L. Sobczyk , Warsaw University of Technology, Institute of Microelectronics and Optoelectronics ul. Koszykowa 65, 00-661 Warsaw, Poland. A.Sobczyk@elka.pw.edu.pl
Witold A. Pleskacz , Warsaw University of Technology, Institute of Microelectronics and Optoelectronics ul. Koszykowa 65, 00-661 Warsaw, Poland. W.Pleskacz@imio.pw.edu.pl
Arkadiusz W. Luczyk , Warsaw University of Technology, Institute of Microelectronics and Optoelectronics ul. Koszykowa 65, 00-661 Warsaw, Poland. A.Luczyk@elka.pw.edu.pl
pp. 1-4
Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters (Abstract)
Ihor Podolskyy , Lviv Polytechnic National University, University of Information Technology and Management, 12 Stephan Bandera Street, Lviv, 79013, Ukraine. Tel: +380322582578
Roman Bazylevych , Lviv Polytechnic National University, University of Information Technology and Management, 12 Stephan Bandera Street, Lviv, 79013, Ukraine. Tel: +380322582578, rbaz@polynet.lviv.ua
Lubov Bazylevych , Lviv Polytechnic National University, University of Information Technology and Management, 12 Stephan Bandera Street, Lviv, 79013, Ukraine. Tel: +380322582578
pp. 1-4
A Mixed Approach for Unified Logic Diagnosis (Abstract)
A. Virazel , Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier - Universit? de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: Viraz
A. Rousset , Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier - Universit? de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: Rouss
S. Pravossoudovitch , Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier - Universit? de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: Pravo
C. Landrault , Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier - Universit? de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: Landr
P. Girard , Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier - Universit? de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: Girar
A. Bosio , Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier - Universit? de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France. Email: Bosio
pp. 1-4
Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates (Abstract)
Lukas Sekanina , Faculty of Information Technology, Brno University of Technology, Bozetechova 2, 612 66 Brno, Czech Republic. Email: sekanina@fit.vutbr.cz
pp. 1-4
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services (Abstract)
Saeed Safari , University of Tehran, Iran. safari@cad.ece.ut.ac.ir
Mohammad Reza Kakoee , University of Tehran, Iran. kakoee@cad.ece.ut.ac.ir
Zainalabedin Navabi , University of Tehran, Iran. navabi@ece.neu.edu
M. Daneshtalab , University of Tehran, Iran. m.daneshtalab@cad.ece.ut.ac.ir
M.H Neishaburi , University of Tehran, Iran. mhnisha@cad.ece.ut.ac.ir
pp. 1-4
Multiple Errors Detection Technique for RAM (Abstract)
V.N. Yarmolik , Bialystok Technical University, Wiejska 45A, 15-351 Bialystok, Poland. Email: yarmolik@ii.pb.bialystok.pl
A.A. Ivaniuk , Belarussian State University of Informatics and Radioelectronics, P. Brovka Str 6, 220013 Minsk, Belarus. Email: ivaniuk@bsuir.unibel.by
S.B. Musin , Belarussian State University of Informatics and Radioelectronics, P. Brovka Str 6, 220013 Minsk, Belarus. Email: musin@bsuir.unibel.by
pp. 1-4
Test Pattern Generator for Delay Faults (Abstract)
T. Rudnicki , Institute of Electronics, Silesian University of Technology, Poland
A. Hlawiczka , Institute of Electronics, Silesian University of Technology, Poland
pp. 1-4
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques (Abstract)
P. Reviriego , Universidad Carlos III de Madrid Madrid, Spain
O. Ruano , Universidad Antonio de Nebrija Madrid, Spain
P. Reyes , Universidad Antonio de Nebrija Madrid, Spain
J.A. Maestro , Universidad Antonio de Nebrija Madrid, Spain
L. Sterpone , Politecnico di Torino Torino, Italy
pp. 1-6
A Novel Parity Bit Scheme for SBox in AES Circuits (Abstract)
M. L. Flottes , Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier, Universit? Montpellier II / CNRS UMR 5506, 161 rue Ada, 34392 Montpellier Cedex 5, France. flottes@
G. Di Natale , Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier, Universit? Montpellier II / CNRS UMR 5506, 161 rue Ada, 34392 Montpellier Cedex 5, France. dinatale
B. Rouzeyre , Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier, Universit? Montpellier II / CNRS UMR 5506, 161 rue Ada, 34392 Montpellier Cedex 5, France. rouzeyre
pp. 1-5
Designing Time-to-Digital Converter for Asynchronous ADCs (Abstract)
Marek Miskowicz , AGH University of Science and Technology, Department of Electronics. E-mail: miskow@agh.edu.pl
Dariusz Koscielnik , AGH University of Science and Technology, Department of Electronics. E-mail: koscieln@agh.edu.pl
pp. 1-6
Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization (Abstract)
Lukas Ruckay , ASICentrum, Novodvorsk? 994, 142 21 Prague, Czech Republic; Department of Circuit Theory, Faculty of Electrical Engineering CTU Prague, Technick? 2, 166 27 Prague, Czech Republic.
Jiri Nedved , ASICentrum, Novodvorsk? 994, 142 21 Prague, Czech Republic
pp. 1-6
RF Transformer Model Parameters Measurement (Abstract)
V. Dumbrava , Kaunas University of Technology, Department of Signal Processing, Studentu str. 50-340, LT-51368, Kaunas, Lithuania
L. Svilainis , Kaunas University of Technology, Department of Signal Processing, Studentu str. 50-340, LT-51368, Kaunas, Lithuania. svilnis@ktu.lt
pp. 1-5
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits (Abstract)
M. B. Santos , IST / INESC-ID Lisboa, R. Alves Redol, 9, 3?, 1000-029 Lisboa, Portugal
J. Semiao , IST / INESC-ID Lisboa, R. Alves Redol, 9, 3?, 1000-029 Lisboa, Portugal; Univ. of Algarve, School of Technology, Campus da Penha, 8005-139 Faro, Portugal, jsemiao@ualg.pt
F. Vargas , PUCRS, Electrical Engineering Dept., Av. Ipiranga, 6681, 90619-900 Porto Alegre, Brazil, vargas@computer.org
J. P. Teixeira , IST / INESC-ID Lisboa, R. Alves Redol, 9, 3?, 1000-029 Lisboa, Portugal, paulo.teixeira@ist.utl.pt
J. J. Rodriguez-Andina , Univ. of Vigo, Dept. de Tecnolog?a Electr?nica, Campus Universitario, 36310 Vigo, Spain, jjrdguez@uvigo.es
I. C. Teixeira , IST / INESC-ID Lisboa, R. Alves Redol, 9, 3?, 1000-029 Lisboa, Portugal
J. Freijedo , IST / INESC-ID Lisboa, R. Alves Redol, 9, 3?, 1000-029 Lisboa, Portugal; Univ. of Vigo, Dept. de Tecnolog?a Electr?nica, Campus Universitario, 36310 Vigo, Spain
pp. 1-6
A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs (Abstract)
Luis F. Lemos , Dep. of Electrical Engineering ? ISEPLABORIS, Rua Dr. Antonio Bernardino de Almeida, 4200-072 Porto - PORTUGAL. lfl@isep.ipp.pt, gca@isep.ipp.pt
Gustavo R. Alves , Dep. of Electrical Engineering ? ISEPLABORIS, Rua Dr. Antonio Bernardino de Almeida, 4200-072 Porto - PORTUGAL. gca@isep.ipp.pt
Jose M. Ferreira , Dep. of Electrical and Computer Engineering ? FEUP, Rua Dr. Roberto Frias, 4200-465 Porto - PORTUGAL. jmf@fe.up.pt
Manuel G. Gericota , Dep. of Electrical Engineering ? ISEPLABORIS, Rua Dr. Antonio Bernardino de Almeida, 4200-072 Porto - PORTUGAL. mgg@isep.ipp.pt, gca@isep.ipp.pt
pp. 1-6
Flip-Flops and Scan-Path Elements for Nanoelectronics (Abstract)
H. T. Vierhaus , Brandenburg University of Technology Cottbus, Computer Science Institute, P. O. Box 10 13 44, D-03013 Cottbus, Germany
R. Kothe , Brandenburg University of Technology Cottbus, Computer Science Institute, P. O. Box 10 13 44, D-03013 Cottbus, Germany
pp. 1-6
Pawel Pawlowski , Chair, Control and System Engineering, Division of Signal Processing and Electronic Circuits, Pozna? University of Technology, Pozna?, Poland. e-mail: Pawel.Pawlowski@put.poznan.pl
Adam Dabrowski , Chair, Control and System Engineering, Division of Signal Processing and Electronic Circuits, Pozna? University of Technology, Pozna?, Poland. e-mail: Adam.Dabrowski@put.poznan.pl
Mario Scholzel , Department of Computer Science, Brandenburg University of Technology, Cottbus, Germany. e-mail: mas@informatik.tu-cottbus.de
pp. 1-6
Dedicated architecture for double precision matrix multiplication in supercomputing environment (Abstract)
K. Wiatr , Dept. of Electronics, ACK "Cyfronet", AGH Univ. of Science and Tech, Cracow, POLAND
P. Russek , Dept. of Electronics, ACK "Cyfronet", AGH Univ. of Science and Tech., Cracow, POLAND
pp. 1-4
Design issues of a low frequency low-pass filter for medical applications using CMOS technology (Abstract)
Andras Timar , Budapest University of Technology and Economics Department of Electron Devices, 3 Goldmann Gy?rgy sq., Budapest, Hungary, Phone: (+36-1) 463- 1870, Fax: (+36-1) 463-2973. e-mail: t
Marta Rencz , Budapest University of Technology and Economics Department of Electron Devices, 3 Goldmann Gy?rgy sq., Budapest, Hungary, Phone: (+36-1) 463- 1870, Fax: (+36-1) 463-2973. e-mail: r
pp. 1-4
Feasibility of Image Compression in FPGA based Neural Networks (Abstract)
Karel Vlcek , Department of Computer Science, V?B - Technical University of Ostrava, 17. listopadu 15, 708 33, Ostrava-Poruba, Czech Republic. karel.vlcek@vsb.cz
Vladimir Havel , Department of Computer Science, V?B - Technical University of Ostrava, 17. listopadu 15, 708 33, Ostrava-Poruba, Czech Republic. vladimir.havel@vsb.cz
pp. 1-3
IP Integration Overhead Analysis in System-on-Chip Video Encoder (Abstract)
Ari Kulmala , Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, Korkeakoulunkatu 1, FI-33101 Tampere, Finland. ari.kulmala@tut.fi
Antti Rasmus , Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, Korkeakoulunkatu 1, FI-33101 Tampere, Finland. antti.rasmus@tut.fi
Erno Salminen , Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, Korkeakoulunkatu 1, FI-33101 Tampere, Finland
Timo D. Hamalainen , Tampere University of Technology, Institute of Digital and Computer Systems, P.O. Box 553, Korkeakoulunkatu 1, FI-33101 Tampere, Finland
pp. 1-4
Quadrature-Phase Topology of a High Frequency Ring Oscillator (Abstract)
Abel Vamos , Budapest University of Technology and Economics Department of Electron Devices, H-1111 Budapest, Goldmann Gy?rgy t?r 3, Hungary, Phone: (+36-1) 463-2702, Fax: (+36-1) 463-2973, e-m
pp. 1-4
Reticle Exposure Plans for Multi-Project Wafers (Abstract)
Da-Wei Hsu , Computer Science and Engineering, Yuan Ze University, Chung-Li, Taiwan
Rung-Bin Lin , Computer Science and Engineering, Yuan Ze University, Chung-Li, Taiwan
Meng-Chiou Wu , Computer Science and Engineering, Yuan Ze University, Chung-Li, Taiwan
Ming-Hsine Kuo , Computer Science and Engineering, Yuan Ze University, Chung-Li, Taiwan
pp. 1-4
Low cost, low power, intelligent brake temperature sensor system for automotive applications (Abstract)
Gyula Bakonyi-Kiss , Budapest University of Technology and Economics, H-1521 Budapest, Hungary. E-mail: achtonus@gmail.com
Zoltan Szucs , Budapest University of Technology and Economics, H-1521 Budapest, Hungary. E-mail: szucs@eet.bme.hu
pp. 1-4
Determining MOSFET Parameters in Moderate Inversion (Abstract)
Wladyslaw Grabinski , Chemin de la Dauphine 20, CH-1291 Commugny, Switzerland
Matthias Bucher , Technical University of Crete, Electronics Laboratory, Polytechnioupolis, GR-16673 Chania, Greece
Antonios Bazigos , National Technical University of Athens, Zographou, GR-15773 Athens, Greece
pp. 1-4
TTTC: Test Technology Technical Council (PDF)
pp. nil4-nil6
Papers
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System (Abstract)
Jiri Kvasnicka , Department of Computer Science and Engineering, Czech Technical University in Prague, Karlovo nam. 13, 121 35 Prague 2. e-mail: kvasnj1@fel.cvut.cz
Hana Kubatova , Department of Computer Science and Engineering, Czech Technical University in Prague, Karlovo nam. 13, 121 35 Prague 2. e-mail: kubatova@fel.cvut.cz
Pavel Kubalik , Department of Computer Science and Engineering, Czech Technical University in Prague, Karlovo nam. 13, 121 35 Prague 2. e-mail: xkubalik@fel.cvut.cz
pp. 1-4
Intrusion Detection System Intended for Multigigabit Networks (Abstract)
Jan Korenek , Faculty of Information Technology, Brno University of Technology, Bo?et?chova 2, Brno, 612 66, Czech Republic. Email: korenek@fit.vutbr.cz
Petr Kobiersky , CESNET, z. s. p. o., Zikova 4, Praha 6, 160 00, Czech Republic. Email: xkobie00@liberouter.org
pp. 1-4
Open Defects Caused by Scratches and Yield Modelling in Deep Sub-Micron Integrated Circuit (Abstract)
Wlodzimierz Jonca , Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland. Email: wjonca@gmail.com
pp. 1-4
Transition Faults Testing Based on Functional Delay Tests (Abstract)
Kestutis Motiejunas , Software Engineering Department, Kaunas University of Technology, Student? 50-406., LT-51368 Kaunas, Lithuania
Vacius Jusas , Software Engineering Department, Kaunas University of Technology, Student? 50-406., LT-51368 Kaunas, Lithuania
Rimantas Seinauskas , Software Engineering Department, Kaunas University of Technology, Student? 50-406., LT-51368 Kaunas, Lithuania
Eduardas Bareisa , Software Engineering Department, Kaunas University of Technology, Student? 50-406., LT-51368 Kaunas, Lithuania
pp. 1-5
Aristides Efthymiou , School of Informatics, University of Edinburgh, Edinburgh EH9 3JZ, UK. Email: aris.efthymiou@ed.ac.uk
pp. 1-6
Prototyping Generators for on-line test vector generation based on PSL properties (Abstract)
Dominique Borrione , Tima Laboratory, 46 avenue F?lix Viallet 38031 Grenoble Cedex, France. dominique.borrione@imag.fr
Yann Oddos , Tima Laboratory, 46 avenue F?lix Viallet 38031 Grenoble Cedex, France. yann.oddos@imag.fr
Katell Morin-Allory , Tima Laboratory, 46 avenue F?lix Viallet 38031 Grenoble Cedex, France. katell.morin@imag.fr
pp. 1-6
On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata (Abstract)
Christian Herde , Carl-von-Ossietzky University, Oldenburg, Germany
Marc Herbstritt , Albert-Ludwigs-University Freiburg im Breisgau, Germany
Bernd Becker , Albert-Ludwigs-University Freiburg im Breisgau, Germany
Erika Abraham , Albert-Ludwigs-University Freiburg im Breisgau, Germany
pp. 1-6
Claudionor Jose N. Coelho , Universidade Federal de Minas Gerais - DCC, Av. Antonio Carlos, 6627, Pampulha, Belo Horizonte-MG, Brazil. vivas@dcc.ufmg.br, marsha@dcc.ufmg.br, otavio@dcc.ufmg.br, coelho@dcc.ufm
Antonio O. Fernandes , Universidade Federal de Minas Gerais - DCC, Av. Antonio Carlos, 6627, Pampulha, Belo Horizonte-MG, Brazil. vivas@dcc.ufmg.br, marsha@dcc.ufmg.br, otavio@dcc.ufmg.br
Marcia C. M. Oliveira , Universidade Federal de Minas Gerais - DCC, Av. Antonio Carlos, 6627, Pampulha, Belo Horizonte-MG, Brazil. vivas@dcc.ufmg.br, marsha@dcc.ufmg.br, otavio@dcc.ufmg.br
Fabricio V. Andrade , Universidade Federal de Minas Gerais - DCC, Av. Antonio Carlos, 6627, Pampulha, Belo Horizonte-MG, Brazil; Centro Federal de Educa??o Tecnol?gica de Minas Gerais - DECOM, Av. Amazo
pp. 1-6
Debug Patterns for Efficient High-level SystemC Debugging (Abstract)
Christian Haufe , AMD Saxony LLC&Co. KG, 01109 Dresden, Germany. christian.haufe@amd.com
Frank Rogin , Fraunhofer IIS / EAS Dresden 01069 Dresden, Germany. frank.rogin@eas.iis.fraunhofer.de
Erhard Fehlauer , Fraunhofer IIS / EAS Dresden 01069 Dresden, Germany. erhard.fehlauer@eas.iis.fraunhofer.de
Sebastian Ohnewald , AMD Saxony LLC&Co. KG, 01109 Dresden, Germany. sebastian.ohnewald@amd.com
pp. 1-6
Memory Based Analogue Signal Generation Implementation Issues for BIST (Abstract)
I. Grout , ECE Department, University of Limerick, Limerick, Ireland.
J. Ryan , ECE Department, University of Limerick, Limerick, Ireland.
T. O. Shea , ECE Department, University of Limerick, Limerick, Ireland.
pp. 1-6
Developing Virtual ADC Testing Environment in MAPLE (Abstract)
Jiri Hospodka , Department of Circuit Theory, Faculty of Electrical Engineering CTU Prague, Technick? 2, 166 27 Prague, Czech Republic. e-mail: Hospodka@fel.cvut.cz
Pravoslav Martinek , Department of Circuit Theory, Faculty of Electrical Engineering CTU Prague, Technick? 2, 166 27 Prague, Czech Republic. e-mail: Martinek@fel.cvut.cz
Ondrej Subrt , Department of Circuit Theory, Faculty of Electrical Engineering CTU Prague, Technick? 2, 166 27 Prague, Czech Republic; ASICentrum, Novodvorsk? 994, 142 21 Prague, Czech Republic.
Petr Struhovsky , Department of Circuit Theory, Faculty of Electrical Engineering CTU Prague, Technick? 2, 166 27 Prague, Czech Republic. e-mail: Struhovsky@centrum.cz
pp. 1-5
ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing (Abstract)
Z. Piatek , Warsaw University of Technology, Poland
W. A. Pleskacz , Warsaw University of Technology, Poland
J. F. Kolodziejski , Institute of Electron Technology, Warsaw, Poland
pp. 1-5
MEMS Testing by Vibrating Capacitor (Abstract)
J. Mizsei , Budapest University of Techn. and Economics, Department of Electron Devices, Goldmann Gy. ter 3. H-1521 Budapest, Hungary, e-mail: mizsei@eet.bme.hu
M. Reggente , Budapest University of Techn. and Economics, Department of Electron Devices, Goldmann Gy. ter 3. H-1521 Budapest, Hungary
pp. 1-4
Author Index (PDF)
pp. 433-434
advert (PDF)
pp. nil1-nil3