New Strategies for System-Level Design (PDF)
Covers (PDF)
Covers (PDF)
Copyright page (PDF)
Foreword to the IEEE DDECS 2007 Workshop (PDF)
Workshop Committees (PDF)
Table of contents (PDF)
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling (Abstract)
A Testable Random Bit Generator based on a High Resolution Phase Noise Detection (Abstract)
Test Pattern Compression Based on Pattern Overlapping (Abstract)
Layout to Logic Defect Analysis for Hierarchical Test Generation (Abstract)
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips (Abstract)
Resource Constrained Co-synthesis of Self-reconfigurable SOPCs (Abstract)
Extended Fault Detection Techniques for Systems-on-Chip (Abstract)
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing (Abstract)
Architecture for Highly Reliable Embedded Flash Memories (Abstract)
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology (Abstract)
Accurately Determining Bridging Defects from Layout (Abstract)
FPGA Implementaton of Strongly Parallel Histogram Equalization (Abstract)
Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's (Abstract)
Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder (Abstract)
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling (Abstract)
A PMT interface for the Optical Module front-end of a neutrino underwater telescope (Abstract)
A proposal for ASM++ diagrams (Abstract)
Lightweight Multi-threaded Network Processor Core in FPGA (Abstract)
Parts Obsolescence Challenges for the Electronics Industry (Abstract)
Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation (Abstract)
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing (Abstract)
Instance Generation for SAT-based ATPG (Abstract)
Power Testing of an FPGA based System Using Modelsim Code Coverage capability (Abstract)
Built in Defect Prognosis for Embedded Memories (Abstract)
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories (Abstract)
Manifestation of Precharge Faults in High Speed DRAM Devices (Abstract)
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair (Abstract)
An Improved MDCT IP Core Generator with Architectural Model Simulation (Abstract)
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System (Abstract)
Automatic generation of circuits for approximate string matching (Abstract)
About the Efficiency of Real Time Sequences FFT Computing (Abstract)
Clockless Implementation of LEON2 for Low-Power Applications (Abstract)
Decomposition of Logic Functions in Reed-Muller Spectral Domain (Abstract)
Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor (Abstract)
Establishing a New Course in Reconfigurable Logic System Design (Abstract)
Power Dissipation in Basic Global Clock Distribution Networks (Abstract)
Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters (Abstract)
A Mixed Approach for Unified Logic Diagnosis (Abstract)
Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates (Abstract)
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services (Abstract)
Multiple Errors Detection Technique for RAM (Abstract)
Test Pattern Generator for Delay Faults (Abstract)
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques (Abstract)
A Novel Parity Bit Scheme for SBox in AES Circuits (Abstract)
Designing Time-to-Digital Converter for Asynchronous ADCs (Abstract)
Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization (Abstract)
RF Transformer Model Parameters Measurement (Abstract)
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits (Abstract)
A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs (Abstract)
Flip-Flops and Scan-Path Elements for Nanoelectronics (Abstract)
Dedicated architecture for double precision matrix multiplication in supercomputing environment (Abstract)
Design issues of a low frequency low-pass filter for medical applications using CMOS technology (Abstract)
Feasibility of Image Compression in FPGA based Neural Networks (Abstract)
IP Integration Overhead Analysis in System-on-Chip Video Encoder (Abstract)
Quadrature-Phase Topology of a High Frequency Ring Oscillator (Abstract)
Reticle Exposure Plans for Multi-Project Wafers (Abstract)
Low cost, low power, intelligent brake temperature sensor system for automotive applications (Abstract)
Determining MOSFET Parameters in Moderate Inversion (Abstract)
TTTC: Test Technology Technical Council (PDF)
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System (Abstract)
Intrusion Detection System Intended for Multigigabit Networks (Abstract)
Open Defects Caused by Scratches and Yield Modelling in Deep Sub-Micron Integrated Circuit (Abstract)
Transition Faults Testing Based on Functional Delay Tests (Abstract)
Prototyping Generators for on-line test vector generation based on PSL properties (Abstract)
On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata (Abstract)
Debug Patterns for Efficient High-level SystemC Debugging (Abstract)
Memory Based Analogue Signal Generation Implementation Issues for BIST (Abstract)
Developing Virtual ADC Testing Environment in MAPLE (Abstract)
ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing (Abstract)
MEMS Testing by Vibrating Capacitor (Abstract)
Author Index (PDF)
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