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Defect Based Testing, IEEE International Workshop on (2004)
Napa Valley, CA, USA
Apr. 5, 2004 to Mar. 31, 2004
ISBN: 0-7803-8950-6
TABLE OF CONTENTS
Papers

Built-in current sensor for IDDQ test (Abstract)

D.M.H. Walker , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Bin Xue , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 3-9

Welcome Message (Abstract)

pp. v

An improved method for i/sub DDT/ testing in the presence of leakage and process variation (Abstract)

Anis Nazer , Dept. of Electr. & Comput. Eng., Beirut American Univ., Lebanon
Ali Chehab , Dept. of Electr. & Comput. Eng., Beirut American Univ., Lebanon
Ayman Kayssi , Dept. of Electr. & Comput. Eng., Beirut American Univ., Lebanon
pp. 11-16

Comparison of wafer-level spatial I/sub DDQ/ estimation methods: NNR versus NCR (Abstract)

D.M.H. Walker , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
S.S. Sabade , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 17-22

Calibrating power supply signal measurements for process and probe card variations (Abstract)

D. Acharyya , Dept. of Comput. Sci. & Electr. Eng.,, Maryland Univ., Baltimore, MD, USA
J. Plusquellic , Dept. of Comput. Sci. & Electr. Eng.,, Maryland Univ., Baltimore, MD, USA
pp. 23-30

Doing more with less: a recipe for rapid IDDQ development (Abstract)

R. Ackerman , Sharp Microelectron. of the Americas, Camas, WA, USA
pp. 33-42

Mixed-signal LSI relationship among measurement accuracy, yield, and test time (Abstract)

H. Kohinata , Agilent Technol., Inc., Japan
S. Fukumoto , Dept. of Electr. & Comput. Eng., Beirut American Univ., Lebanon
M. Arai , Dept. of Comput. Sci. & Electr. Eng.,, Maryland Univ., Baltimore, MD, USA
pp. 43-45

On the effectiveness of detecting small delay defects in the slack interval (Abstract)

A.D. Singh , Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA
Haihua Yan , Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA
pp. 49-53

On the potential of flush delay for characterization and test optimization (Abstract)

C. Thibeault , Dept. of Electr. Eng., Ecole de technologie superieure, Montreal, Que., Canada
pp. 55-60

At-speed test for path delay faults using practical techniques (Abstract)

Jing Wang , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Wangqi Qiu , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Xiang Lu , Dept. of Electr. & Comput. Eng., Beirut American Univ., Lebanon
pp. 61-66

Delay testing based on transition faults propagated to all reachable outputs (Abstract)

B. Vaidya , Northeastern Univ., Boston, MA, USA
M.B. Tahoori , Northeastern Univ., Boston, MA, USA
pp. 67-75

On correlating structural tests with functional tests for speed binning (Abstract)

M. Abadir , Somerset Design Center, Motorola Inc., Austin, TX, USA
Jing Zeng , Somerset Design Center, Motorola Inc., Austin, TX, USA
pp. 79-83

Fault diagnosis of a GHz CMOS LNA using high-speed ADC-based BIST (Abstract)

J. Liobe , Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
M. Margala , Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
pp. 85-89

Automatic test pattern generation for resistive bridging faults (Abstract)

P. Engelke , Albert-Ludwigs-Univ., Freiburg, Germany
M. Renovell , Dept. of Electr. & Comput. Eng., Beirut American Univ., Lebanon
I. Polian , Albert-Ludwigs-Univ., Freiburg, Germany
pp. 91-96

A memory built-in self-diagnosis design with syndrome compression (Abstract)

Rei-Fu Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chin-Lung Su , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 99-104

Test volume reduction via flip-flop compatibility analysis for balanced parallel scan (Abstract)

A. Singh , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
A. Chatterjee , Georgia Inst. of Technol., Atlanta, GA, USA
M. Ashouei , Georgia Inst. of Technol., Atlanta, GA, USA
pp. 105-109

"ITRS test challenges need defect based test: fact or fiction?" (Abstract)

J. Plusquellic , Georgia Inst. of Technol., Atlanta, GA, USA
pp. 112

Author Index (PDF)

pp. 113

Table of Contents (PDF)

pp. iii-iv

Copyright (PDF)

pp. ii
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