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Defect Based Testing, IEEE International Workshop on (2000)
Montreal, Canada
Apr. 30, 2000 to Apr. 30, 2000
ISBN: 0-7695-0637-2
TABLE OF CONTENTS

Reviewers (PDF)

pp. ix
Session 1: Deep Sub-Micron I<sub>DDQ</sub> Testing

Feasibility of Current Measurements in Sub 0.25 micron VLSIs (Abstract)

Ali Keshavarzi , Intel Corporation
Shekhar Borkar , Intel Corporation
Vivek De , Intel Corporation
pp. 3

A New Scheme for Effective I<sub>DDQ</sub> Testing in Deep Submicron (Abstract)

Y. Tsiatouhas , ISD S.A., Chalandri, Greece; University of Patras, Greece
Y. Moisiadis , Uniersity of Athens, Athens, Greece
Th. Haniotakis , Uniersity of Athens, Athens, Greece; University of Patras, Greece
D. Nikolos , University of Patras, Greece
A. Arapoyanni , Uniersity of Athens, Athens, Greece
pp. 9
Session 2: Defect Oriented Testing

Defect-Based Testing for Fabless Companies (Abstract)

J. Khare , Level One Communications,Sacramento, CA
H. T. Heineken , Level One Communications,Sacramento, CA
pp. 23

Optimal Clustering and Statistical Identification of Defective ICs using I<sub>DDQ</sub> Testing (Abstract)

A. Rao , PalmChip Corporation, Loveland, CO
A. P. Jayasumana , Colorado State University, Fort Collins
Y. K. Malaiya , Colorado State University, Fort Collins
pp. 30
Session 3: Current Measurement And Yield

IDDQ Profiles: A Technique to Reduce Test Escape and Yield Loss during IDDQ Testing (Abstract)

Hugo Cheung , Burr-Brown Corporation, Tucson, AZ
Sandeep K. Gupta , University of Southern California, Los Angeles, CA
pp. 45

A Practical Implementation of BICS for Safety-Critical Applications (Abstract)

Patricia A. Smith , Sandia National Laboratories, Albuquerque, NM
David V. Campbell , Sandia National Laboratories, Albuquerque, NM
pp. 51

Charge Based Testing (CBT) of submicron CMOS SRAMs (Abstract)

M. Rosales , Balearic Islands University, Spain
I. de Pa? , Balearic Islands University, Spain
J. Segura , Balearic Islands University, Spain
C. F. Hawkins , The University of New Mexico and Sandia National Labs.
J. Soden , Sandia National Labs.
pp. 57
Session 4: Current and Voltage Test Techniques

Testing of Deep-Submicron Battery-Operated Circuits using New Fast Current Monitoring Scheme (Abstract)

Martin Margala , University of Alberta, Edmonton, Canada
Ivan Pecuh , PMC-Sierra, Burnaby, Canada
pp. 65

IDDQ Testable Design of Static CMOS PLAs (Abstract)

Masaki Hashizume , The Univ. of Tokushima, Japan
Hiroshi Hoshika , The Univ. of Tokushima, Japan
Hiroyuki Yotsuyanagi , The Univ. of Tokushima, Japan
Takeomi Tamesada , The Univ. of Tokushima, Japan
pp. 70

On-Line Testing and Diagnosis Scheme for Intermediate Voltage Values Affecting Bus Lines (Abstract)

Cecilia Metra , D.E.I.S. University of Bologna, Italy
Michele Favalli , D.I. University of Ferrara, Italy
Bruno Ricc? , D.E.I.S. University of Bologna, Italy
pp. 76

Author Index (PDF)

pp. 82
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