Design, Automation & Test in Europe Conference & Exhibition (2012)
Mar. 12, 2012 to Mar. 16, 2012
On-chip interconnection networks consume a significant fraction of the chip's power, and the rapidly increasing core counts in future technologies is going to further aggravate their impact on the chip's overall power consumption. A large fraction of the traffic originates not from data messages exchanged between sharing cores, but from the communication between the cores and intermediate hardware structures (i.e., directories) for the purpose of maintaining coherence in the presence of conflicting updates. In this paper, we propose Dynamic Directories, a method allowing the directories to be placed arbitrarily in the chip by piggy-backing the virtual to physical address translation. This eliminates a large fraction of the on-chip interconnect traversals, hence reducing the power consumption. Through trace-driven and cycle-accurate simulation in a range of scientific and Map-Reduce applications, we show that our technique reduces the power and energy expended by the on-chip interconnect by up to 37% (16.4% on average) with negligible hardware overhead and a small improvement in performance (1.3% on average).
power integrated circuits, cache storage, cores, integrated circuit modelling, network-on-chip, map-reduce applications, dynamic directories, reducing on-chip interconnect power, multicores, chip overall power consumption, data messages, piggy-backing, through trace-driven, cycle-accurate simulation, Tiles, System-on-a-chip, Multicore processing, Coherence, Integrated circuit interconnections, Principal component analysis, Multicore architecture, On-chip networks, Non-uniform caches
"Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores," Design, Automation & Test in Europe Conference & Exhibition(DATE), Dresden Germany, 2012, pp. 479-484.