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Design, Automation & Test in Europe Conference & Exhibition (2011)
Grenoble France
Mar. 14, 2011 to Mar. 18, 2011
ISSN: 1530-1591
ISBN: 978-1-61284-208-0
pp: 1-4
A genetic programming-based circuit synthesis method is proposed that enables to globally optimize the number of gates in circuits that have already been synthesized using common methods such as ABC and SIS. The main contribution is a proposal for a new fitness function that enables to significantly reduce the fitness evaluation time in comparison to the state of the art. The fitness function performs optimized equivalence checking using a SAT solver. It is shown that the equivalence checking time can significantly be reduced when knowledge of the parent circuit and its mutated offspring is taken into account. For a cost of a runtime, results of conventional synthesis conducted using SIS and ABC were improved by 20-40% for the LGSynth93 benchmarks.
logic gates, circuit optimisation, combinational circuits, computability, equivalent circuits, genetic algorithms, logic design, mutated offspring, global postsynthesis optimization, combinational circuit, genetic programming-based circuit synthesis, circuit gates, fitness function, fitness evaluation time, SAT solver, equivalence checking time, parent circuit, Logic gates, Genetic programming, Indexes, Benchmark testing, Runtime, Circuit synthesis, Analog circuits

"A global postsynthesis optimization method for combinational circuits," Design, Automation & Test in Europe Conference & Exhibition(DATE), Grenoble France, 2011, pp. 1-4.
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