Design, Automation & Test in Europe Conference & Exhibition (2011)
Mar. 14, 2011 to Mar. 18, 2011
The determination of the optical flow is a central problem in image processing, as it allows to describe how an image changes over time by means of a numerical vector field. The estimation of the optical flow is however a very complex problem, which has been faced using many different mathematical approaches. A large body of work has been recently published about variational methods, following the technique for total variation minimization proposed by Chambolle. Still, their hardware implementations do not offer good performance in terms of frames that can be processed per time unit, mainly because of the complex dependency scheme among the data. In this work, we propose a highly parallel and accelerated FPGA implementation of the Chambolle algorithm, which splits the original image into a set of overlapping sub-frames and efficiently exploits the reuse of intermediate results. We validate our hardware on large frames (up to 1024 × 768), and the proposed approach significantly improves state-of-the-art implementations, reaching up to 76× speedups, which enables real-time frame rates even at high resolutions.
image sequences, field programmable gate arrays, image resolution, FPGA, Chambolle algorithm, image processing, numerical vector field, optical flow estimation, total variation minimization, Hardware, Arrays, Optical imaging, Field programmable gate arrays, Adaptive optics, Estimation, Memory management
"A high-performance parallel implementation of the Chambolle algorithm," Design, Automation & Test in Europe Conference & Exhibition(DATE), Grenoble France, 2011, pp. 1-6.