Design, Automation & Test in Europe Conference & Exhibition (2011)
Mar. 14, 2011 to Mar. 18, 2011
Scratch Pad Memory (SPM), a software-controlled on-chip memory, has been widely adopted in many embedded systems due to its small area and low power consumption. As technology scaling reaches the sub-micron level, leakage energy consumption is surpassing dynamic energy consumption and becoming a critical issue. In this paper, we propose a novel hybrid SPM which consists of non-volatile memory (NVM) and SRAM to take advantage of the ultra-low leakage power consumption and high density of NVM as well as the efficient writes of SRAM. A novel dynamic data allocation algorithm is proposed to make use of the full potential of both NVM and SRAM. According to the experimental results, with the help of the proposed algorithm, the novel hybrid SPM architecture can reduce memory access time by 18.17%, dynamic energy by 24.29%, and leakage power by 37.34% on average compared with a pure SRAM based SPM with the same size area.
system-on-chip, embedded systems, energy consumption, low-power electronics, random-access storage, dynamic data allocation algorithm, energy efficient hybrid on-chip scratch pad memory, nonvolatile memory, software-controlled on-chip memory, embedded systems, low power consumption, SRAM, ultra-low leakage power consumption, Nonvolatile memory, Random access memory, Resource management, Heuristic algorithms, System-on-a-chip, Computer architecture, Energy consumption
"Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory," Design, Automation & Test in Europe Conference & Exhibition(DATE), Grenoble France, 2011, pp. 1-6.