The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2010)
Dresden Germany
Mar. 8, 2010 to Mar. 12, 2010
ISSN: 1530-1591
ISBN: 978-1-4244-7054-9
TABLE OF CONTENTS

Tutorials [9 abstracts] (PDF)

pp. xlv-xlviii

All things are connected (PDF)

Alberto Sangiovanni-Vincentelli , UC Berkeley and Cadence, US
pp. 1

Loosely Time-Triggered Architectures for Cyber-Physical Systems (PDF)

Albert Benveniste , IRISA/INRIA, Campus de Beaulieu, 35042 Rennes cedex, France
pp. 3-8

Energy-efficient real-time task scheduling with temperature-dependent leakage (PDF)

Chuan-Yue Yang , Department of Computer Science and Information Engineering, National Taiwan University, Taiwan
Jian-Jia Chen , Computer Engineering and Networks Laboratory (TIK), ETH Zürich, Germany
Lothar Thiele , Computer Engineering and Networks Laboratory (TIK), ETH Zürich, Germany
Tei-Wei Kuo , Department of Computer Science and Information Engineering, National Taiwan University, Taiwan
pp. 9-14

Predicting energy and performance overhead of Real-Time Operating Systems (PDF)

Sandro Penolazzi , Dept. of Electronic Systems, School of ICT, KTH, Stockholm, Sweden
Ingo Sander , Dept. of Electronic Systems, School of ICT, KTH, Stockholm, Sweden
Ahmed Hemani , Dept. of Electronic Systems, School of ICT, KTH, Stockholm, Sweden
pp. 15-20

Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling (PDF)

Min Bao , Linköping University, Sweden
Alexandru Andrei , Ericsson, Linköping, Sweden
Petru Eles , Linköping University, Sweden
Zebo Peng , Linköping University, Sweden
pp. 21-26

Multicore soft error rate stabilization using adaptive dual modular redundancy (PDF)

Ramakrishna Vadlamani , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, United States
Jia Zhao , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, United States
Wayne Burleson , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, United States
Russell Tessier , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, United States
pp. 27-32

A fully-asynchronous low-power framework for GALS NoC integration (PDF)

Yvain Thonnart , CEA-LETI, MINATEC, Grenoble, France
Pascal Vivet , CEA-LETI, MINATEC, Grenoble, France
Fabien Clermidy , CEA-LETI, MINATEC, Grenoble, France
pp. 33-38

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller (PDF)

Xiaowen Chen , National University of Defense Technology, 410073, Changsha, China
Zhonghai Lu , KTH-Royal Institute of Technology, 16440 Kista, Stockholm, Sweden
Axel Jantsch , KTH-Royal Institute of Technology, 16440 Kista, Stockholm, Sweden
Shuming Chen , National University of Defense Technology, 410073, Changsha, China
pp. 39-44

MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture (PDF)

Sergio V. Tota , Dipartimento di Elettronica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129, Italy
Mario R. Casu , Dipartimento di Elettronica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129, Italy
Massimo Ruo Roch , Dipartimento di Elettronica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129, Italy
Luca Rostagno , Dipartimento di Elettronica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129, Italy
Maurizio Zamboni , Dipartimento di Elettronica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I-10129, Italy
pp. 45-50

AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs (PDF)

Lin Huang , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China
pp. 51-56

Statistical SRAM analysis for yield enhancement (Abstract)

Paul Zuber , Digital Components, IMEC-Belgium
Miguel Miranda , Digital Components, IMEC-Belgium
Petr Dobrovolny , Digital Components, IMEC-Belgium
Koen van der Zanden , Digital Components, IMEC-Belgium
Jong-Hoon Jung , Design Technology Team, System LSI Division, Samsung Electronics Co.-Korea
pp. 57-62

Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme (PDF)

Mingjing Chen , CSE Department, UC San Diego, La Jolla, CA 92093, USA
Alex Orailoglu , CSE Department, UC San Diego, La Jolla, CA 92093, USA
pp. 63-68

Scan based methodology for reliable state retention power gating designs (PDF)

Sheng Yang , School of ECS, University of Southampton, UK
Bashir M. Al-Hashimi , School of ECS, University of Southampton, UK
David Flynn , ARM, Cambridge, UK
Saqib Khursheed , School of ECS, University of Southampton, UK
pp. 69-74

TLM+ modeling of embedded HW/SW systems (PDF)

Wolfgang Ecker , Infineon Technologies AG, 85579 Neubiberg, Germany
Volkan Esen , Infineon Technologies AG, Germany
Robert Schwencker , Infineon Technologies AG, Germany
Thomas Steininger , Infineon Technologies AG, Germany
Michael Velten , Infineon Technologies AG, TU München, Germany
pp. 75-80

Scenario extraction for a refined timing-analysis of automotive network topologies (Abstract)

Matthias Traub , Daimler AG, Research and Advanced Engineering, D-71059 Sindelfingen, Germany
Thilo Streichert , Daimler AG, Research and Advanced Engineering, D-71059 Sindelfingen, Germany
Oleg Krasovytskyy , Daimler AG, Research and Advanced Engineering, D-71059 Sindelfingen, Germany
Jurgen Becker , Karlsruhe Institute of Technology, Institute for Information Processing Technology (ITIV), Germany
pp. 81-86

Graphical Model Debugger Framework for embedded systems (PDF)

Kebin Zeng , Mads Clausen Institute, University of Southern Denmark, Alsion2, 6400 Soenderborg, Denmark
Yu Guo , Mads Clausen Institute, University of Southern Denmark, Alsion2, 6400 Soenderborg, Denmark
Christo K. Angelov , Mads Clausen Institute, University of Southern Denmark, Alsion2, 6400 Soenderborg, Denmark
pp. 87-92

IP routing processing with graphic processors (PDF)

Shuai Mu , Tsinghua University, China
Xinya Zhang , Fudan University, China
Nairen Zhang , University of Wisconsin-Madison, USA
Jiaxin Lu , University of Wisconsin-Madison, USA
Yangdong Steve Deng , Tsinghua University, China
Shu Zhang , NVidia Corporation, USA
pp. 93-98

An efficient distributed memory interface for many-core platform with 3D stacked DRAM (PDF)

Igor Loi , DEIS, University of Bologna, Italy
Luca Benini , DEIS, University of Bologna, Italy
pp. 99-104

Efficient OpenMP data mapping for multicore platforms with vertically stacked memory (Abstract)

Andrea Marongiu , DEIS - University of Bologna, Viale Risorgimento, 2 - 40136 - Italy
Martino Ruggiero , DEIS - University of Bologna, Viale Risorgimento, 2 - 40136 - Italy
Luca Benini , DEIS - University of Bologna, Viale Risorgimento, 2 - 40136 - Italy
pp. 105-110

Energy-efficient variable-flow liquid cooling in 3D stacked architectures (PDF)

Ayse K. Coskun , Electrical and Computer Engineering Department, Boston University, USA
David Atienza , Embedded Systems Laboratory (ESL), Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Tajana Simunic Rosing , Computer Science and Engineering Dept. (CSE), University of California San Diego, USA
Thomas Brunschwiler , IBM Research GmbH, Zurich Research Laboratory, Switzerland
Bruno Michel , IBM Research GmbH, Zurich Research Laboratory, Switzerland
pp. 111-116

Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers (PDF)

Jieyi Long , Dept. of EECS, Northwestern Univ., Evaston, IL 60208, USA
Seda Ogrenci Memik , Dept. of EECS, Northwestern Univ., Evaston, IL 60208, USA
Matthew Grayson , Dept. of EECS, Northwestern Univ., Evaston, IL 60208, USA
pp. 117-122

Are we there yet? Has IP block assembly become as easy as LEGO? (PDF)

Bryon Moyer , TechFocus Media, USA
Joachim Kunkel , Synopsys, USA
John Cornish , ARM, UK
Chris Rowen , Tensilica, USA
Eshel Haritan , CoWare, USA
Yankin Tanurhan , Virage Logic, USA
pp. 123

Temperature-aware dynamic resource provisioning in a power-optimized datacenter (PDF)

Ehsan Pakbaznia , University of Southern California, Department of Electrical Engineering-Systems, Los Angeles, U.S.A.
Mohammad Ghasemazar , University of Southern California, Department of Electrical Engineering-Systems, Los Angeles, U.S.A.
Massoud Pedram , University of Southern California, Department of Electrical Engineering-Systems, Los Angeles, U.S.A.
pp. 124-129

From transistors to MEMS: Throughput-aware power gating in CMOS circuits (PDF)

Michael B. Henry , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, USA
Leyla Nazhandali , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, USA
pp. 130-135

Energy- and endurance-aware design of phase change memory caches (PDF)

Yongsoo Joo , Department of Computer Science and Engineering, Pennsylvania State University, University Park, 16802, USA
Dimin Niu , Department of Computer Science and Engineering, Pennsylvania State University, University Park, 16802, USA
Xiangyu Dong , Department of Computer Science and Engineering, Pennsylvania State University, University Park, 16802, USA
Guangyu Sun , Department of Computer Science and Engineering, Pennsylvania State University, University Park, 16802, USA
Naehyuck Chang , Department of Electrical Engineering and Computer Science, Seoul National University, Korea
Yuan Xie , Department of Computer Science and Engineering, Pennsylvania State University, University Park, 16802, USA
pp. 136-141

Evaluation and design exploration of solar harvested-energy prediction algorithm (Abstract)

Mustafa Imran Ali , School of Electronics and Computer Science, University of Southampton, UK
Bashir M. Al-Hashimi , School of Electronics and Computer Science, University of Southampton, UK
Joaquin Recas , DACYA, Complutense University, Madrid, Spain
David Atienza , Embedded Systems Laboratory, Ecole Polytechnique Fédérale de Lausanne, Switzerland
pp. 142-147

A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) (PDF)

Yiran Chen , Seagate Technology, Bloomington, MN, USA
Hai Li , ECE Department, PolyTech Institute of NYU, Brooklyn, NY, USA
Xiaobin Wang , Seagate Technology, Bloomington, MN, USA
Wenzhong Zhu , Seagate Technology, Bloomington, MN, USA
Wei Xu , ECSE Department, Rensselaer Polytechnic Institute, Troy, New York, USA
Tong Zhang , ECSE Department, Rensselaer Polytechnic Institute, Troy, New York, USA
pp. 148-153

Pseudo-CMOS: A novel design style for flexible electronics (PDF)

Tsung-Ching Huang , Dept. of Electrical and Computer Engineering, University of California at Santa Barbara, 93106-9560, USA
Kenjiro Fukuda , Quantum-Phase Electronics Center, School of Engineering, The University of Tokyo, 113-8656, Japan
Chun-Ming Lo , Dept. of Electrical and Computer Engineering, University of California at Santa Barbara, 93106-9560, USA
Yung-Hui Yeh , Flexible Electronics Technology Division, EOL/ITRI, Chutung, Hsinchu 31040, Taiwan-R.O.C.
Tsuyoshi Sekitani , Quantum-Phase Electronics Center, School of Engineering, The University of Tokyo, 113-8656, Japan
Takao Someya , Quantum-Phase Electronics Center, School of Engineering, The University of Tokyo, 113-8656, Japan
Kwang-Ting Cheng , Dept. of Electrical and Computer Engineering, University of California at Santa Barbara, 93106-9560, USA
pp. 154-159

Spinto: High-performance energy minimization in spin glasses (Abstract)

Hector J. Garcia , The University of Michigan, 2260 Hayward Street, Ann Arbor, 48109-2121, USA
Igor L. Markov , The University of Michigan, 2260 Hayward Street, Ann Arbor, 48109-2121, USA
pp. 160-165

TSV redundancy: Architecture and design issues in 3D IC (PDF)

Ang-Chih Hsieh , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
TingTing Hwang , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
Ming-Tung Chang , Global Unichip Corporation, Hsinchu, Taiwan 300
Min-Hsiu Tsai , Global Unichip Corporation, Hsinchu, Taiwan 300
Chih-Mou Tseng , Global Unichip Corporation, Hsinchu, Taiwan 300
Hung-Chun Li , Global Unichip Corporation, Hsinchu, Taiwan 300
pp. 166-171

A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching (PDF)

Aditi Rathi , The Department of Computer Science and Engineering, The Pennsylvania State University, University Park, 16802, USA
Michael DeBole , The Department of Computer Science and Engineering, The Pennsylvania State University, University Park, 16802, USA
Weina Ge , The Department of Computer Science and Engineering, The Pennsylvania State University, University Park, 16802, USA
Robert T. Collins , The Department of Computer Science and Engineering, The Pennsylvania State University, University Park, 16802, USA
N. Vijaykrishnan , The Department of Computer Science and Engineering, The Pennsylvania State University, University Park, 16802, USA
pp. 172-177

Parallel subdivision surface rendering and animation on the Cell BE processor (PDF)

R. Grottesi , DM-DEIS, University of Bologna, Italy
S. Morigi , DM-DEIS, University of Bologna, Italy
M. Ruggiero , DM-DEIS, University of Bologna, Italy
L. Benini , DM-DEIS, University of Bologna, Italy
pp. 178-183

Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem (PDF)

Camille Jalier , CEA, LETI, MINATEC, F38054 Grenoble, France
Didier Lattard , CEA, LETI, MINATEC, F38054 Grenoble, France
Ahmed Amine Jerraya , CEA, LETI, MINATEC, F38054 Grenoble, France
Gilles Sassatelli , University of Montpellier II, LIRMM, UMR 5506, France
Pascal Benoit , University of Montpellier II, LIRMM, UMR 5506, France
Lionel Torres , University of Montpellier II, LIRMM, UMR 5506, France
pp. 184-189

Recursion-driven parallel code generation for multi-core platforms (PDF)

Rebecca L. Collins , Department of Computer Science, Columbia University, New York, 10027, USA
Bharadwaj Vellore , Department of Computer Science, Columbia University, New York, 10027, USA
Luca P. Carloni , Department of Computer Science, Columbia University, New York, 10027, USA
pp. 190-195

An industrial design space exploration framework for supporting run-time resource management on multi-core systems (PDF)

G. Mariani , ALaRI - University of Lugano, Switzerland
P. Avasare , IMEC, Belgium
G. Vanmeerbeeck , IMEC, Belgium
C. Ykman-Couvreur , IMEC, Belgium
G. Palermo , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
C. Silvano , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
V. Zaccaria , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
pp. 196-201

Stretching the limits of FPGA SerDes for enhanced ATE performance (PDF)

A.M. Majid , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
D.C. Keezer , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
pp. 202-207

Multi-temperature testing for core-based system-on-chip (PDF)

Zhiyuan He , Department of Computer and Information Science, Linköping University, SE-58183, Sweden
Zebo Peng , Department of Computer and Information Science, Linköping University, SE-58183, Sweden
Petru Eles , Department of Computer and Information Science, Linköping University, SE-58183, Sweden
pp. 208-213

Memory testing with a RISC microcontroller (PDF)

Ad van de Goor , ComTex, Gouda, The Netherlands
Georgi Gaydadjiev , Computer Engineering, Delft University of Technology, The Netherlands
Said Hamdioui , Computer Engineering, Delft University of Technology, The Netherlands
pp. 214-219

Constant-time admission control for Deadline Monotonic tasks (Abstract)

Alejandro Masrur , Institute for Real-Time Computer Systems, TU Munich, Germany
Samarjit Chakraborty , Institute for Real-Time Computer Systems, TU Munich, Germany
Georg Farber , Institute for Real-Time Computer Systems, TU Munich, Germany
pp. 220-225

Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks (PDF)

Jonas Rox , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, D-38106 / Germany
Rolf Ernst , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, D-38106 / Germany
pp. 226-231

Transition-aware real-time task scheduling for reconfigurable embedded systems (PDF)

Hessam Kooti , Computer Sciences Department, University of California, Irvine, USA
Elaheh Bozorgzadeh , Computer Sciences Department, University of California, Irvine, USA
Shenghui Liao , Computer Sciences Department, University of California, Irvine, USA
Lichun Bao , Computer Sciences Department, University of California, Irvine, USA
pp. 232-237

IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults (PDF)

Songjun Pan , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Yu Hu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
pp. 238-243

Aging-resilient design of pipelined architectures using novel detection and correction circuits (PDF)

Hamed Dadgour , Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA
Kaustav Banerjee , Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA
pp. 244-249

An integrated framework for joint design space exploration of microarchitecture and circuits (PDF)

Omid Azizi , Department of Electrical Engineering, Stanford University, USA
Aqeel Mahesri , NVIDIA Corporation, USA
John P. Stevenson , Department of Electrical Engineering, Stanford University, USA
Sanjay J. Patel , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Mark Horowitz , Department of Electrical Engineering, Stanford University, USA
pp. 250-255

Challenges in the design of automotive software (Abstract)

Simon Furst , BMW Group, 80788 Munich, Germany
pp. 256-258

AUTOSAR and the automotive tool chain (PDF)

Stefan Voget , Continental Engineering Services GmbH, Regensburg, Germany
pp. 259-262

High-fidelity markovian power model for protocols (PDF)

Jing Cao , School of Computer Science and Engineering, The University of New South Wales, Australia
Albert Nymeyer , School of Computer Science and Engineering, The University of New South Wales, Australia
pp. 267-270

Energy-performance design space exploration in SMT architectures exploiting selective load value predictions (PDF)

A. Gellert , ¿Lucian Blaga¿ University of Sibiu - Computer Science and Engineering Department, Romanian
G. Palermo , Politecnico di Milano - Dipartimento di Elettronica e Informazione, Italy
V. Zaccaria , Politecnico di Milano - Dipartimento di Elettronica e Informazione, Italy
A. Florea , ¿Lucian Blaga¿ University of Sibiu - Computer Science and Engineering Department, Romanian
L. Vintan , ¿Lucian Blaga¿ University of Sibiu - Computer Science and Engineering Department, Romanian
C. Silvano , Politecnico di Milano - Dipartimento di Elettronica e Informazione, Italy
pp. 271-274

Error resilience of intra-die and inter-die communication with 3D spidergon STNoC (PDF)

Vladimir Pasca , TIMA Laboratories, Grenoble, France
Lorena Anghel , TIMA Laboratories, Grenoble, France
Claudia Rusu , TIMA Laboratories, Grenoble, France
Riccardo Locatelli , ST Microelectronics, Grenoble, France
Marcello Coppola , ST Microelectronics, Grenoble, France
pp. 275-278

Towards a chip level reliability simulator for copper/low-k backend processes (PDF)

Muhammad Bashir , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
Linda Milor , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
pp. 279-282

NBTI modeling in the framework of temperature variation (PDF)

Seyab , Delft University of Technology, Computer Engineering Laboratory, Mekelweg 4, 2628 CD,The Netherlands
Said Hamdioui , Delft University of Technology, Computer Engineering Laboratory, Mekelweg 4, 2628 CD,The Netherlands
pp. 283-286

RunAssert: A non-intrusive run-time assertion for parallel programs debugging (PDF)

Chi-Neng Wen , Computer Science and Information Engineering, National Chung Cheng University, ChiaYi, Taiwan
Shu-Hsuan Chou , Computer Science and Information Engineering, National Chung Cheng University, ChiaYi, Taiwan
Tien-Fu Chen , Computer Science and Information Engineering, National Chung Cheng University, ChiaYi, Taiwan
Tay-Jyi Lin , SoC Technology Center, Industrial Technology Research Institute, HsinChu, Taiwan
pp. 287-290

An RDL-configurable 3D memory tier to replace on-chip SRAM (PDF)

Marco Facchini , IMEC - Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001 Heverlee, Belgium
Pol Marchal , IMEC - Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001 Heverlee, Belgium
Francky Catthoor , IMEC - Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001 Heverlee, Belgium
Wim Dehaene , ESAT-MICAS Katholieke University Leuven, Kasteelpark Aremberg 10, B-3001 Heverlee, Belgium
pp. 291-294

GentleCool: Cooling aware proactive workload scheduling in multi-machine systems (PDF)

Raid Ayoub , Department of Computer Science and Engineering, University of California, San Diego, USA
Shervin Sharifi , Department of Computer Science and Engineering, University of California, San Diego, USA
Tajana Simunic Rosing , Department of Computer Science and Engineering, University of California, San Diego, USA
pp. 295-298

Timing modeling for digital sub-threshold circuits (Abstract)

Niklas Lotze , University of Freiburg - IMTEK, Department of Microsystems Engineering, Laboratory for Microelectronics, Germany
Jacob Goppert , University of Freiburg - IMTEK, Department of Microsystems Engineering, Laboratory for Microelectronics, Germany
Yiannos Manoli , University of Freiburg - IMTEK, Department of Microsystems Engineering, Laboratory for Microelectronics, Germany
pp. 299-302

Power consumption of logic circuits in ambipolar carbon nanotube technology (PDF)

M. Haykel Ben Jamaa , Swiss Federal Institute of Technology, Lausanne, Switzerland
Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Giovanni De Micheli , Swiss Federal Institute of Technology, Lausanne, Switzerland
pp. 303-306

Reversible logic synthesis through ant colony optimization (PDF)

Min Li , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
Yexin Zheng , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
Michael S. Hsiao , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
Chao Huang , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
pp. 307-310

Low-power FinFET circuit synthesis using surface orientation optimization (PDF)

Prateek Mishra , Dept. of Electrical Engineering, Princeton University, NJ 08544, USA
Niraj K. Jha , Dept. of Electrical Engineering, Princeton University, NJ 08544, USA
pp. 311-314

Implementing digital logic with sinusoidal supplies (PDF)

Kalyana C. Bollapalli , Department of ECE, Texas A&M University, College Station 77843, USA
Sunil P. Khatri , Department of ECE, Texas A&M University, College Station 77843, USA
Laszlo B. Kish , Department of ECE, Texas A&M University, College Station 77843, USA
pp. 315-318

A reconfigurable multiprocessor architecture for a reliable face recognition implementation (PDF)

Antonino Tumeo , Politecnico di Milano - DEI, Milan, Italy
Francesco Regazzoni , Crypto Group, Universite Catholique de Louvain, Louvain-la-Neuve, Belgium
Gianluca Palermo , Politecnico di Milano - DEI, Milan, Italy
Fabrizio Ferrandi , Politecnico di Milano - DEI, Milan, Italy
Donatella Sciuto , Politecnico di Milano - DEI, Milan, Italy
pp. 319-322

A systematic approach to the test of combined HW/SW systems (Abstract)

Alexander Krupp , Paderborn University / C-LAB, Germany
Wolfgang Muller , Paderborn University / C-LAB, Germany
pp. 323-326

A new approach for adaptive failure diagnostics based on emulation test (Abstract)

S. Ostendorff , Integrated Hard- and Software Systems Group, Ilmenau University of Technology, POB 10 05 65, 98684 Ilmenau, Germany
H.-D. Wuttke , Integrated Hard- and Software Systems Group, Ilmenau University of Technology, POB 10 05 65, 98684 Ilmenau, Germany
J. Sachsse , Integrated Hard- and Software Systems Group, Ilmenau University of Technology, POB 10 05 65, 98684 Ilmenau, Germany
S. Kohler , Boundary Scan Division, GÖPEL electronic GmbH, Göschwitzer Str. 58/60, 07745 Jena, Germany
pp. 327-330

Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems (PDF)

Karthik Lakshmanan , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA-15213, USA
Gaurav Bhatia , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA-15213, USA
Raj Rajkumar , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA-15213, USA
pp. 331-334

Scalable stochastic processors (PDF)

Sriram Narayanan , Department of Electrical and Computer Engineering, UIUC, 1308 West Main St., Urbana, IL 61801, USA
John Sartori , Department of Electrical and Computer Engineering, UIUC, 1308 West Main St., Urbana, IL 61801, USA
Rakesh Kumar , Department of Electrical and Computer Engineering, UIUC, 1308 West Main St., Urbana, IL 61801, USA
Douglas L. Jones , Department of Electrical and Computer Engineering, UIUC, 1308 West Main St., Urbana, IL 61801, USA
pp. 335-338

AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics (PDF)

Bahman Kheradmand-Boroujeni , Integrated and Wireless Systems, CSEM, Neuchâtel, Switzerland
Christian Piguet , Integrated and Wireless Systems, CSEM, Neuchâtel, Switzerland
Yusuf Leblebici , Microelectronic Systems Laboratory, EPFL, Lausanne, Switzerland
pp. 339-344

On the efficacy of write-assist techniques in low voltage nanoscale SRAMs (PDF)

Vikas Chandra , ARM R&D, San Jose, CA, USA
Cezary Pietrzyk , ARM R&D, San Jose, CA, USA
Robert Aitken , ARM R&D, San Jose, CA, USA
pp. 345-350

Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times (PDF)

Hwisung Jung , Department of EE-Systems, University of Southern California, Los Angeles, USA
Massoud Pedram , Department of EE-Systems, University of Southern California, Los Angeles, USA
pp. 351-356

Run-time spatial resource management for real-time applications on heterogeneous MPSoCs (Abstract)

Timon D. ter Braak , Department of Electrical Engineering, Mathematics and Computer Science, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands
Philip K.F. Holzenspies , Department of Electrical Engineering, Mathematics and Computer Science, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands
Jan Kuper , Department of Electrical Engineering, Mathematics and Computer Science, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands
Johann L. Hurink , Department of Electrical Engineering, Mathematics and Computer Science, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands
Gerard J.M. Smit , Department of Electrical Engineering, Mathematics and Computer Science, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands
pp. 357-362

Rapid runtime estimation methods for pipelined MPSoCs (PDF)

Haris Javaid , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Andhi Janapsatya , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Mohammad Shihabul Haque , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Sri Parameswaran , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
pp. 363-368

Automatic workload generation for system-level exploration based on modified GCC compiler (Abstract)

Jari Kreku , VTT Technical Research Center of Finland, Kaitoväylä 1, FI-90570 Oulu, Finland
Kari Tiensyrja , VTT Technical Research Center of Finland, Kaitoväylä 1, FI-90570 Oulu, Finland
Geert Vanmeerbeeck , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
pp. 369-374

A rapid prototyping system for error-resilient multi-processor systems-on-chip (Abstract)

Matthias May , Microelectronic Systems Design, Research Group, University of Kaiserslautern, 67663, Germany
Norbert Wehn , Microelectronic Systems Design, Research Group, University of Kaiserslautern, 67663, Germany
Abdelmajid Bouajila , Institute for Integrated Systems, Technische Universität München, Arcisstr 21, 80290, Germany
Johannes Zeppenfeld , Institute for Integrated Systems, Technische Universität München, Arcisstr 21, 80290, Germany
Walter Stechele , Institute for Integrated Systems, Technische Universität München, Arcisstr 21, 80290, Germany
Andreas Herkersdorf , Institute for Integrated Systems, Technische Universität München, Arcisstr 21, 80290, Germany
Daniel Ziener , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, 91058, Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, 91058, Germany
pp. 375-380

Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip (PDF)

Jih-Sheng Shen , Department of CSIE, National Chung Cheng University, Chiayi, Taiwan, ROC
Chun-Hsian Huang , Department of CSIE, National Chung Cheng University, Chiayi, Taiwan, ROC
Pao-Ann Hsiung , Department of CSIE, National Chung Cheng University, Chiayi, Taiwan, ROC
pp. 381-386

Application-specific memory performance of a heterogeneous reconfigurable architecture (Abstract)

Sean Whitty , Institute of Computer and Network Engineering, Technische Universität Braunschweig, 38106, Germany
Henning Sahlbach , Institute of Computer and Network Engineering, Technische Universität Braunschweig, 38106, Germany
Brady Hurlburt , Institute of Computer and Network Engineering, Technische Universität Braunschweig, 38106, Germany
Rolf Ernst , Institute of Computer and Network Engineering, Technische Universität Braunschweig, 38106, Germany
Wolfram Putzke-Roming , Deutsche Thomson OHG, 30625 Hannover, Germany
pp. 387-392

A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation (PDF)

A. Akin , Faculty of Engineering and Natural Sciences, Sabanci University, 34956 Tuzla, Istanbul, Turkey
G. Sayilar , Faculty of Engineering and Natural Sciences, Sabanci University, 34956 Tuzla, Istanbul, Turkey
I. Hamzaoglu , Faculty of Engineering and Natural Sciences, Sabanci University, 34956 Tuzla, Istanbul, Turkey
pp. 393-398

Ultra-high throughput string matching for Deep Packet Inspection (PDF)

Alan Kennedy , School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
Xiaojun Wang , School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
Zhen Liu , School of Electronic Engineering, Dublin City University, Dublin 9, Ireland
Bin Liu , Department of Computer Science and Technology, Tsinghua University, Beijing, China
pp. 399-404

A HMMER hardware accelerator using divergences (PDF)

Juan Fernando Eusse Giraldo , Department of Electrical Engineering, University of Brasilia, DF, Brazil
Nahri Moreano , School of Computing, University of Mato Grosso do Sul, Campo Grande/MS, Brazil
Ricardo Pezzuol Jacobi , Department of Computer Science, University of Brasilia, DF, Brazil
Alba Cristina Magalhaes Alves de Melo , Department of Computer Science, University of Brasilia, DF, Brazil
pp. 405-410

Proactive NBTI mitigation for busy functional units in out-of-order microprocessors (PDF)

Lin Li , Dept of ECE, University of Pittsburgh, USA
Youtao Zhang , Dept of CS, University of Pittsburgh, USA
Jun Yang , Dept of ECE, University of Pittsburgh, USA
Jianhua Zhao , Dept of CS, Nanjing University, China
pp. 411-416

Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability (PDF)

Shrikanth Ganapathy , Department d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Spain
Ramon Canal , Department d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Spain
Antonio Gonzalez , Department d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Spain
Antonio Rubio , Department d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Spain
pp. 417-422

Analytical model for TDDB-based performance degradation in combinational logic (PDF)

Mihir Choudhury , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Vikas Chandra , ARM R&D, San Jose, USA
Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Robert Aitken , ARM R&D, San Jose, USA
pp. 423-428

Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs (PDF)

B. Alorda , Electronic Systems Group, Physics Dept., Illes Balears University, Palma de Mallorca, Spain
G. Torrens , Electronic Systems Group, Physics Dept., Illes Balears University, Palma de Mallorca, Spain
S. Bota , Electronic Systems Group, Physics Dept., Illes Balears University, Palma de Mallorca, Spain
J. Segura , Electronic Systems Group, Physics Dept., Illes Balears University, Palma de Mallorca, Spain
pp. 429-434

Test front loading in early stages of automotive software development based on AUTOSAR (PDF)

Alexander Michailidis , Group Research & Advanced Engineering, Daimler AG, Sindelfingen, Germany
Uwe Spieth , Group Research & Advanced Engineering, Daimler AG, Sindelfingen, Germany
Thomas Ringler , Group Research & Advanced Engineering, Daimler AG, Sindelfingen, Germany
Bernd Hedenetz , Group Research & Advanced Engineering, Daimler AG, Sindelfingen, Germany
Stefan Kowalewski , Computer Science 11, RWTH Aachen University, Germany
pp. 435-440

A proposal for real-time interfaces in SPEEDS (PDF)

Purandar Bhaduri , Indian Institute of Technology Guwahati, India
Ingo Stierand , University of Oldenburg, Germany
pp. 441-446

Scenario-based analysis and synthesis of real-time systems using uppaal (PDF)

Kim G. Larsen , Center for Embedded Software Systems (CISS), Aalborg University, DK-9220, Denmark
Shuhao Li , Center for Embedded Software Systems (CISS), Aalborg University, DK-9220, Denmark
Brian Nielsen , Center for Embedded Software Systems (CISS), Aalborg University, DK-9220, Denmark
Saulius Pusinskas , Center for Embedded Software Systems (CISS), Aalborg University, DK-9220, Denmark
pp. 447-452

Variation-aware interconnect extraction using statistical moment preserving model order reduction (PDF)

Tarek El-Moselhy , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139 USA
Luca Daniel , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, 02139 USA
pp. 453-458

Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate (PDF)

Navin Srivastava , Mentor Graphics, Wilsonville, OR, USA
Roberto Suaya , Mentor Graphics, Grenoble, France
Kaustav Banerjee , University of California, Santa Barbara, USA
pp. 459-464

HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling (Abstract)

Jorge Fernandez Villena , INESC ID / IST - TU Lisbon. Rua Alves Redol 9, 1000-029, Portugal
Luis Miguel Silveira , INESC ID / IST - TU Lisbon. Rua Alves Redol 9, 1000-029, Portugal
pp. 465-470

On passivity of the super node algorithm for EM modeling of interconnect systems (PDF)

Maria V. Ugryumova , Department of Mathematics and Computer Science, Eindhoven University of Technology, The Netherlands
Wil H.A. Schilders , Eindhoven University of Technology and NXP Semiconductors, The Netherlands
pp. 471-476

The road to energy-efficient systems: From hardware-driven to software-defined (PDF)

Gerhard Fettweis , Vodafone Chair Mobile Communications Systems, TU Dresden, Germany
pp. 477

Vacuity analysis for property qualification by mutation of checkers (PDF)

Luigi Di Guglielmo , Dipartimento di Informatica - Università di Verona, Strada le Grazie 15, 37134, Italy
Franco Fummi , Dipartimento di Informatica - Università di Verona, Strada le Grazie 15, 37134, Italy
Graziano Pravadelli , Dipartimento di Informatica - Università di Verona, Strada le Grazie 15, 37134, Italy
pp. 478-483

An abstraction-guided simulation approach using Markov models for microprocessor verification (PDF)

Tao Zhang , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Tao Lv , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
pp. 484-489

Efficient decision ordering techniques for SAT-based test generation (PDF)

Mingsong Chen , Department of Computer and Information Science and Engineering, University of Florida, Gainesville, 32611, USA
Xiaoke Qin , Department of Computer and Information Science and Engineering, University of Florida, Gainesville, 32611, USA
Prabhat Mishra , Department of Computer and Information Science and Engineering, University of Florida, Gainesville, 32611, USA
pp. 490-495

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy (PDF)

Mohammad Shihabul Haque , University of New South Wales, Sydney, Australia
Jorgen Peddersen , University of New South Wales, Sydney, Australia
Andhi Janapsatya , University of New South Wales, Sydney, Australia
Sri Parameswaran , University of New South Wales, Sydney, Australia
pp. 496-501

FlashPower: A detailed power model for NAND flash memory (PDF)

Vidyabhushan Mohan , Department of Computer Science, University of Virginia, Charlottesville, 22904, USA
Sudhanva Gurumurthi , Department of Computer Science, University of Virginia, Charlottesville, 22904, USA
Mircea R. Stan , Department of Electrical and Computer Engg, University of Virginia, Charlottesville, 22904, USA
pp. 502-507

A power optimization method for CMOS Op-Amps using sub-space based geometric programming (PDF)

Wei Gao , Computer Science & Engineering Department, York University, Toronto, Canada
Richard Hornsey , Computer Science & Engineering Department, York University, Toronto, Canada
pp. 508-513

Power gating design for standard-cell-like structured ASICs (PDF)

Sin-Yu Chen , Computer Science and Engineering line, Yuan Ze University, Chung-Li, Taiwan
Rung-Bin Lin , Computer Science and Engineering line, Yuan Ze University, Chung-Li, Taiwan
Hui-Hsiang Tung , Computer Science and Engineering line, Yuan Ze University, Chung-Li, Taiwan
Kuen-Wey Lin , Computer Science and Engineering line, Yuan Ze University, Chung-Li, Taiwan
pp. 514-519

Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement (PDF)

Meng Tie , Micro Processor Research and Development Center, Peking University, Beijing, China
Haiying Dong , Micro Processor Research and Development Center, Peking University, Beijing, China
Tong Wang , Micro Processor Research and Development Center, Peking University, Beijing, China
Xu Cheng , Micro Processor Research and Development Center, Peking University, Beijing, China
pp. 520-525

An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability (PDF)

L. Fanucci , Dept. of Information Engineering, University of Pisa, Italy
G. Pasetti , Dept. of Information Engineering, University of Pisa, Italy
P. D'Abramo , Austriamicrosystems AG, Navacchio (Pisa), Italy
R. Serventi , Austriamicrosystems AG, Navacchio (Pisa), Italy
F. Tinfena , Austriamicrosystems AG, Navacchio (Pisa), Italy
P. Chassard , Valeo Engine and Electrical Systems, Creteil Cedex, France
L. Labiste , Valeo Engine and Electrical Systems, Creteil Cedex, France
P. Tisserand , Valeo Engine and Electrical Systems, Creteil Cedex, France
pp. 526-531

Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation (Abstract)

Matthias Muller , Wilhelm-Schickard-Institute for Computer Science, Department of Computer Engineering, University of Tübingen, Sand 13, 72076, Germany
Axel Braun , Wilhelm-Schickard-Institute for Computer Science, Department of Computer Engineering, University of Tübingen, Sand 13, 72076, Germany
Joachim Gerlach , Wilhelm-Schickard-Institute for Computer Science, Department of Computer Engineering, University of Tübingen, Sand 13, 72076, Germany
Wolfgang Rosenstiel , Wilhelm-Schickard-Institute for Computer Science, Department of Computer Engineering, University of Tübingen, Sand 13, 72076, Germany
Dennis Nienhuser , Intelligent Systems and Production Engineering, FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany
J. Marius Zollner , Intelligent Systems and Production Engineering, FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany
Oliver Bringmann , Intelligent Systems and Production Engineering, FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany
pp. 532-537

Simulation-based verification of the MOST NetInterface specification revision 3.0 (PDF)

Andreas Braun , FZI Forschungszentrum Informatik, Systementwurf in der Mikroelektronik, Haid-und-Neu-Str. 10-14, D-76131 Karlsruhe, Germany
Oliver Bringmann , FZI Forschungszentrum Informatik, Systementwurf in der Mikroelektronik, Haid-und-Neu-Str. 10-14, D-76131 Karlsruhe, Germany
Djones Lettnin , Universität Tübingen, Wilhelm Schickard-Institut für Informatik, Sand 13, D-72076, Germany
Wolfgang Rosenstiel , Universität Tübingen, Wilhelm Schickard-Institut für Informatik, Sand 13, D-72076, Germany
pp. 538-543

Holistic simulation of FlexRay networks by using run-time model switching (PDF)

Michael Karner , Institute for Technical Informatics, Graz University of Technology, Austria
Eric Armengaud , Virtual Vehicle Competence Center, Austria
Christian Steger , Institute for Technical Informatics, Graz University of Technology, Austria
Reinhold Weiss , Institute for Technical Informatics, Graz University of Technology, Austria
pp. 544-549

Computing robustness of FlexRay schedules to uncertainties in design parameters (PDF)

Arkadeb Ghosal , General Motors Research, USA
Haibo Zeng , General Motors Research, USA
Marco Di Natale , Scuola Superiore SantAnna, Italy
Yakov Ben-Haim , Technion - Israel Institute of Technology, Israel
pp. 550-555

Adapting to adaptive testing (PDF)

Erik Jan Marinissen , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium
Adit Singh , Auburn University, Electrical & Comp. Eng., AL 36849, United States of America
Dan Glotter , OptimalTest, 18 Einstein Street, Nes Ziona, Israel 74140
Marco Esposito , OptimalTest, 18 Einstein Street, Nes Ziona, Israel 74140
John M. Carulli , Texas Instruments, 13121 TI Blvd., MS366, Dallas, 75243, United States of America
Amit Nahar , Texas Instruments, 13121 TI Blvd., MS366, Dallas, 75243, United States of America
Kenneth M. Butler , Texas Instruments, 13121 TI Blvd., MS366, Dallas, 75243, United States of America
Davide Appello , ST Microelectronics srl, Via C. Olivetti, 2, 20041 Agrate Brianza, Italy
Chris Portelli , ST Microelectronics, 190 Av. Célestin Coq, 13106, ROUSSET cedex, France
pp. 556-561

Using filesystem virtualization to avoid metadata bottlenecks (PDF)

Ernest Artiaga , Barcelona Supercomputing Center (BSC-CNS), Jordi Girona 31, E-08034 Spain
Toni Cortes , Barcelona Supercomputing Center (BSC-CNS), and Dept. of Computer Architecture, Technical University of Catalonia (UPC), Jordi Girona 1-3, E-08034 Spain
pp. 562-567

An accurate system architecture refinement methodology with mixed abstraction-level virtual platform (PDF)

Zhe-Mao Hsu , SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan 31040, ROC
Jen-Chieh Yeh , SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan 31040, ROC
I-Yao Chuang , SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan 31040, ROC
pp. 568-573

Non-intrusive virtualization management using libvirt (Abstract)

Matthias Bolte , Paderborn Center for Parallel Computing PC2, University of Paderborn, Fürstenallee 11, 33102, Germany
Michael Sievers , Paderborn Center for Parallel Computing PC2, University of Paderborn, Fürstenallee 11, 33102, Germany
Georg Birkenheuer , Paderborn Center for Parallel Computing PC2, University of Paderborn, Fürstenallee 11, 33102, Germany
Oliver Niehorster , Paderborn Center for Parallel Computing PC2, University of Paderborn, Fürstenallee 11, 33102, Germany
Andre Brinkmann , Paderborn Center for Parallel Computing PC2, University of Paderborn, Fürstenallee 11, 33102, Germany
pp. 574-579

Process variation and temperature-aware reliability management (PDF)

Cheng Zhuo , EECS Department, University of Michigan, Ann Arbor, 48109, USA
Dennis Sylvester , EECS Department, University of Michigan, Ann Arbor, 48109, USA
David Blaauw , EECS Department, University of Michigan, Ann Arbor, 48109, USA
pp. 580-585

Optimized self-tuning for circuit aging (Abstract)

Evelyn Mintarno , Stanford University, CA, USA
Joelle Skaf , Stanford University, CA, USA
Rui Zheng , Arizona State University, USA
Jyothi Velamala , Arizona State University, USA
Yu Cao , Arizona State University, USA
Stephen Boyd , Stanford University, CA, USA
Robert W. Dutton , Stanford University, CA, USA
Subhasish Mitra , Stanford University, CA, USA
pp. 586-591

Investigating the impact of NBTI on different power saving cache strategies (PDF)

A. Ricketts , Department of Computer Science and Engineering, The Pennsylvania State University, USA
J. Singh , Department of Computer Science, University of Bristol, UK
K. Ramakrishnan , Department of Computer Science and Engineering, The Pennsylvania State University, USA
N. Vijaykrishnan , Department of Computer Science and Engineering, The Pennsylvania State University, USA
D. K. Pradhan , Department of Computer Science, University of Bristol, UK
pp. 592-597

Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph (PDF)

Huan Wang , National ASIC System Engineering Technology Research Center, Southeast University, Nanjing 210096, China
Yang Zhang , National ASIC System Engineering Technology Research Center, Southeast University, Nanjing 210096, China
Chen Mei , National ASIC System Engineering Technology Research Center, Southeast University, Nanjing 210096, China
Ming Ling , National ASIC System Engineering Technology Research Center, Southeast University, Nanjing 210096, China
pp. 598-601

Enhanced Q-learning algorithm for dynamic power management with performance constraint (PDF)

Wei Liu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, 13902, USA
Ying Tan , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, 13902, USA
Qinru Qiu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, 13902, USA
pp. 602-605

Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations (PDF)

Aline Mello , Université Pierre et Marie Curie, 4, Place Jussieu - Paris - France
Isaac Maia , Université Pierre et Marie Curie, 4, Place Jussieu - Paris - France
Alain Greiner , Université Pierre et Marie Curie, 4, Place Jussieu - Paris - France
Francois Pecheux , Université Pierre et Marie Curie, 4, Place Jussieu - Paris - France
pp. 606-609

High-speed clock recovery for low-cost FPGAs (Abstract)

Istvan Haller , Computer Science Department, Technical University of Cluj-Napoca, Romania
Zoltan Francisc Baruch , Computer Science Department, Technical University of Cluj-Napoca, Romania
pp. 610-613

Demonstration of an in-band reconfiguration data distribution and network node reconfiguration (Abstract)

Uwe Pross , Core Mountains GmbH, Chemnitz, Germany
Sebastian Goller , Core Mountains GmbH, Chemnitz, Germany
Erik Markert , Chair Circuit and System Design, Chemnitz University of Technology, Germany
Michael Juttner , Chair Circuit and System Design, Chemnitz University of Technology, Germany
Jan Langer , Chair Circuit and System Design, Chemnitz University of Technology, Germany
Ulrich Heinkel , Chair Circuit and System Design, Chemnitz University of Technology, Germany
Joachim Knablein , Alcatel-Lucent, Nuremberg, Germany
Axel Schneider , Alcatel-Lucent, Nuremberg, Germany
pp. 614-617

Programmable aging sensor for automotive safety-critical applications (PDF)

J. C. Vazquez , Instituto Nacional de Astrofísica, Optica y Electrónica, (INAOE), México
V. Champac , Instituto Nacional de Astrofísica, Optica y Electrónica, (INAOE), México
I. C. Teixeira , INESC-ID, Lisboa, Portugal
M. B. Santos , INESC-ID, Lisboa, Portugal
J. P. Teixeira , INESC-ID, Lisboa, Portugal
pp. 618-621

Passive reduced order modeling of multiport interconnects via semidefinite programming (PDF)

Zohaib Mahmood , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology. Cambridge, 02139, USA
Brad Bond , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology. Cambridge, 02139, USA
Tarek Moselhy , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology. Cambridge, 02139, USA
Alexandre Megretski , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology. Cambridge, 02139, USA
Luca Daniel , Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology. Cambridge, 02139, USA
pp. 622-625

GoldMine: Automatic assertion generation using data mining and static analysis (PDF)

Shobha Vasudevan , Electrical and Computer Engineering Department, University of Illinois at Urbana Champaign, USA
David Sheridan , Electrical and Computer Engineering Department, University of Illinois at Urbana Champaign, USA
Sanjay Patel , Electrical and Computer Engineering Department, University of Illinois at Urbana Champaign, USA
David Tcheng , Electrical and Computer Engineering Department, University of Illinois at Urbana Champaign, USA
Bill Tuohy , Electrical and Computer Engineering Department, University of Illinois at Urbana Champaign, USA
Daniel Johnson , Electrical and Computer Engineering Department, University of Illinois at Urbana Champaign, USA
pp. 626-629

Assertion-based verification of RTOS properties (PDF)

Marcio F. S. Oliveira , C-Lab, University of Paderborn, Germany
Henning Zabel , C-Lab, University of Paderborn, Germany
Wolfgang Mueller , C-Lab, University of Paderborn, Germany
pp. 630-633

Post-placement temperature reduction techniques (PDF)

Wei Liu , Technical University of Denmark, Kgs.Lyngby, Denmark
Alberto Nannarelli , Technical University of Denmark, Kgs.Lyngby, Denmark
Andrea Calimera , Politecnico di Torino, Italy
Enrico Macii , Politecnico di Torino, Italy
Massimo Poncino , Politecnico di Torino, Italy
pp. 634-637

Clock gating approaches by IOEX graphs and cluster efficiency plots (PDF)

Jithendra Srinivas , CSE, Penn State University, USA
Jairam S , CSE, Penn State University, USA
pp. 638-641

Timing modeling and analysis for AUTOSAR-based software development - a case study (PDF)

Kay Klobedanz , University of Paderborn/C-LAB, Faculty of Electrical Engineering, Computer Science and Mathematics, 33102 Paderborn, Germany
Christoph Kuznik , University of Paderborn/C-LAB, Faculty of Electrical Engineering, Computer Science and Mathematics, 33102 Paderborn, Germany
Andreas Thuy , University of Paderborn/C-LAB, Faculty of Electrical Engineering, Computer Science and Mathematics, 33102 Paderborn, Germany
Wolfgang Mueller , University of Paderborn/C-LAB, Faculty of Electrical Engineering, Computer Science and Mathematics, 33102 Paderborn, Germany
pp. 642-645

Design of a real-time optimized emulation method (PDF)

Timo Kerstan , University of Paderborn, Fuerstenalle 11, 33102, Germany
Markus Oertel , OFFIS Institute for Information Technology, Escherweg 2, 26121 Oldenburg, Germany
pp. 646-649

Capturing intrinsic parameter fluctuations using the PSP compact model (PDF)

B. Cheng , Dept. of Electronics & Electrical Engineering, University of Glasgow, U.K.
D. Dideban , Dept. of Electronics & Electrical Engineering, University of Glasgow, U.K.
N. Moezi , Dept. of Electronics & Electrical Engineering, University of Glasgow, U.K.
C. Millar , Dept. of Electronics & Electrical Engineering, University of Glasgow, U.K.
G. Roy , Dept. of Electronics & Electrical Engineering, University of Glasgow, U.K.
X. Wang , Dept. of Electronics & Electrical Engineering, University of Glasgow, U.K.
S. Roy , Dept. of Electronics & Electrical Engineering, University of Glasgow, U.K.
A. Asenov , Dept. of Electronics & Electrical Engineering, University of Glasgow, U.K.
pp. 650-653

Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective (PDF)

Pavel Ghosh , Computer Science and Engineering Program, School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe, USA, 85287
Arunabha Sen , Computer Science and Engineering Program, School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe, USA, 85287
pp. 654-657

Security aspects in 6lowPan networks (PDF)

Ron Barker , Vodafone Group R&D, USA
pp. 660

Monolithically stackable hybrid FPGA (PDF)

Dmitri Strukov , ECE Department, UC Santa Barbara, CA, USA
Alan Mishchenko , EECS Department, UC Berkeley, CA, USA
pp. 661-666

Spintronic memristor devices and application (PDF)

Xiaobin Wang , Seagate Technology, 7801 Computer Avenue South, Bloomington, MN 55435, USA
Yiran Chen , Seagate Technology, 7801 Computer Avenue South, Bloomington, MN 55435, USA
pp. 667-672

Compact model of memristors and its application in computing systems (PDF)

Hai Li , Department of Electrical and Computer Engineering, Polytechnic Institute of New York University, 6 MetroTech Center, Brooklyn, USA
Miao Hu , Department of Electrical and Computer Engineering, Polytechnic Institute of New York University, 6 MetroTech Center, Brooklyn, USA
pp. 673-678

Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs (PDF)

Daniele Ludovicix , ENDIF, University of Ferrara, 44100, Italy
Alessandro Stranoy , DEIS, University of Bologna, 40136, Italy
Georgi N. Gaydadjievx , ENDIF, University of Ferrara, 44100, Italy
Luca Beniniyy , Computer Engineering Lab., Delft University of Technology, The Netherlands
Davide Bertozziy , DEIS, University of Bologna, 40136, Italy
pp. 679-684

A methodology for the characterization of process variation in NoC links (Abstract)

Carles Hernandez , Universidad Politécnica de Valencia, Grupo de Architecturas Paralelas, Departamento de Informática de Sistemas, Camino de Vera s/n 46022, España
Federico Silla , Universidad Politécnica de Valencia, Grupo de Architecturas Paralelas, Departamento de Informática de Sistemas, Camino de Vera s/n 46022, España
Jose Duato , Universidad Politécnica de Valencia, Grupo de Architecturas Paralelas, Departamento de Informática de Sistemas, Camino de Vera s/n 46022, España
pp. 685-690

PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks (PDF)

Johnnie Chan , Department of Electrical Engineering, Columbia University, New York, USA
Gilbert Hendry , Department of Electrical Engineering, Columbia University, New York, USA
Aleksandr Biberman , Department of Electrical Engineering, Columbia University, New York, USA
Keren Bergman , Department of Electrical Engineering, Columbia University, New York, USA
Luca P. Carloni , Department of Computer Science, Columbia University, New York, USA
pp. 691-696

An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation (PDF)

Arnd Geis , IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Pierluigi Nuzzoz , EECS Department, U.C. Berkeley, Cory Hall, CA 94720, USA
Julien Ryckaert , IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Yves Rolainy , Vrije Universiteit Brussel, Pleinlaan 2, 1000, Belgium
Gerd Vandersteeny , Vrije Universiteit Brussel, Pleinlaan 2, 1000, Belgium
Jan Craninckx , IMEC, Kapeldreef 75, 3001 Leuven, Belgium
pp. 697-701

A compact digital amplitude modulator in 90nm CMOS (PDF)

V. Chironi , Dept.of Innovation Engineering, University of Salento, Lecce, Italy
B. Debaillie , IMEC, Leuven, Belgium
A. Baschirotto , Dept.of Innovation Engineering, University of Salento, Lecce, Italy
J. Craninckx , IMEC, Leuven, Belgium
M. Ingels , IMEC, Leuven, Belgium
pp. 702-705

A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR (PDF)

Thomas Froehlich , Austriamicrosystems Switzerland AG, Rapperswil Switzerland
Vivek Sharma , Austriamicrosystems Switzerland AG, Rapperswil Switzerland
Markus Bingesser , Austriamicrosystems Switzerland AG, Rapperswil Switzerland
pp. 706-710

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits (PDF)

Armin Tajalli , Microelectronic Systems Lab. (LSM), Ecole Polytechnique Fédéral de Lausanne (EPFL), CH-1015, Switzerland
Yusuf Leblebici , Microelectronic Systems Lab. (LSM), Ecole Polytechnique Fédéral de Lausanne (EPFL), CH-1015, Switzerland
pp. 711-716

Clock skew scheduling for soft-error-tolerant sequential circuits (PDF)

Kai-Chiang Wu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
Diana Marculescu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
pp. 717-722

HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data paths (Abstract)

Mario Scholzel , Department of Computer Science, Brandenburg University of Technology, Cottbus, Germany
pp. 723-728

Scalable codeword generation for coupled buses (PDF)

Kedar Karmarkar , Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, 62901-6603, USA
Spyros Tragoudas , Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, 62901-6603, USA
pp. 729-734

An adaptive code rate EDAC scheme for random access memory (PDF)

Ching-Yi Chen , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
pp. 735-740

Worst case delay analysis for memory interference in multicore systems (PDF)

Rodolfo Pellizzoni , University of Illinois at Urbana-Champaign, USA
Andreas Schranzhofer , Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
Jian-Jia Chen , Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
Marco Caccamo , University of Illinois at Urbana-Champaign, USA
Lothar Thiele , Swiss Federal Institute of Technology (ETH), Zurich, Switzerland
pp. 741-746

Throughput modeling to evaluate process merging transformations in polyhedral process networks (PDF)

Sjoerd Meijer , Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands
Hristo Nikolov , Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands
Todor Stefanov , Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Netherlands
pp. 747-752

Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms (PDF)

Jeronimo Castrillon , Institute for Integrated Signal Processing Systems (ISS), RWTH Aachen University, Germany
Ricardo Velasquez , ALaRI Institute, Lugano, Switzerland
Anastasia Stulova , Institute for Integrated Signal Processing Systems (ISS), RWTH Aachen University, Germany
Weihua Sheng , Institute for Integrated Signal Processing Systems (ISS), RWTH Aachen University, Germany
Jianjiang Ceng , Institute for Integrated Signal Processing Systems (ISS), RWTH Aachen University, Germany
Rainer Leupers , Institute for Integrated Signal Processing Systems (ISS), RWTH Aachen University, Germany
Gerd Ascheid , Institute for Integrated Signal Processing Systems (ISS), RWTH Aachen University, Germany
Heinrich Meyr , Institute for Integrated Signal Processing Systems (ISS), RWTH Aachen University, Germany
pp. 753-758

Bounding the shared resource load for the performance analysis of multiprocessor systems (PDF)

Simon Schliecker , Institute of Computer and Network Engineering, Technische Universität Braunschweig, D-38106, Germany
Mircea Negrean , Institute of Computer and Network Engineering, Technische Universität Braunschweig, D-38106, Germany
Rolf Ernst , Institute of Computer and Network Engineering, Technische Universität Braunschweig, D-38106, Germany
pp. 759-764

An error-correcting unordered code and hardware support for robust asynchronous global communication (PDF)

Melinda Y. Agyekum , Department of Computer Science, Columbia University, New York, 10027, USA
Steven M. Nowick , Department of Computer Science, Columbia University, New York, 10027, USA
pp. 765-770

Large-scale Boolean matching (PDF)

Hadi Katebi , University of Michigan, 2260 Hayward St., Ann Arbor, 48109, USA
Igor L. Markov , University of Michigan, 2260 Hayward St., Ann Arbor, 48109, USA
pp. 771-776

KL-Cuts: A new approach for logic synthesis targeting multiple output blocks (Abstract)

Osvaldo Martinello , Institute of Informatics, Federal University of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil
Felipe S. Marques , Institute of Informatics, Federal University of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil
Renato P. Ribas , Institute of Informatics, Federal University of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil
Andre I. Reis , Institute of Informatics, Federal University of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil
pp. 777-782

RALF: Reliability Analysis for Logic Faults — An exact algorithm and its applications (PDF)

Samuel Luckenbill , Computer Science Department, University of California, Los Angeles, USA
Ju-Yueh Lee , Electrical Engineering Department, University of California, Los Angeles, USA
Yu Hu , Electrical Engineering Department, University of Alberta, Edmonton Canada
Rupak Majumdar , Computer Science Department, University of California, Los Angeles, USA
Lei He , Electrical Engineering Department, University of California, Los Angeles, USA
pp. 783-788

Panel 6.8: The challenges of heterogeneous multicore debug (PDF)

Grant Martin , Tensilica, Santa Clara, California, U.S.A.
Albrecht Mayer , Infineon, Munich, Germany
pp. 789

Low power design of the X-GOLD® SDR 20 baseband processor (Abstract)

Wolfgang Raab , Infineon Technologies AG, Germany
Jorg Berthold , Infineon Technologies AG, Germany
Ulrich Hachmann , Infineon Technologies AG, Germany
Dominik Langen , Infineon Technologies AG, Germany
Michael Schreiner , Infineon Technologies AG, Germany
Holger Eisenreich , TU Dresden, Germany
Jens-Uwe Schluessler , TU Dresden, Germany
Georg Ellguth , TU Dresden, Germany
pp. 792-793

Low power mobile internet devices using LTE technology (PDF)

Volker Aue , Blue Wonder Communications, Dresden, Germany
pp. 794

A black box method for stability analysis of arbitrary SRAM cell structures (PDF)

M. Wieckowski , Dept. Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
D. Sylvester , Dept. Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
D. Blaauw , Dept. Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
V. Chandra , ARM R&D, San Jose, CA, USA
S. Idgunji , ARM R&D, San Jose, CA, USA
C. Pietrzyk , ARM R&D, San Jose, CA, USA
R. Aitken , ARM R&D, San Jose, CA, USA
pp. 795-800

Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis (PDF)

Masood Qazi , Massachusetts Institute of Technology, Cambridge, USA
Mehul Tikekar , Massachusetts Institute of Technology, Cambridge, USA
Lara Dolecek , Massachusetts Institute of Technology, Cambridge, USA
Devavrat Shah , Massachusetts Institute of Technology, Cambridge, USA
Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge, USA
pp. 801-806

Practical Monte-Carlo based timing yield estimation of digital circuits (PDF)

Javid Jaffari , ECE Department, University of Waterloo, ON, Canada N2L 3G1
Mohab Anis , ECE Department, University of Waterloo, ON, Canada N2L 3G1
pp. 807-812

Statistical static timing analysis using Markov chain Monte Carlo (PDF)

Yashodhan Kanoria , Departments of Electrical Engineering, Stanford University, USA
Subhasish Mitra , Departments of Electrical Engineering, Stanford University, USA
Andrea Montanari , Departments of Electrical Engineering, Stanford University, USA
pp. 813-818

KAHRISMA: A Novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture (Abstract)

Ralf Koenig , Karlsruhe Institute of Technology, Germany
Lars Bauer , Karlsruhe Institute of Technology, Germany
Timo Stripf , Karlsruhe Institute of Technology, Germany
Muhammad Shafique , Karlsruhe Institute of Technology, Germany
Waheed Ahmed , Karlsruhe Institute of Technology, Germany
Juergen Becker , Karlsruhe Institute of Technology, Germany
Jorg Henkel , Karlsruhe Institute of Technology, Germany
pp. 819-824

A reconfigurable cache memory with heterogeneous banks (PDF)

Domingo Benitez , SIANI Institute & DIS dpt - Univ. of Las Palmas de G. C., 35017, Spain
Juan C. Moure , Computer Architecture & Operating Systems dpt., University Autónoma of Barcelona, 08193, Spain
Dolores Rexachs , Computer Architecture & Operating Systems dpt., University Autónoma of Barcelona, 08193, Spain
Emilio Luque , Computer Architecture & Operating Systems dpt., University Autónoma of Barcelona, 08193, Spain
pp. 825-830

Evaluation of runtime task mapping heuristics with rSesame - a case study (PDF)

Kamana Sigdel , Computer Engineering Laboratory, EEMCS, Delft University of Technology, The Netherlands
Mark Thompson , Computer Systems Architecture Group, University of Amsterdam, The Netherlands
Carlo Galuzzi , Computer Systems Architecture Group, University of Amsterdam, The Netherlands
Andy D. Pimentel , Computer Engineering Laboratory, EEMCS, Delft University of Technology, The Netherlands
Koen Bertels , Computer Engineering Laboratory, EEMCS, Delft University of Technology, The Netherlands
pp. 831-836

VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems (PDF)

Abelardo Jara-Berrocal , NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA
Ann Gordon-Ross , NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA
pp. 837-842

pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems (PDF)

Zhimin Chen , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 26061, USA
Patrick Schaumont , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 26061, USA
pp. 843-848

BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation (PDF)

Maxime Nassar , Département COMELEC, Institut TELECOM, TELECOM ParisTech, Bull, CNRS LTCI, FRANCE
Shivam Bhasin , Département COMELEC, Institut TELECOM, TELECOM ParisTech, Bull, CNRS LTCI, FRANCE
Jean-Luc Danger , Département COMELEC, Institut TELECOM, TELECOM ParisTech, Bull, CNRS LTCI, FRANCE
Guillaume Duc , Département COMELEC, Institut TELECOM, TELECOM ParisTech, Bull, CNRS LTCI, FRANCE
Sylvain Guilley , Département COMELEC, Institut TELECOM, TELECOM ParisTech, Bull, CNRS LTCI, FRANCE
pp. 849-854

Fault-based attack of RSA authentication (PDF)

Andrea Pellegrini , University of Michigan, USA
Valeria Bertacco , University of Michigan, USA
Todd Austin , University of Michigan, USA
pp. 855-860

Detecting/preventing information leakage on the memory bus due to malicious hardware (PDF)

Abhishek Das , Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL USA
Gokhan Memik , Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL USA
Joseph Zambreno , Electrical and Computer Engineering Department, Iowa State University, Ames, USA
Alok Choudhary , Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL USA
pp. 861-866

An embedded platform for privacy-friendly road charging applications (PDF)

Josep Balasch , K.U.Leuven ESAT/COSIC and IBBT, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Ingrid Verbauwhede , K.U.Leuven ESAT/COSIC and IBBT, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Bart Preneel , K.U.Leuven ESAT/COSIC and IBBT, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
pp. 867-872

Defect aware X-filling for low-power scan testing (PDF)

S. Balatsouka , Dept. of Computer Science, University of Ioannina, 45110, Greece
V. Tenentes , Dept. of Computer Science, University of Ioannina, 45110, Greece
X. Kavousianos , Dept. of Computer Science, University of Ioannina, 45110, Greece
K. Chakrabarty , Dept. of Electrical & Computer Engineering, Duke University, 27708 Durham, NC, USA
pp. 873-878

Parallel X-fault simulation with critical path tracing technique (PDF)

Raimund Ubar , Department of Computer Engineering, Tallinn University of Technology, Estonia
Sergei Devadze , Department of Computer Engineering, Tallinn University of Technology, Estonia
Jaan Raik , Department of Computer Engineering, Tallinn University of Technology, Estonia
Artur Jutman , Department of Computer Engineering, Tallinn University of Technology, Estonia
pp. 879-884

Diagnosis of multiple arbitrary faults with mask and reinforcement effect (PDF)

Jing Ye , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Yu Hu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
pp. 885-890

Skewed pipelining for parallel simulink simulations (PDF)

Arquimedes Canedo , IBM Research - Tokyo, Japan
Takeo Yoshizawa , IBM Research - Tokyo, Japan
Hideaki Komatsu , IBM Research - Tokyo, Japan
pp. 891-896

An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms (PDF)

Alessio Bonfietti , DEIS - Universitá di Bologna, Italy
Luca Benini , DEIS - Universitá di Bologna, Italy
Michele Lombardi , DEIS - Universitá di Bologna, Italy
Michela Milano , DEIS - Universitá di Bologna, Italy
pp. 897-902

A software update service with self-protection capabilities (PDF)

Moritz Neukirchner , Institut für Datentechnik und Kommunikationsnetze, Technische Universität Braunschweig, Germany
Steffen Stein , Institut für Datentechnik und Kommunikationsnetze, Technische Universität Braunschweig, Germany
Harald Schrom , Institut für Datentechnik und Kommunikationsnetze, Technische Universität Braunschweig, Germany
Rolf Ernst , Institut für Datentechnik und Kommunikationsnetze, Technische Universität Braunschweig, Germany
pp. 903-908

Bitstream processing for embedded systems using C++ metaprogramming (PDF)

Reimund Klemm , Vodafone Chair Mobile Communication Systems, Technische Universität Dresden, Germany
Gerhard Fettweis , Vodafone Chair Mobile Communication Systems, Technische Universität Dresden, Germany
pp. 909-913

Increasing PCM main memory lifetime (Abstract)

Alexandre P. Ferreira , Department of Computer Science, University of Pittsburgh, Pennsylvania USA
Miao Zhou , Department of Computer Science, University of Pittsburgh, Pennsylvania USA
Santiago Bock , Department of Computer Science, University of Pittsburgh, Pennsylvania USA
Bruce Childers , Department of Computer Science, University of Pittsburgh, Pennsylvania USA
Rami Melhem , Department of Computer Science, University of Pittsburgh, Pennsylvania USA
Daniel Mosse , Department of Computer Science, University of Pittsburgh, Pennsylvania USA
pp. 914-919

Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm (Abstract)

Andhi Janapsatya , School of Computer Science & Engineering, University of New South Wales, Sydney, 2052, Australia
Aleksandar Ignjatovic , NICTA, Sydney, NSW 2052, Australia
Jorgen Peddersen , School of Computer Science & Engineering, University of New South Wales, Sydney, 2052, Australia
Sri Parameswaran , NICTA, Sydney, NSW 2052, Australia
pp. 920-925

A memory- and time-efficient on-chip TCAM minimizer for IP lookup (PDF)

Heeyeol Yu , Computer Science & Engineering Department, University of California, Riverside, USA
pp. 926-931

PANEL SESSION - Who Is Closing the embedded software design gap? (PDF)

W. Ecker , Infineon, DE
Pierre Bricaud , Synopsys, FR
Rainer Doemer , UC Irvine, US
Yossi Veller , Mentor Graphics, US
Stefan Heinen , Infineon, DE
Jurgen Mossinger , Bosch, DE
Andreas von Schwerin , Siemens, DE
pp. 932

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs (PDF)

Binzhang Fu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Yinhe Han , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Huawei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 933-936

A High-Voltage Low-Power DC-DC buck regulator for automotive applications (PDF)

G. Pasetti , Dept. of Information Engineering, University of Pisa, Italy
L. Fanucci , Dept. of Information Engineering, University of Pisa, Italy
R. Serventi , Austriamicrosystems AG, Navacchio (PI), Italy
pp. 937-940

SimTag: Exploiting tag bits similarity to improve the reliability of the data caches (PDF)

Jesung Kim , Department of Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, South Korea
Soontae Kim , Department of Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, South Korea
Yebin Lee , Department of Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, South Korea
pp. 941-944

The split register file (PDF)

J. Abella , Intel Barcelona Research Center, Intel Labs Barcelona - UPC, Spain
J. Carretero , Intel Barcelona Research Center, Intel Labs Barcelona - UPC, Spain
P. Chaparro , Intel Barcelona Research Center, Intel Labs Barcelona - UPC, Spain
X. Vera , Intel Barcelona Research Center, Intel Labs Barcelona - UPC, Spain
pp. 945-948

Multithreaded code from synchronous programs: Extracting independent threads for OpenMP (PDF)

Daniel Baudisch , Department of Computer Science, University of Kaiserslautern, Germany
Jens Brandt , Department of Computer Science, University of Kaiserslautern, Germany
Klaus Schneider , Department of Computer Science, University of Kaiserslautern, Germany
pp. 949-952

RMOT: Recursion in model order for task execution time estimation in a software pipeline (Abstract)

Nabeel Iqbal , Karlsruhe Institute of Technology (KIT), Chair for Embedded Systems, Germany
M. Adnan Siddique , Karlsruhe Institute of Technology (KIT), Chair for Embedded Systems, Germany
Jorg Henkel , Karlsruhe Institute of Technology (KIT), Chair for Embedded Systems, Germany
pp. 953-956

Approximate logic synthesis for error tolerant applications (PDF)

Doochul Shin , Electrical Engineering Department, University of Southern California, Los Angeles, 90089, USA
Sandeep K. Gupta , Electrical Engineering Department, University of Southern California, Los Angeles, 90089, USA
pp. 957-960

Automatic microarchitectural pipelining (PDF)

Marc Galceran-Oms , Universitat Politècnica de Catalunya, Barcelona, Spain
Jordi Cortadella , Universitat Politècnica de Catalunya, Barcelona, Spain
Dmitry Bufistov , Universitat Politècnica de Catalunya, Barcelona, Spain
Mike Kishinevsky , Strategic CAD Lab, Intel Corporation., Hillsboro, OR USA
pp. 961-964

Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage (PDF)

Rahul Rithe , Massachusetts Institute of Technology, Cambridge, 02139, USA
Jie Gu , Texas Instruments, Dallas, 75243, USA
Alice Wang , Texas Instruments, Dallas, 75243, USA
Satyendra Datla , Texas Instruments, Dallas, 75243, USA
Gordon Gammie , Texas Instruments, Dallas, 75243, USA
Dennis Buss , Texas Instruments, Dallas, 75243, USA
Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge, 02139, USA
pp. 965-968

Dynamically reconfigurable register file for a softcore VLIW processor (PDF)

Stephan Wong , Computer Engineering Laboratory, Delft University of Technology, The Netherlands
Fakhar Anjam , Computer Engineering Laboratory, Delft University of Technology, The Netherlands
Faisal Nadeem , Computer Engineering Laboratory, Delft University of Technology, The Netherlands
pp. 969-972

FPGA-based adaptive computing for correlated multi-stream processing (PDF)

Ming Liu , II. Physics Institute, Justus-Liebig-University Giessen (JLU), Germany
Zhonghai Lu , Dept. of Electronic Systems, Royal Institute of Technology (KTH), Sweden
Wolfgang Kuehn , II. Physics Institute, Justus-Liebig-University Giessen (JLU), Germany
Axel Jantsch , Dept. of Electronic Systems, Royal Institute of Technology (KTH), Sweden
pp. 973-976

Far Correlation-based EMA with a precharacterized leakage model (PDF)

Olivier Meynard , Institut TELECOM, TELECOM ParisTech, CNRS LTCI, 46 rue Barrault 75 634, France
Sylvain Guilley , Institut TELECOM, TELECOM ParisTech, CNRS LTCI, 46 rue Barrault 75 634, France
Jean-Luc Danger , Institut TELECOM, TELECOM ParisTech, CNRS LTCI, 46 rue Barrault 75 634, France
Laurent Sauvage , Institut TELECOM, TELECOM ParisTech, CNRS LTCI, 46 rue Barrault 75 634, France
pp. 977-980

Improved countermeasure against Address-bit DPA for ECC scalar multiplication (PDF)

Masami Izumi , The University of Electro-Communications, 1-5-1, Chofugaoka, Chofu, Tokyo 182-8585, Japan
Jun Ikegami , The University of Electro-Communications, 1-5-1, Chofugaoka, Chofu, Tokyo 182-8585, Japan
Kazuo Sakiyama , The University of Electro-Communications, 1-5-1, Chofugaoka, Chofu, Tokyo 182-8585, Japan
Kazuo Ohta , The University of Electro-Communications, 1-5-1, Chofugaoka, Chofu, Tokyo 182-8585, Japan
pp. 981-984

Constrained Power Management: Application to a multimedia mobile platform (PDF)

Patrick Bellasi , Dipartimento di Elettronica e Informazione, Politecnico di Milano, P.zza Leonardo da Vinci, 32. 20133, Italy
Stefano Bosisio , Dipartimento di Elettronica e Informazione, Politecnico di Milano, P.zza Leonardo da Vinci, 32. 20133, Italy
Matteo Carnevali , Dipartimento di Elettronica e Informazione, Politecnico di Milano, P.zza Leonardo da Vinci, 32. 20133, Italy
William Fornaciari , Dipartimento di Elettronica e Informazione, Politecnico di Milano, P.zza Leonardo da Vinci, 32. 20133, Italy
David Siorpaes , Advanced System Technology, STMicroelectronics, Via C. Olivetti, 2. 20041 - Agrate Brianza, Italy
pp. 989-992

Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits (PDF)

Farhad Mehdipour , School of Information Science and Electrical Engineering, Department of Informatics, Kyushu University, Fukuoka, Japan
Hiroaki Honda , Institute of Systems, Information Technologies and Nanotechnologies, Fukuoka, Japan
Hiroshi Kataoka , School of Information Science and Electrical Engineering, Department of Informatics, Kyushu University, Fukuoka, Japan
Koji Inoue , School of Information Science and Electrical Engineering, Department of Informatics, Kyushu University, Fukuoka, Japan
Irina Kataeva , Department of Quantum Engineering, Nagoya University, Japan
Kazuaki Murakami , School of Information Science and Electrical Engineering, Department of Informatics, Kyushu University, Fukuoka, Japan
Hiroyuki Akaike , Department of Quantum Engineering, Nagoya University, Japan
Akira Fujimaki , Department of Quantum Engineering, Nagoya University, Japan
pp. 993-996

MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture (PDF)

Tamar Kranenburg , Delft University of Technology, EEMCS, Circuits and Systems group, Mekelweg 4, 2628 CD, The Netherlands
Rene van Leuken , Delft University of Technology, EEMCS, Circuits and Systems group, Mekelweg 4, 2628 CD, The Netherlands
pp. 997-1000

Automatic pipelining from transactional datapath specifications (PDF)

Eriko Nurvitadhi , Carnegie Mellon University, USA
James C. Hoe , Carnegie Mellon University, USA
Timothy Kam , Intel Corporation, USA
Shih-Lien L. Lu , Intel Corporation, USA
pp. 1001-1004

Increasing the power efficiency of PCs by improving the hardware/OS interaction (Abstract)

Chris Schlager , Operating System Research Center, AMD, USA
pp. 1005

Optimize your power and performance yields and regain those sleepless nights (PDF)

Krisztian Flautner , Vice President of Research & Development, ARM, USA
pp. 1006

Digital statistical analysis using VHDL (PDF)

Manfred Dietrich , Fraunhofer IIS/EAS Dresden, Germany
Uwe Eichler , Fraunhofer IIS/EAS Dresden, Germany
Joachim Haase , Fraunhofer IIS/EAS Dresden, Germany
pp. 1007-1010

A resilience roadmap (PDF)

Sani R. Nassif , Austin Research Laboratory, IBM Corporation, TX 78758, USA
Nikil Mehta , Department of Computer Science, California Institute of Technology, Pasadena, 91125, USA
Yu Cao , Department of Electrical Engineering, Arizona State University, Tempe, 85287, USA
pp. 1011-1016

Vision for cross-layer optimization to address the dual challenges of energy and reliability (Abstract)

Andre DeHon , Electrical and Systems Engineering, University of Pennsylvania, 200 S. 33rd St., Philadelphia, 19104, USA
Heather M. Quinn , Los Alamos National Laboratory, ISR-3 Space Data Systems, NM 87545, USA
Nicholas P. Carter , Intel Corporation, 2200 Mission College Blvd, RNB6-61, Santa Clara, California 95054, USA
pp. 1017-1022

Design techniques for cross-layer resilience (PDF)

Nicholas P. Carter , Intel Corporation, 2200 Mission College Blvd., RNB6-61, Santa Clara, California 95054, USA
Helia Naeimi , Intel Corporation, 2200 Mission College Blvd., RNB6-61, Santa Clara, California 95054, USA
Donald S. Gardner , Intel Corporation, 2200 Mission College Blvd., RNB6-61, Santa Clara, California 95054, USA
pp. 1023-1028

Cross-layer resilience challenges: Metrics and optimization (PDF)

Subhasish Mitra , Robust Systems Group, Department of EE and Department of CS, Stanford University, CA, USA
Kevin Brelsford , Robust Systems Group, Department of EE and Department of CS, Stanford University, CA, USA
Pia N. Sanda , IBM Corporation, Poughkeepsie, NY, USA
pp. 1029-1034

Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs (PDF)

Jun Zhu , Royal Institute of Technology, Stockholm, Sweden
Ingo Sander , Royal Institute of Technology, Stockholm, Sweden
Axel Jantsch , Royal Institute of Technology, Stockholm, Sweden
pp. 1035-1040

Automated bottleneck-driven design-space exploration of media processing systems (PDF)

Yang Yang , Department of Electrical Engineering, Eindhoven University of Technology, Netherlands
Marc Geilen , Department of Electrical Engineering, Eindhoven University of Technology, Netherlands
Twan Basten , Department of Electrical Engineering, Eindhoven University of Technology, Netherlands
Sander Stuijk , Department of Electrical Engineering, Eindhoven University of Technology, Netherlands
Henk Corporaal , Department of Electrical Engineering, Eindhoven University of Technology, Netherlands
pp. 1041-1046

Using Transaction Level Modeling techniques for wireless sensor network simulation (PDF)

Markus Damm , Institute of Computer Technology, Vienna University of Technology, Austria
Javier Moreno , Institute of Computer Technology, Vienna University of Technology, Austria
Jan Haase , Institute of Computer Technology, Vienna University of Technology, Austria
Christoph Grimm , Institute of Computer Technology, Vienna University of Technology, Austria
pp. 1047-1052

RTOS-aware refinement for TLM2.0-based HW/SW designs (PDF)

Markus Becker , C-LAB, University of Paderborn, Germany
Giuseppe Di Guglielmo , Dipartimento di Informatica, Università di Verona, Italy
Franco Fummi , Dipartimento di Informatica, Università di Verona, Italy
Wolfgang Mueller , C-LAB, University of Paderborn, Germany
Graziano Pravadelli , Dipartimento di Informatica, Università di Verona, Italy
Tao Xie , C-LAB, University of Paderborn, Germany
pp. 1053-1058

Power Variance Analysis breaks a masked ASIC implementation of AES (PDF)

Yang Li , The University of Electro-Communications, Tokyo, Japan
Kazuo Sakiyama , The University of Electro-Communications, Tokyo, Japan
Lejla Batina , Radboud University Nijmegen, The Netherlands
Daisuke Nakatsu , The University of Electro-Communications, Tokyo, Japan
Kazuo Ohta , The University of Electro-Communications, Tokyo, Japan
pp. 1059-1064

Novel Physical Unclonable Function with process and environmental variations (PDF)

Xiaoxiao Wang , ECE Dept, University of Connecticut, USA
Mohammad Tehranipoor , ECE Dept, University of Connecticut, USA
pp. 1065-1070

Ultra low-power 12-bit SAR ADC for RFID applications (PDF)

Daniela De Venuto , DEE Politecnico di Bari, Italy
Eduard Stikvoort , NXP Semiconductors, Eindhoven, The Netherlands
David Tio Castro , NXP Semiconductors, Leuven, Belgium
Youri Ponomarev , NXP Semiconductors, Leuven, Belgium
pp. 1071-1075

A portable multi-pitch e-drum based on printed flexible pressure sensors (PDF)

Chun-Ming Lo , Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, 93106-9560, USA
Tsung-Ching Huang , Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, 93106-9560, USA
Cheng-Yi Chiang , Flexible Electronics Technology Division, EOL-ITRI, Chutung, Hsinchu 31040, Taiwan-R.O.C.
Johnson Hou , Flexible Electronics Technology Division, EOL-ITRI, Chutung, Hsinchu 31040, Taiwan-R.O.C.
Kwang-Ting Cheng , Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, 93106-9560, USA
pp. 1082-1087

Computation of yield-optimized Pareto fronts for analog integrated circuit specifications (PDF)

Daniel Mueller-Gritschneder , Institute for Electronic Design Automation, Technische Universitaet Muenchen, Germany
Helmut Graeb , Institute for Electronic Design Automation, Technische Universitaet Muenchen, Germany
pp. 1088-1093

Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity (PDF)

Elie Maricau , ESAT-MICAS, KULeuven, Belgium
Georges Gielen , ESAT-MICAS, KULeuven, Belgium
pp. 1094-1099

A general mathematical model of probabilistic ripple-carry adders (PDF)

Mark S. K. Lau , School of Electrical and Electronic Engineering, Nanyang Technological University, 50, Singapore 639798
Keck-Voon Ling , School of Electrical and Electronic Engineering, Nanyang Technological University, 50, Singapore 639798
Yun-Chung Chu , School of Electrical and Electronic Engineering, Nanyang Technological University, 50, Singapore 639798
Arun Bhanu , School of Electrical and Electronic Engineering, Nanyang Technological University, 50, Singapore 639798
pp. 1100-1105

An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique (Abstract)

Bo Liu , ESAT-MICAS, Katholieke Universiteit Leuven, Belgium
Francisco V. Fernandez , IMSE, CSIC and University of Sevilla, Spain
Georges Gielen , ESAT-MICAS, Katholieke Universiteit Leuven, Belgium
pp. 1106-1111

Reuse-aware modulo scheduling for stream processors (PDF)

Li Wang , National Laboratory for Parallel and Distributed Processing, School of Computer, NUDT, China
Jingling Xue , Programming Languages & Compilers Group, School of Computer Science and Engineering, UNSW, Australia
Xuejun Yang , National Laboratory for Parallel and Distributed Processing, School of Computer, NUDT, China
pp. 1112-1117

Compilation of stream programs for multicore processors that incorporate scratchpad memories (PDF)

Weijia Che , Faculty of Computer Science and Engineering, Arizona State University, Tempe, 85287, USA
Amrit Panda , Faculty of Computer Science and Engineering, Arizona State University, Tempe, 85287, USA
Karam S. Chatha , Faculty of Computer Science and Engineering, Arizona State University, Tempe, 85287, USA
pp. 1118-1123

Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems (PDF)

Hideki Takase , Graduate School of Information Science, Nagoya University, C3-1 (631), Furo-cho, Chikusa-ku, 464-8603 Japan
Hiroyuki Tomiyama , Graduate School of Information Science, Nagoya University, C3-1 (631), Furo-cho, Chikusa-ku, 464-8603 Japan
Hiroaki Takada , Graduate School of Information Science, Nagoya University, C3-1 (631), Furo-cho, Chikusa-ku, 464-8603 Japan
pp. 1124-1129

A special-purpose compiler for look-up table and code generation for function evaluation (PDF)

Yuanrui Zhang , Department of Computer Science and Engineering, Pennsylvania State University, USA
Lanping Deng , School of Electrical, Computer and Engineering, Arizona State University, USA
Praveen Yedlapalli , Department of Computer Science and Engineering, Pennsylvania State University, USA
Sai Prashanth Muralidhara , Department of Computer Science and Engineering, Pennsylvania State University, USA
Hui Zhao , Department of Computer Science and Engineering, Pennsylvania State University, USA
Mahmut Kandemir , Department of Computer Science and Engineering, Pennsylvania State University, USA
Chaitali Chakrabarti , School of Electrical, Computer and Engineering, Arizona State University, USA
Nikos Pitsianis , Department of Electrical and Computer Engineering, Aristotle University, Greece
Xiaobai Sun , Department of Computer Science, Duke University, USA
pp. 1130-1135

General behavioral thermal modeling and characterization for multi-core microprocessor design (PDF)

Thom J. A. Eguia , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Sheldon X.-D. Tan , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Ruijing Shen , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Eduardo H. Pacheco , Intel Corporation, 2200 Mission College Blvd, Santa Clara, CA, 95052, USA
Murli Tirumala , Intel Corporation, 2200 Mission College Blvd, Santa Clara, CA, 95052, USA
pp. 1136-1141

On the construction of guaranteed passive macromodels for high-speed channels (PDF)

Alessandro Chinea , Department of Electronics, Politecnico di Torino, Italy
Stefano Grivet-Talocia , Department of Electronics, Politecnico di Torino, Italy
Dirk Deschrijver , Department of Information Technology, Ghent University-IBBT, Belgium
Tom Dhaene , Department of Information Technology, Ghent University-IBBT, Belgium
Luc Knockaert , Department of Information Technology, Ghent University-IBBT, Belgium
pp. 1142-1147

Extended Hamiltonian Pencil for passivity assessment and enforcement for S-parameter systems (PDF)

Zuochang Ye , Tsinghua University, China
L. Miguel Silveira , INESC-ID/IST - TU Lisbon, Portugal
Joel R. Phillips , Cadence Design Systems, USA
pp. 1148-1152

Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation (PDF)

Takayuki Watanabe , School of Administration and Informatics, University of Shizuoka, Japan
Hideki Asai , Dept. of System Engineering, Faculty of Engineering, Shizuoka University, Hamamatsu, Japan
pp. 1153-1158

Carbon nanotube circuits: Living with imperfections and variations (PDF)

Jie Zhang , Department of Electrical Engineering, Stanford University, CA, USA
Nishant Patil , Department of Electrical Engineering, Stanford University, CA, USA
Albert Lin , Department of Electrical Engineering, Stanford University, CA, USA
H. -S. Philip Wong , Department of Electrical Engineering, Stanford University, CA, USA
Subhasish Mitra , Department of Electrical Engineering, Stanford University, CA, USA
pp. 1159-1164

Properties of and improvements to time-domain dynamic thermal analysis algorithms (PDF)

Xi Chen , EECS Department, University of Michigan, Ann Arbor, USA
Robert P. Dick , EECS Department, University of Michigan, Ann Arbor, USA
Li Shang , ECEE Department, University of Colorado, Boulder, USA
pp. 1165-1170

Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation (PDF)

Meng-Huan Wu , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan
Wen-Chuan Lee , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan
Chen-Yu Chuang , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan
Ren-Song Tsay , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan
pp. 1177-1182

Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs (PDF)

Rauf Salimi Khaligh , Embedded Systems Engineering Group (ESE) - ITI, Universität Stuttgart, Pfaffenwaldring 47, D-70569, Germany
Martin Radetzki , Embedded Systems Engineering Group (ESE) - ITI, Universität Stuttgart, Pfaffenwaldring 47, D-70569, Germany
pp. 1183-1188

Efficient High-Level modeling in the networking domain (Abstract)

Christian Zebelein , University of Erlangen-Nuremberg, Germany
Joachim Falk , University of Erlangen-Nuremberg, Germany
Christian Haubelt , University of Erlangen-Nuremberg, Germany
Jurgen Teich , University of Erlangen-Nuremberg, Germany
Rainer Dorsch , IBM Research & Development GmbH, Germany
pp. 1189-1194

UML design for dynamically reconfigurable multiprocessor embedded systems (PDF)

Jorgiano Vidal , Lab-STICC - European University of Brittany - UBS - CNRS, UMR 3192, Centre de Recherche - BP 92116 - F-56321 Lorient Cedex - FRANCE
Florent de Lamotte , Lab-STICC - European University of Brittany - UBS - CNRS, UMR 3192, Centre de Recherche - BP 92116 - F-56321 Lorient Cedex - FRANCE
Guy Gogniat , Lab-STICC - European University of Brittany - UBS - CNRS, UMR 3192, Centre de Recherche - BP 92116 - F-56321 Lorient Cedex - FRANCE
Jean-Philippe Diguet , Lab-STICC - European University of Brittany - UBS - CNRS, UMR 3192, Centre de Recherche - BP 92116 - F-56321 Lorient Cedex - FRANCE
Philippe Soulard , SODIUS - 6 rue de Cornouaille - F-44300 NANTES - FRANCE
pp. 1195-1200

Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systems (PDF)

Fabian Mischkalla , University of Paderborn, C-LAB, Fuerstenallee 11, D-33102, Germany
Da He , University of Paderborn, C-LAB, Fuerstenallee 11, D-33102, Germany
Wolfgang Mueller , University of Paderborn, C-LAB, Fuerstenallee 11, D-33102, Germany
pp. 1201-1206

Formal semantics for PSL modeling layer and application to the verification of transactional models (PDF)

Luca Ferro , TIMA (CNRS-GrenobleINP-UJF), 46 Av. Félix Viallet - 38031 Grenoble cedex - France
Laurence Pierre , TIMA (CNRS-GrenobleINP-UJF), 46 Av. Félix Viallet - 38031 Grenoble cedex - France
pp. 1207-1212

COTS-based applications in space avionics (PDF)

Michel Pignol , CNES, Toulouse, France
pp. 1213-1219

Worst-case end-to-end delay analysis of an avionics AFDX network (PDF)

Henri Bauer , Airbus France - 316 Route de Bayonne 31300 Toulouse, France
Jean-Luc Scharbarg , Université de Toulouse - IRIT/ENSEEIHT/INPT - 2, rue Camichel 31000, France
Christian Fraboul , Université de Toulouse - IRIT/ENSEEIHT/INPT - 2, rue Camichel 31000, France
pp. 1220-1224

Integration, cooling and packaging issues for aerospace equipments (PDF)

C. Sarno , Packaging Department, TBU Navigation, Thales, Aerospace Division, Valence, France
C. Tantolin , Packaging Department, TBU Navigation, Thales, Aerospace Division, Valence, France
pp. 1225-1230

A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs (PDF)

L. Sterpone , Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
N. Battezzati , Politecnico di Torino, Dipartimento di Automatica e Informatica, Italy
pp. 1231-1236

Reducing the storage requirements of a test sequence by using a background vector (PDF)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
Sudhakar M. Reddy , Electrical & Computer Eng. Dept., University of Iowa, Iowa City, 52242, U.S.A.
pp. 1237-1242

BISD: Scan-based Built-In self-diagnosis (PDF)

Melanie Elm , Institute for Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, 70569, Germany
Hans-Joachim Wunderlich , Institute for Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, 70569, Germany
pp. 1243-1248

Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules (PDF)

Mohammad Mirza-Aghatabar , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, 90089-2562, USA
Melvin A. Breuer , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, 90089-2562, USA
Sandeep K. Gupta , Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, 90089-2562, USA
pp. 1249-1254

A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis (PDF)

Jason Cong , Department of Computer Science, University of California, Los Angeles, USA
Hui Huang , Department of Computer Science, University of California, Los Angeles, USA
Wei Jiang , Department of Computer Science, University of California, Los Angeles, USA
pp. 1255-1260

Behavioral level dual-vth design for reduced leakage power with thermal awareness (PDF)

Junbo Yu , Tsinghua National Laboratory for Information Science, and Technology, Dept. of Computer Science, Tsinghua University, Beijing, 10084, China
Qiang Zhou , Tsinghua National Laboratory for Information Science, and Technology, Dept. of Computer Science, Tsinghua University, Beijing, 10084, China
Gang Qu , Dept. of Electrical and Computer Engineering and Institute for Advanced Computer Studies, University of Maryland, College Park, USA
Jinian Bian , Tsinghua National Laboratory for Information Science, and Technology, Dept. of Computer Science, Tsinghua University, Beijing, 10084, China
pp. 1261-1266

Coordinated resource optimization in behavioral synthesis (PDF)

Jason Cong , Computer Science Department, University of California, Los Angeles, USA
Bin Liu , Computer Science Department, University of California, Los Angeles, USA
Junjuan Xu , Computer Science Department, University of California, Los Angeles, USA
pp. 1267-1272

A methodology for propagating design tolerances to shape tolerances for use in manufacturing (PDF)

Shayak Banerjee , The University of Texas at Austin, 78712, USA
Kanak B. Agarwal , IBM Austin Research Laboratory, TX 78758, USA
Chin-Ngai Sze , IBM Austin Research Laboratory, TX 78758, USA
Sani Nassif , IBM Austin Research Laboratory, TX 78758, USA
Michael Orshansky , The University of Texas at Austin, 78712, USA
pp. 1273-1278

Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance (PDF)

Xin Gao , Department of Electrical Engineering, University of Hawaii at Manoa, Honolulu, 96822, U.S.A.
Luca Macchiarulo , Department of Electrical Engineering, University of Hawaii at Manoa, Honolulu, 96822, U.S.A.
pp. 1279-1284

Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component Analysis (PDF)

Safar Hatami , University of Southern California, Department of Electrical Engineering, Los Angeles, USA
Massoud Pedram , University of Southern California, Department of Electrical Engineering, Los Angeles, USA
pp. 1285-1290

Exploiting local logic structures to optimize multi-core SoC floorplanning (PDF)

Cheng-Hong Li , Department of Computer Science - Columbia University in the City of New York, USA
Sampada Sonalkar , Department of Computer Science - Columbia University in the City of New York, USA
Luca P. Carloni , Department of Computer Science - Columbia University in the City of New York, USA
pp. 1291-1296

Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems (PDF)

Sven van Haastregt , LIACS, Leiden University, Niels Bohrweg 1, 2333 CA, The Netherlands
Eyal Halm , LIACS, Leiden University, Niels Bohrweg 1, 2333 CA, The Netherlands
Bart Kienhuis , LIACS, Leiden University, Niels Bohrweg 1, 2333 CA, The Netherlands
pp. 1297-1300

Differential Power Analysis enhancement with statistical preprocessing (Abstract)

Victor Lomne , LIRMM, UMR 5506, University Montpellier 2 - CNRS, 161, rue Ada, 34392, France
Amine Dehbaoui , LIRMM, UMR 5506, University Montpellier 2 - CNRS, 161, rue Ada, 34392, France
Philippe Maurine , LIRMM, UMR 5506, University Montpellier 2 - CNRS, 161, rue Ada, 34392, France
Lionel Torres , LIRMM, UMR 5506, University Montpellier 2 - CNRS, 161, rue Ada, 34392, France
Michel Robert , LIRMM, UMR 5506, University Montpellier 2 - CNRS, 161, rue Ada, 34392, France
pp. 1301-1304

Correlation controlled sampling for efficient variability analysis of analog circuits (PDF)

Javid Jaffari , ECE Department, University of Waterloo, ON, Canada N2L 3G1
Mohab Anis , ECE Department, University of Waterloo, ON, Canada N2L 3G1
pp. 1305-1308

Formal verification of analog circuits in the presence of noise and process variation (Abstract)

Rajeev Narayanan , Dept. of Electrical and Computer Engineering, Concordia University, Montreal, Quebec, Canada
Behzad Akbarpour , Dept. of Electrical and Computer Engineering, Concordia University, Montreal, Quebec, Canada
Mohamed H. Zaki , Dept. of Computer Science, University of British Columbia, Vancouver, Canada
Sofiene Tahar , Dept. of Electrical and Computer Engineering, Concordia University, Montreal, Quebec, Canada
Lawrence C. Paulson , Computer Laboratory, University of Cambridge, UK
pp. 1309-1312

Toward optimized code generation through model-based optimization (Abstract)

Asma Charfi , CEA LIST, Laboratory of model driven engineering for embedded systems, Point Courrier 94, F-91191, Gif sur Yvette, France
Chokri Mraidha , CEA LIST, Laboratory of model driven engineering for embedded systems, Point Courrier 94, F-91191, Gif sur Yvette, France
Sebastien Gerard , CEA LIST, Laboratory of model driven engineering for embedded systems, Point Courrier 94, F-91191, Gif sur Yvette, France
Francois Terrier , CEA LIST, Laboratory of model driven engineering for embedded systems, Point Courrier 94, F-91191, Gif sur Yvette, France
Pierre Boulet , Université Lille 1, Sciences et Technologies, cité scientifique, 59655, Villeneuve d'Ascq Cedex, France
pp. 1313-1316

Path-based scheduling in a hardware compiler (PDF)

Ruirui Gu , Department of Electrical and Computer Engineering, University of Maryland at College Park, USA
Alessandro Forin , Microsoft Research, Microsoft Corporation, Redmond, WA, USA
Neil Pittman , Microsoft Research, Microsoft Corporation, Redmond, WA, USA
pp. 1317-1320

Optimization of FIR filter to improve eye diagram for general transmission line systems (PDF)

Yung-Shou Cheng , National Taiwan University, Department of Electrical Engineering and Graduate Institute of Communication Engineering, Taipei, Taiwan, 10617, R.O.C.
Yen-Cheng Lai , National Taiwan University, Department of Electrical Engineering and Graduate Institute of Communication Engineering, Taipei, Taiwan, 10617, R.O.C.
Ruey-Beei Wu , National Taiwan University, Department of Electrical Engineering and Graduate Institute of Communication Engineering, Taipei, Taiwan, 10617, R.O.C.
pp. 1321-1324

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits (PDF)

Roshan Weerasekera , Centre for Microsystems Engineering, Faculty of Science & Technology, Lancaster University, LA1 4YR, UK
Matt Grange , Centre for Microsystems Engineering, Faculty of Science & Technology, Lancaster University, LA1 4YR, UK
Dinesh Pamunuwa , Centre for Microsystems Engineering, Faculty of Science & Technology, Lancaster University, LA1 4YR, UK
Hannu Tenhunen , Department of Electronics, Computer, and Software Systems, KTH School of Information and Communication Technologies, ELECTRUM 229, 164 40 Kista, Sweden
pp. 1325-1328

Interconnect delay and slew metrics using the beta distribution (PDF)

Jun-Kuei Zeng , National Taiwan University, Electrical Engineering Department, Taiwan
Chung-Ping Chen , National Taiwan University, Electrical Engineering Department, Taiwan
pp. 1329-1332

Accurate timed RTOS model for transaction level modeling (PDF)

Yonghyun Hwang , CECS, University of California, Irvine, 92617, USA
Gunar Schirner , Dept. of ECE, Northeastern University, Boston, MA, 02115, USA
Samar Abdi , Dept. of ECE, Concordia University, Montreal, Canada H3G 1M8
Daniel G. Gajski , CECS, University of California, Irvine, 92617, USA
pp. 1333-1336

A modeling method by eliminating execution traces for performance evaluation (PDF)

Kouichi Ono , IBM Research - Tokyo, 1623-14 Shimotsuruma, Yamato-shi, Kanagawa, 242-8502 Japan
Manabu Toyota , Component Technology Solution, IBM Japan, Ltd., 338 Enpukuji-cho, Nakagyou-ku, Kyoto, 604-8175 Japan
Ryo Kawahara , IBM Research - Tokyo, 1623-14 Shimotsuruma, Yamato-shi, Kanagawa, 242-8502 Japan
Yoshifumi Sakamoto , Component Technology Solution, IBM Japan, Ltd., 338 Enpukuji-cho, Nakagyou-ku, Kyoto, 604-8175 Japan
Takeo Nakada , IBM Research - Tokyo, 1623-14 Shimotsuruma, Yamato-shi, Kanagawa, 242-8502 Japan
Naoaki Fukuoka , Tokyo R&D Center, KYOCERA MITA Corp., 2-14-9 Tamagawadai, Setagaya-ku, 158-8610 Japan
pp. 1337-1340

Verifying UML/OCL models using Boolean satisfiability (PDF)

Mathias Soeken , Group for Computer Architecture, University of Bremen, 28359, Germany
Robert Wille , Group for Computer Architecture, University of Bremen, 28359, Germany
Mirco Kuhlmann , Database Systems Group, University of Bremen, 28359, Germany
Martin Gogolla , Database Systems Group, University of Bremen, 28359, Germany
Rolf Drechsler , Group for Computer Architecture, University of Bremen, 28359, Germany
pp. 1341-1344

SCOC3: a space computer on a chip (Abstract)

Franck Koebel , EADS Astrium Satellite, CoC Electronic France, Elancourt, France
Jean-Francois Coldefy , EADS Astrium Satellite, CoC Electronic France, Elancourt, France
pp. 1345-1348

High temperature polymer capacitors for aerospace applications (PDF)

Clinton K. Landrock , Department of Engineering Science, Simon Fraser University, Burnaby, Canada
Bozena Kaminska , Department of Engineering Science, Simon Fraser University, Burnaby, Canada
pp. 1349-1352

An on-chip clock generation scheme for faster-than-at-speed delay testing (PDF)

Songwei Pei , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
Huawei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
pp. 1353-1356

Construction of dual mode components for reconfiguration aware high-level synthesis (PDF)

George Economakos , National Technical University of Athens, School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory, Heroon Polytechniou 9, GR-15780 Zografou, Greece
Sotirios Xydis , National Technical University of Athens, School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory, Heroon Polytechniou 9, GR-15780 Zografou, Greece
Ioannis Koutras , National Technical University of Athens, School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory, Heroon Polytechniou 9, GR-15780 Zografou, Greece
Dimitrios Soudris , National Technical University of Athens, School of Electrical and Computer Engineering Microprocessors and Digital Systems Laboratory, Heroon Polytechniou 9, GR-15780 Zografou, Greece
pp. 1357-1360

Optimizing Data-Flow Graphs with min/max, adding and relational operations (Abstract)

J. Perez , GIM (www.teisa.unican.es/gim), TEISA, University of Cantabria, Santander, Spain
P. Sanchez , GIM (www.teisa.unican.es/gim), TEISA, University of Cantabria, Santander, Spain
V. Fernandez , GIM (www.teisa.unican.es/gim), TEISA, University of Cantabria, Santander, Spain
pp. 1361-1364

Optimization of the bias current network for accurate on-chip thermal monitoring (PDF)

Jieyi Long , Dept. of EECS, Northwestern Univ., Evaston, IL 60208, USA
Seda Ogrenci Memik , Dept. of EECS, Northwestern Univ., Evaston, IL 60208, USA
pp. 1365-1368

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal (PDF)

Fan Yang , Department of CST, Tsinghua University, China
Yici Cai , Department of CST, Tsinghua University, China
Qiang Zhou , Department of CST, Tsinghua University, China
Jiang Hu , Department of ECE, Texas A&M University, USA
pp. 1369-1372

NIM- a noise index model to estimate delay discrepancies between silicon and simulation (PDF)

Elif Alpaslan , Division of Engineering, Brown University, Providence, USA
Jennifer Dworak , Division of Engineering, Brown University, Providence, USA
Bram Kruseman , NXP Semiconductors High Tech Campus, Eindhoven, The Netherlands
Ananta K. Majhi , NXP Semiconductors High Tech Campus, Eindhoven, The Netherlands
Wilmar M. Heuvelman , NXP Semiconductors High Tech Campus, Eindhoven, The Netherlands
Paul van de Wiel , NXP Semiconductors High Tech Campus, Eindhoven, The Netherlands
pp. 1373-1376

Panel: First commandment at least, do nothing well! (PDF)

Marco Casale-Rossi , Synopsys, Inc., Sunnyvale, CA, USA
Giovanni De Micheli , Ecole Polytechnique Federale de Lausanne, Switzerland
Antun Domic , Synopsys, Inc., Sunnyvale, CA, USA
Enrico Macii , Politecnico di Torino, Italy
Piero Perlo , Centro Ricerche FIAT, Torino, Italy
Andreas Wild , ENIAC, Bruxelles, Belgium
Roberto Zafalon , STMicroelectronics, Agrate Brianza, Italy
pp. 1377

SigNet: Network-on-chip filtering for coarse vector directories (PDF)

Natalie Enright Jerger , Department of Electrical and Computer Engineering, University of Toronto, ON, Canada
pp. 1378-1383

Feedback control for providing QoS in NoC based multicores (PDF)

Akbar Sharifi , Computer Science and Engineering Department, Pennsylvania State University, USA
Hui Zhao , Computer Science and Engineering Department, Pennsylvania State University, USA
Mahmut Kandemir , Computer Science and Engineering Department, Pennsylvania State University, USA
pp. 1384-1389

Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network (PDF)

Minje Jun , School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
Sungroh Yoon , School of Electrical Engineering, Korea University, Seoul, Korea
Eui-Young Chung , School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea
pp. 1390-1395

Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector (PDF)

Teo Cupaiuolo , Advanced System Technologies - STMicrolectronics, Agrate Brianza, Italy
Massimiliano Siti , Advanced System Technologies - STMicrolectronics, Agrate Brianza, Italy
Alessandro Tomasoni , Politecnico di Milano, Milan, Italy
pp. 1396-1401

A low cost multi-standard near-optimal soft-output sphere decoder: Algorithm and architecture (Abstract)

Ozgun Paker , ST Ericsson, High Tech Campus 41, Eindhoven, The Netherlands
Sebastian Eckert , Blue Wonder Communications GmbH, Am Waldschlösschen 1,D-01099, Dresden, Germany
Andreas Bury , Blue Wonder Communications GmbH, Am Waldschlösschen 1,D-01099, Dresden, Germany
pp. 1402-1407

Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study (PDF)

Rudy Beraha , Qualcomm Corp. Research and Development, San Diego, California 92121, USA
Isask'har Walter , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa 32000, Israel
Israel Cidon , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa 32000, Israel
Avinoam Kolodny , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa 32000, Israel
pp. 1408-1413

Domain specific architecture for next generation wireless communication (PDF)

Botao Zhang , Institute of Microelectrics & Microprocessor, School of Computer Science, National University of Defense Technology, Changsha HN, China
Hengzhu Liu , Institute of Microelectrics & Microprocessor, School of Computer Science, National University of Defense Technology, Changsha HN, China
Heng Zhao , Institute of Microelectrics & Microprocessor, School of Computer Science, National University of Defense Technology, Changsha HN, China
Fangzheng Mo , Institute of Microelectrics & Microprocessor, School of Computer Science, National University of Defense Technology, Changsha HN, China
Ting Chen , Institute of Microelectrics & Microprocessor, School of Computer Science, National University of Defense Technology, Changsha HN, China
pp. 1414-1419

A 150Mbit/s 3GPP LTE Turbo code decoder (PDF)

Matthias May , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663, Germany
Thomas Ilnseher , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663, Germany
Norbert Wehn , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663, Germany
Wolfgang Raab , Infineon Technologies AG, 81726 München, Germany
pp. 1420-1425

High-quality pattern selection for screening small-delay defects considering process variations and crosstalk (PDF)

Ke Peng , ECE Department, University of Connecticut, USA
Mahmut Yilmaz , AMD, Sunnyvale, CA, USA
Mohammad Tehranipoor , ECE Department, University of Connecticut, USA
Krishnendu Chakrabarty , ECE Department, Duke University, USA
pp. 1426-1431

Layout-aware pseudo-functional testing for critical paths considering power supply noise effects (PDF)

Xiao Liu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Yubin Zhang , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Feng Yuan , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
pp. 1432-1437

On reset based functional broadside tests (PDF)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
Sudhakar M. Reddy , Electrical & Computer Eng. Dept., University of Iowa, 52242, U.S.A.
pp. 1438-1443

Scheduling for energy efficiency and fault tolerance in hard real-time systems (PDF)

Yu Liu , ECE, University of Illinois at Chicago, USA
Han Liang , Digital Media Group, Trident Microsystems, Inc., USA
Kaijie Wu , ECE, University of Illinois at Chicago, USA
pp. 1444-1449

Scoped identifiers for efficient bit aligned logging (PDF)

Roy Shea , Computer Science Department, University of California, Los Angeles, 90095-1594, USA
Mani Srivastava , Electrical Engineering and Computer Departments, University of California, Los Angeles, 90095-1594, USA
Young Cho , Information Sciences Institute, University of Southern California, Los Angeles, 90292-6611, USA
pp. 1450-1455

Linear programming approach for performance-driven data aggregation in networks of embedded sensors (PDF)

Cristian Ferent , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
Varun Subramanian , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
Michael Gilberti , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
Alex Doboli , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
pp. 1456-1461

Soft error-aware design optimization of low power and time-constrained embedded systems (PDF)

Rishad A. Shafik , School of ECS, University of Southampton, SO17 1BJ, UK
Bashir M. Al-Hashimi , School of ECS, University of Southampton, SO17 1BJ, UK
Krishnendu Chakrabarty , Department of ECE, Duke University, Durham, NC 27708, USA
pp. 1462-1467

Contango: Integrated optimization of SoC clock networks (PDF)

Dongjin Lee , University of Michigan, 2260 Hayward St., Ann Arbor, 48109, USA
Igor L. Markov , University of Michigan, 2260 Hayward St., Ann Arbor, 48109, USA
pp. 1468-1473

Clock skew optimization considering complicated power modes (PDF)

Chiao-Ling Lung , National Tsing-Hua University, HsinChu, Taiwan
Zi-Yi Zeng , National Tsing-Hua University, HsinChu, Taiwan
Chung-Han Chou , National Tsing-Hua University, HsinChu, Taiwan
Shih-Chieh Chang , National Tsing-Hua University, HsinChu, Taiwan
pp. 1474-1479

A general method to make multi-clock system deterministic (PDF)

Menghao Su , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Yunji Chen , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Xiang Gao , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
pp. 1480-1485

Embedded software testing: What kind of problem is this? (PDF)

Erika Cota , PPGC - Instituto de Informática, Universidade Federal do Rio Grande do Sul, Po Box 15064, ZIP 91501-970 - Porto Alegre, Brazil
pp. 1486

Cool MPSoC programming (PDF)

Rainer Leupers , RWTH Aachen University, Germany
Xiaoning Nie , Infineon Technologies, Germany
Matthias Weiss , Blue Wonder Communications, Germany
Lothar Thiele , ETH Zurich, Switzerland
Bart Kienhuis , Compaan Design, Netherlands
Tsuyoshi Isshiki , Tokyo Institute of Technology, Japan
pp. 1488-1493

Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study (PDF)

Hong-Zu Chou , Electrical Engineering Department, National Taiwan University, Taipei, Taiwan
Haiqian Yu , Teradyne Inc., North Reading, MA, USA
Kai-Hui Chang , Avery Design Systems, Inc., Andover, MA, USA
Dylan Dobbyn , Teradyne Inc., North Reading, MA, USA
Sy-Yen Kuo , Electrical Engineering Department, National Taiwan University, Taipei, Taiwan
pp. 1494-1499

Optimizing equivalence checking for behavioral synthesis (PDF)

Kecheng Hao , Department of Computer Science, Portland State University, OR 97207, USA
Fei Xie , Department of Computer Science, Portland State University, OR 97207, USA
Sandip Ray , Department of Computer Sciences, University of Texas at Austin, 78712, USA
Jin Yang , Strategic CAD Labs, DTS, Intel Corporation, Hillsboro, OR 97124, USA
pp. 1500-1505

Checking and deriving module paths in Verilog cell library descriptions (PDF)

Matthias Raffelsieper , CS Dept., TU/Eindhoven, The Netherlands
MohammadReza Mousavi , CS Dept., TU/Eindhoven, The Netherlands
Chris Strolenberg , Fenix, Eindhoven, The Netherlands
pp. 1506-1511

BACH 2 : Bounded reachability checker for compositional linear hybrid systems (PDF)

Lei Bu , State Key Laboratory for Novel Software Technology, Nanjing University, Jiangsu, China 210093
You Li , State Key Laboratory for Novel Software Technology, Nanjing University, Jiangsu, China 210093
Linzhang Wang , State Key Laboratory for Novel Software Technology, Nanjing University, Jiangsu, China 210093
Xin Chen , State Key Laboratory for Novel Software Technology, Nanjing University, Jiangsu, China 210093
Xuandong Li , State Key Laboratory for Novel Software Technology, Nanjing University, Jiangsu, China 210093
pp. 1512-1517

DVFS based task scheduling in a harvesting WSN for Structural Health Monitoring (PDF)

A. Ravinagarajan , Computer Science and Engineering, University of California San Diego, La Jolla, USA
D. Dondi , Computer Science and Engineering, University of California San Diego, La Jolla, USA
T Simunic Rosing , Computer Science and Engineering, University of California San Diego, La Jolla, USA
pp. 1518-1523

Power-accuracy tradeoffs in human activity transition detection (PDF)

Jeffrey Boyd , School of Computing, Informatics, and Decision Systems Engineering, Arizona State University, Tempe, USA
Hari Sundaram , School of Computing, Informatics, and Decision Systems Engineering, Arizona State University, Tempe, USA
Aviral Shrivastava , School of Computing, Informatics, and Decision Systems Engineering, Arizona State University, Tempe, USA
pp. 1524-1529

Non-invasive blood oxygen saturation monitoring for neonates using reflectance pulse oximeter (PDF)

Wei Chen , Department of Industrial Design, Eindhoven University of Technology, Den Dolech 2, 5612 AZ, The Netherlands
Idowu Ayoola , Department of Industrial Design, Eindhoven University of Technology, Den Dolech 2, 5612 AZ, The Netherlands
Sidarto Bambang Oetomo , Department of Industrial Design, Eindhoven University of Technology, Den Dolech 2, 5612 AZ, The Netherlands
Loe Feijs , Department of Industrial Design, Eindhoven University of Technology, Den Dolech 2, 5612 AZ, The Netherlands
pp. 1530-1535

An active vision system for fall detection and posture recognition in elderly healthcare (PDF)

G. Diraco , CNR-IMM, Via Monteroni, presso Campus Universitario, Palazzina A3 - 73100 Lecce, Italy
A. Leone , CNR-IMM, Via Monteroni, presso Campus Universitario, Palazzina A3 - 73100 Lecce, Italy
P. Siciliano , CNR-IMM, Via Monteroni, presso Campus Universitario, Palazzina A3 - 73100 Lecce, Italy
pp. 1536-1541

A Smart Space application to dynamically relate medical and environmental information (PDF)

Fabio Vergari , DEIS, Alma Mater Studiorum - Università di Bologna, Italy
Sara Bartolini , DEIS, Alma Mater Studiorum - Università di Bologna, Italy
Federico Spadini , ARCES, Alma Mater Studiorum - Università di Bologna, Italy
Alfredo D'Elia , ARCES, Alma Mater Studiorum - Università di Bologna, Italy
Guido Zamagni , ARCES, Alma Mater Studiorum - Università di Bologna, Italy
Luca Roffia , ARCES, Alma Mater Studiorum - Università di Bologna, Italy
Tullio Salmon Cinotti , ARCES, Alma Mater Studiorum - Università di Bologna, Italy
pp. 1542-1547

An architecture for self-organization in pervasive systems (PDF)

Aly. A. Syed , NXP Corporate Innovation and Technology/Research High Tech. Campus 32, 5656 AE Eindhoven, The Netherlands
Johan Lukkien , Department of Mathematics and Computer Science, Den Dolech 2, 5612 AZ Eindhoven, The Netherlands
Roxana Frunza , TOPIC Embedded Systems, Eindhovenseweg 32-C, 5683 KH BEST, The Netherlands
pp. 1548-1553

TIMBER: Time borrowing and error relaying for online timing error resilience (PDF)

Mihir Choudhury , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Vikas Chandra , ARM R&D, San Jose, USA
Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Robert Aitken , ARM R&D, San Jose, USA
pp. 1554-1559

ERSA: Error Resilient System Architecture for probabilistic applications (PDF)

Larkhoon Leem , Department of Electrical Engineering, Stanford University, CA, USA
Hyungmin Cho , Department of Electrical Engineering, Stanford University, CA, USA
Jason Bau , Department of Electrical Engineering, Stanford University, CA, USA
Quinn A. Jacobson , Nokia Research Center, Palo Alto, CA, USA
Subhasish Mitra , Department of Electrical Engineering, Stanford University, CA, USA
pp. 1560-1565

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors (PDF)

Lei Zhang , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Yue Yu , Department of Computer Science, Illinois Institute of Technology, USA
Jianbo Dong , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Yinhe Han , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Shangping Ren , Department of Computer Science, Illinois Institute of Technology, USA
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
pp. 1566-1571

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors (PDF)

Pramod Subramanyan , Supercomputer Education and Research Center, Indian Institute of Science, Bangalore, India
Virendra Singh , Supercomputer Education and Research Center, Indian Institute of Science, Bangalore, India
Kewal K. Saluja , Electrical and Computer Engg. Dept., University of Wisconsin-Madison, USA
Erik Larsson , Dept. of Computer and Info. Science, Linköping University, Sweden
pp. 1572-1577

Robust design of embedded systems (Abstract)

Martin Lukasiewycz , University of Erlangen-Nuremberg, Germany
Michael Glass , University of Erlangen-Nuremberg, Germany
Jurgen Teich , University of Erlangen-Nuremberg, Germany
pp. 1578-1583

Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint (PDF)

Lin Huang , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., China
pp. 1584-1589

PM-COSYN: PE and memory co-synthesis for MPSoCs (PDF)

Yi-Jung Chen , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan
Chia-Lin Yang , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan
Po-Han Wang , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan
pp. 1590-1595

Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs (PDF)

Brett H. Meyer , Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA 15213, USA
Adam S. Hartman , Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA 15213, USA
Donald E. Thomas , Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA 15213, USA
pp. 1596-1601

Efficient power conversion for ultra low voltage micro scale energy transducers (PDF)

Chao Lu , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Sang Phill Park , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Vijay Raghunathan , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
pp. 1602-1607

Transmitting TLM transactions over analogue wire models (Abstract)

Stephan Schulz , Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division, Zeunerstr. 38, 01069 Dresden, Germany
Jorg Becker , Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division, Zeunerstr. 38, 01069 Dresden, Germany
Thomas Uhle , Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division, Zeunerstr. 38, 01069 Dresden, Germany
Karsten Einwich , Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division, Zeunerstr. 38, 01069 Dresden, Germany
Soren Sonntag , Lantiq Deutschland GmbH, Design Platforms & Services, Neubiberg, Germany
pp. 1608-1613

Intent-leveraged optimization of analog circuits via homotopy (PDF)

Metha Jeeradit , Computer Systems Laboratory, Stanford University, CA, USA
Jaeha Kim , Computer Systems Laboratory, Stanford University, CA, USA
Mark Horowitz , Computer Systems Laboratory, Stanford University, CA, USA
pp. 1614-1619

Optimal regulation of traffic flows in networks-on-chip (PDF)

Fahimeh Jafari , Ferdowsi University of Mashhad, Iran
Zhonghai Lu , Royal Institute of Technology (KTH), Sweden
Axel Jantsch , Royal Institute of Technology (KTH), Sweden
Mohammad H. Yaghmaee , Ferdowsi University of Mashhad, Iran
pp. 1621-1624

A method to remove deadlocks in Networks-on-Chips with Wormhole flow control (PDF)

Ciprian Seiculescu , LSI, EPFL, Lausanne, Switzerland
Srinivasan Murali , iNoCs, Lausanne, Switzerland
Luca Benini , DEIS, University of Bologna, Italy
Giovanni De Micheli , LSI, EPFL, Lausanne, Switzerland
pp. 1625-1628

An analytical method for evaluating Network-on-Chip performance (PDF)

Sahar Foroutan , ST-Microelectronics, Switzerland
Yvain Thonnart , CEA-Leti, France
Richard Hersemeule , ST-Microelectronics, Switzerland
Ahmed Jerraya , CEA-Leti, France
pp. 1629-1632

A low-area flexible MIMO detector for WiFi/WiMAX standards (PDF)

Nariman Moezzi-Madani , Electrical and Computer Engineering Department, North Carolina State University, Raleigh, USA
Thorlindur Thorolfsson , Electrical and Computer Engineering Department, North Carolina State University, Raleigh, USA
William Rhett Davis , Electrical and Computer Engineering Department, North Carolina State University, Raleigh, USA
pp. 1633-1636

An embedded wide-range and high-resolution CLOCK jitter measurement circuit (PDF)

Yu Lee , SOC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan
Ching-Yuan Yang , Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan
Nai-Chen Daniel Cheng , SOC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan
Ji-Jan Chen , SOC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan
pp. 1637-1640

Analog circuit test based on a digital signature (Abstract)

A. Gomez , Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Av. Diagonal 647, planta 9, E-08028 Barcelona (Spain)
R. Sanahuja , Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Av. Diagonal 647, planta 9, E-08028 Barcelona (Spain)
L. Balado , Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Av. Diagonal 647, planta 9, E-08028 Barcelona (Spain)
J. Figueras , Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Av. Diagonal 647, planta 9, E-08028 Barcelona (Spain)
pp. 1641-1644

DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimation (Abstract)

Nabeel Iqbal , Karlsruhe Institute of Technology (KIT), Chair for Embedded Systems, Germany
M.Adnan Siddique , Karlsruhe Institute of Technology (KIT), Chair for Embedded Systems, Germany
Jorg Henkel , Karlsruhe Institute of Technology (KIT), Chair for Embedded Systems, Germany
pp. 1645-1648

Taming the component timing: A CBD methodology for real-time embedded systems (PDF)

Manoj G. Dixit , India Science Lab, GM R&D, India
Pallab Dasgupta , Indian Institute of Technology, Kharagpur, India
S. Ramesh , India Science Lab, GM R&D, India
pp. 1649-1652

Deterministic, predictable and light-weight multithreading using PRET-C (PDF)

Sidharta Andalam , Department of Electrical and Computer Engineering, University of Auckland, New Zealand
Partha S Roop , Department of Electrical and Computer Engineering, University of Auckland, New Zealand
Alain Girault , INRIA Rhone-Alpes, Grenoble, France
pp. 1653-1656

Inversed Temperature Dependence aware clock skew scheduling for sequential circuits (PDF)

Jieyi Long , Dept. of EECS, Northwestern Univ., Evaston, IL 60208, USA
Seda Ogrenci Memik , Dept. of EECS, Northwestern Univ., Evaston, IL 60208, USA
pp. 1657-1660

DynAHeal: Dynamic energy efficient task assignment for wireless healthcare systems (PDF)

Priti Aghera , CSE Department, UC San Diego, USA
Dilip Krishnaswamy , CSE Department, UC San Diego, USA
Diana Fang , CSE Department, UC San Diego, USA
Ayse Coskun , ECE Department, Boston University, USA
Tajana Rosing , CSE Department, UC San Diego, USA
pp. 1661-1664

Instruction precomputation with memoization for fault detection (PDF)

Demid Borodin , Delft University of Technology, The Netherlands
B.H.H. Juurlink , Delft University of Technology, The Netherlands
pp. 1665-1668

Simultaneous budget and buffer size computation for throughput-constrained task graphs (PDF)

Maarten H. Wiggers , Eindhoven University of Technology, The Netherlands
Marco J.G. Bekooij , NXP Semiconductors, The Netherlands
Marc C.W. Geilen , Eindhoven University of Technology, The Netherlands
Twan Basten , Eindhoven University of Technology, The Netherlands
pp. 1669-1672

An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits (PDF)

Xiaoda Pan , State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, China
Fan Yang , State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, China
Xuan Zeng , State Key Lab. of ASIC & System, Microelectronics Department, Fudan University, China
Yangfeng Su , School of Mathematical Sciences, Fudan University, China
pp. 1673-1676

Panel session - great challenges in nanoelectronics and impact on academic research: More than Moore or Beyond CMOS? (PDF)

R De Keersmaeker , IMEC and Catrene, BE
M. Roukes , Caltech, US
D. Antoinadis , MIT, US
H. De Man , KU Leuven and IMEC, BE
G. Bourianoff , SRC and Intel, US
M. Brillouet , CEA-LETI, FR
L. Samuelson , Lund U, SE
pp. 1677

3D-integration of silicon devices: A key technology for sophisticated products (PDF)

A. Klumpp , Nanomaterials, Devices and Silicon Processing, NDS, Fraunhofer Institute for Reliability and Microintegration Hansastr. 27d, 80686 Munich, Germany
P. Ramm , Nanomaterials, Devices and Silicon Processing, NDS, Fraunhofer Institute for Reliability and Microintegration Hansastr. 27d, 80686 Munich, Germany
R. Wieland , Nanomaterials, Devices and Silicon Processing, NDS, Fraunhofer Institute for Reliability and Microintegration Hansastr. 27d, 80686 Munich, Germany
pp. 1678-1683

Creating 3D specific systems: Architecture, design and CAD (PDF)

Paul D. Franzon , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh 27695, USA
W. Rhett Davis , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh 27695, USA
Thor Thorolffson , Department of Electrical and Computer Engineering, North Carolina State University, Raleigh 27695, USA
pp. 1684-1688

Testing TSV-based three-dimensional stacked ICs (PDF)

Erik Jan Marinissen , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium
pp. 1689-1694

Leveraging dominators for preprocessing QBF (PDF)

Hratch Mangassarian , University of Toronto, ECE Department, ON M5S 3G4, Canada
Bao Le , University of Toronto, ECE Department, ON M5S 3G4, Canada
Alexandra Goultiaeva , University of Toronto, CS Department, ON M5S 3G4, Canada
Andreas Veneris , University of Toronto, ECE Department, ON M5S 3G4, Canada
Fahiem Bacchus , University of Toronto, CS Department, ON M5S 3G4, Canada
pp. 1695-1700

Formal specification of networks-on-chips: deadlock and evacuation (PDF)

Freek Verbeek , Institute for Computing and Information Sciences, Radboud University Nijmegen, School of Computer Science, Open University of The Netherlands
Julien Schmaltz , Institute for Computing and Information Sciences, Radboud University Nijmegen, School of Computer Science, Open University of The Netherlands
pp. 1701-1706

Tighter integration of BDDs and SMT for Predicate Abstraction (PDF)

A. Cimatti , FBK-irst, Trento, Italy
A. Franzen , FBK-irst, Trento, Italy
A. Griggio , University of Trento DISI, Italy
K. Kalyanasundaram , FBK-irst, Trento, Italy
M. Roveri , FBK-irst, Trento, Italy
pp. 1707-1712

An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion (Abstract)

Muhammad Shafique , Karlsruhe Institute of Technology, Chair for Embedded Systems, Germany
Bastian Molkenthin , Karlsruhe Institute of Technology, Chair for Embedded Systems, Germany
Jorg Henkel , Karlsruhe Institute of Technology, Chair for Embedded Systems, Germany
pp. 1713-1718

Scheduling and energy-distortion tradeoffs with operational refinement of image processing (PDF)

Davide Anastasia , Dept. of Electronic and Electrical Engineering, University College London, UK
Yiannis Andreopoulos , Dept. of Electronic and Electrical Engineering, University College London, UK
pp. 1719-1724

enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder (Abstract)

Muhammad Shafique , Karlsruhe Institute of Technology, Chair for Embedded Systems, Germany
Lars Bauer , Karlsruhe Institute of Technology, Chair for Embedded Systems, Germany
Jorg Henkel , Karlsruhe Institute of Technology, Chair for Embedded Systems, Germany
pp. 1725-1730

A method for design of impulse bursts noise filters optimized for FPGA implementations (PDF)

Zdenek Vasicek , Faculty of Information Technology, Brno University of Technology, Czech Republic
Lukas Sekanina , Faculty of Information Technology, Brno University of Technology, Czech Republic
Michal Bidlo , Faculty of Information Technology, Brno University of Technology, Czech Republic
pp. 1731-1736

Exploration of hardware sharing for image encoders (Abstract)

S. Lopez , Institute for Applied Microelectronics (IUMA), University of Las Palmas de Gran Canaria, SPAIN
R. Sarmiento , Institute for Applied Microelectronics (IUMA), University of Las Palmas de Gran Canaria, SPAIN
P.G. Potter , Department of Computing, Imperial College, London, UK
W. Luk , Department of Computing, Imperial College, London, UK
P.Y.K. Cheung , Department of Electrical and Electronic Engineering, Imperial College, London, UK
pp. 1737-1742

Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity map (PDF)

S. Hadjitheophanous , Department of Electrical and Computer Engineering, University of Cyprus, KIOS Research Center for Intelligent Systems and Networks, PO Box 20537, 1678 Nicosia, Cyprus
C. Ttofis , Department of Electrical and Computer Engineering, University of Cyprus, KIOS Research Center for Intelligent Systems and Networks, PO Box 20537, 1678 Nicosia, Cyprus
A. S. Georghiades , Department of Electrical and Computer Engineering, University of Cyprus, KIOS Research Center for Intelligent Systems and Networks, PO Box 20537, 1678 Nicosia, Cyprus
T. Theocharides , Department of Electrical and Computer Engineering, University of Cyprus, KIOS Research Center for Intelligent Systems and Networks, PO Box 20537, 1678 Nicosia, Cyprus
pp. 1743-1748

A robust ADC code hit counting technique (PDF)

Jiun-Lang Huang , Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Kuo-Yu Chou , Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Ming-Huan Lu , Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Xuan-Lun Huang , Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
pp. 1749-1754

An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links (PDF)

Mohamed Abbas , VLSI Design & Education Center, The University of Tokyo, 113-0032, Japan
Kwang-Ting Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA
Yasuo Furukawa , ADVANTEST Corporation, Gunma 370-0718, Japan
Satoshi Komatsu , VLSI Design & Education Center, The University of Tokyo, 113-0032, Japan
Kunihiro Asada , VLSI Design & Education Center, The University of Tokyo, 113-0032, Japan
pp. 1755-1760

Fault diagnosis of analog circuits based on machine learning (PDF)

Ke Huang , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
Salvador Mir , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
pp. 1761-1766

Block-level bayesian diagnosis of analogue electronic circuits (PDF)

Shaji Krishnan , Analytical Research Department, TNO, Zeist, The Netherlands
Klaas D. Doornbos , Business unit CAR, NXP Semiconductors, Nijmegen, The Netherlands
Rudi Brand , Business unit CAR, NXP Semiconductors, Nijmegen, The Netherlands
Hans G. Kerkhoff , CTIT-TDT, University of Twente, Enschede, The Netherlands
pp. 1767-1772

Control network generator for latency insensitive designs (PDF)

Eliyah Kilada , University of Utah, USA
Kenneth S. Stevens , University of Utah, USA
pp. 1773-1778

Using Speculative Functional Units in high level synthesis (PDF)

Alberto A. Del Barrio , Universidad Complutense de Madrid, Spain
Maria C. Molina , Universidad Complutense de Madrid, Spain
Jose M. Mendias , Universidad Complutense de Madrid, Spain
Roman Hermida , Universidad Complutense de Madrid, Spain
Seda Ogrenci Memik , Northwestern University, EECS Department, Evanston, Illinois, USA
pp. 1779-1784

Retiming multi-rate DSP algorithms to meet real-time requirement (PDF)

Xue-Yang Zhu , State Key Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences, China, Beijing 100190
pp. 1785-1790

Combining optimizations in automated low power design (PDF)

Qiang Liu , Department of Computing, Imperial College, London SW7 2AZ, UK
Tim Todman , Department of Computing, Imperial College, London SW7 2AZ, UK
Wayne Luk , Department of Computing, Imperial College, London SW7 2AZ, UK
pp. 1791-1796

A new quaternary FPGA based on a voltage-mode multi-valued circuit (Abstract)

Cristiano Lazzari , INESC-ID, Lisbon, Portugal
Paulo Flores , INESC-ID / IST, TU Lisbon, Portugal
Jose Monteiro , INESC-ID / IST, TU Lisbon, Portugal
Luigi Carro , Institute of Informatics - UFRGS, Porto Alegre, Brazil
pp. 1797-1802

An evaluation of a slice fault aware tool chain (PDF)

Adwait Gupte , Department of Electrical and Computer Engineering, Iowa State University, USA
Phillip Jones , Department of Electrical and Computer Engineering, Iowa State University, USA
pp. 1803-1808

Reliability- and process variation-aware placement for FPGAs (PDF)

Assem A. M. Bsoul , ECE Department, University of British Columbia, Vancouver, V6T 1Z4, Canada
Naraig Manjikian , ECE Department, Queen's University, Kingston, ON K7L 3N6, Canada
Li Shang , ECE Department, University of Colorado at Boulder, 80309, U.S.A.
pp. 1809-1814
101 ms
(Ver 3.3 (11022016))