The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2009)
Nice France
Apr. 20, 2009 to Apr. 24, 2009
ISSN: 1530-1591
ISBN: 978-1-4244-3781-8
TABLE OF CONTENTS

Start (PDF)

pp. i

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips (Abstract)

Ciprian Seiculescu , LSI, EPFL, Lausanne, Switzerland
Srinivasan Murali , iNoCs, Lausanne, Switzerland
Luca Benini , DEIS, Univerity of Bologna, Italy
Giovanni De Micheli , LSI, EPFL, Lausanne, Switzerland
pp. 9-14

A highly resilient routing algorithm for fault-tolerant NoCs (Abstract)

David Fick , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
Andrew DeOrio , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
Gregory Chen , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
Valeria Bertacco , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
Dennis Sylvester , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
David Blaauw , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
pp. 21-26

Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture (Abstract)

Sean Whitty , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig 38106, Germany
Henning Sahlbach , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig 38106, Germany
Rolf Ernst , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig 38106, Germany
Wolfram Putzke-Roming , Deutsche Thomson OHG, 30625 Hannover, Germany
pp. 27-32

DPR in high energy physics (Abstract)

Wenxue Gao , Lehrstuhl Informatik V, B6,26, 68131 Mannheim, Germany
Andreas Kugel , Lehrstuhl Informatik V, B6,26, 68131 Mannheim, Germany
Reinhard Manner , Lehrstuhl Informatik V, B6,26, 68131 Mannheim, Germany
Norbert Abel , Kirchhoff Institute for Physics, Im Neuenheimer Feld 227, 69120 Heidelberg, Germany
Nick Meier , Kirchhoff Institute for Physics, Im Neuenheimer Feld 227, 69120 Heidelberg, Germany
Udo Kebschull , Kirchhoff Institute for Physics, Im Neuenheimer Feld 227, 69120 Heidelberg, Germany
pp. 39-44

A flexible layered architecture for accurate digital baseband algorithm development and verification (Abstract)

Amirhossein Alimohammad , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Saeed F. Fard , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Bruce F. Cockburn , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
pp. 45-50

Integrated scheduling and synthesis of control applications on distributed embedded systems (Abstract)

Soheil Samii , Department of Computer and Information Science, Linköping University, Sweden
Anton Cervin , Department of Automatic Control, Lund University, Sweden
Petru Eles , Department of Computer and Information Science, Linköping University, Sweden
Zebo Peng , Department of Computer and Information Science, Linköping University, Sweden
pp. 57-62

A self-adaptive system architecture to address transistor aging (Abstract)

Omer Khan , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA 01002
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA 01002
pp. 81-86

Masking timing errors on speed-paths in logic circuits (Abstract)

Mihir R. Choudhury , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005 USA
Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005 USA
pp. 87-92

WCRT algebra and interfaces for esterel-style synchronous processing (Abstract)

Michael Mendler , Faculty of Inform. Sys. and Appl. Comp. Sciences, The University of Bamberg, Germany
Reinhard von Hanxleden , Department of Computer Science, Christian-Albrechts-Universität zu Kiel, Germany
Claus Traulsen , Department of Computer Science, Christian-Albrechts-Universität zu Kiel, Germany
pp. 93-98

Reliable mode changes in real-time systems with fixed priority or EDF scheduling (Abstract)

Nikolay Stoimenov , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
Simon Perathoner , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
Lothar Thiele , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
pp. 99-104

Improved worst-case response-time calculations by upper-bound conditions (Abstract)

Victor Pollex , Ulm University, Institute of Embedded Systems/Real-Time Systems, Germany
Steffen Kollmann , Ulm University, Institute of Embedded Systems/Real-Time Systems, Germany
Karsten Albers , Ulm University, Institute of Embedded Systems/Real-Time Systems, Germany
Frank Slomka , Ulm University, Institute of Embedded Systems/Real-Time Systems, Germany
pp. 105-110

A generalized scheduling approach for dynamic dataflow applications (Abstract)

William Plishker , Electrical and Computer Engineering Department, University of Maryland, College Park, USA
Nimish Sane , Electrical and Computer Engineering Department, University of Maryland, College Park, USA
Shuvra S. Bhattacharyya , Electrical and Computer Engineering Department, University of Maryland, College Park, USA
pp. 111-116

Multi-clock Soc design using protocol conversion (Abstract)

Roopak Sinha , University of Auckland, New Zealand
Partha S. Roop , University of Auckland, New Zealand
Samik Basu , Iowa State University, USA
Zoran Salcic , Starfleet Academy, University of Auckland, New Zealand
pp. 123-128

A formal approach to design space exploration of protocol converters (Abstract)

Karin Avnit , School of Computer Science and Engineering, The University of New South Wales, Sydney Australia
Arcot Sowmya , School of Computer Science and Engineering, The University of New South Wales, Sydney Australia
pp. 129-134

Model-based synthesis and optimization of static multi-rate image processing algorithms (Abstract)

Joachim Keinert , Fraunhofer IIS, Digital Cinema Department, Erlangen, Germany
Hritam Dutta , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Frank Hannig , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Christian Haubelt , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
pp. 135-140

Minimization of NBTI performance degradation using internal node control (Abstract)

David R. Bild , EECS Department, University of Michigan, Ann Arbor, 48109, USA
Gregory E. Bok , Nico Trading, 311 S. Wacker Drive, Suite 900, Chicago, IL 60606, USA
Robert P. Dick , EECS Department, University of Michigan, Ann Arbor, 48109, USA
pp. 148-153

Physically clustered forward body biasing for variability compensation in nanometer CMOS design (Abstract)

Ashoka Sathanur , Politecnico di Torino, Ecole Polytechnique Fédérale de Lausanne, Switzerland
Antonio Pullini , Ecole Polytechnique Fédérale de Lausanne, Switzerland
Luca Benini , Università di Bologna, Italy
Giovanni De Micheli , Ecole Polytechnique Fédérale de Lausanne, Switzerland
Enrico Macii , Politecnico di Torino, Italy
pp. 154-159

Design and implementation of a database filter for BLAST acceleration (Abstract)

Panagiotis Afratis , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Constantinos Galanakis , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Euripides Sotiriades , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Georgios-Grigorios Mplemenos , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Grigorios Chrysos , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Ioannis Papaefstathiou , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Dionisios Pnevmatikatos , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
pp. 166-171

Priority-based packet communication on a bus-shaped structure for FPGA-systems (Abstract)

Oliver Sander , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
Benjamin Glas , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
Christoph Roth , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
Jurgen Becker , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
Klaus D. Muller-Glaser , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
pp. 178-183

Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor (Abstract)

Syed Zahid Ahmed , Menta, France
Julien Eydoux , Menta, France
Laurent Rouge , Menta, France
Jean-Baptiste Cuelle , Menta, France
Gilles Sassatelli , University of Montpellier 2, UMR CNRS 5506, LIRMM, France
Lionel Torres , University of Montpellier 2, UMR CNRS 5506, LIRMM, France
pp. 184-189

Functional qualification of TLM verification (PDF)

Nicola Bombieri , Dipartimento di Informatica, Università di Verona, Italy
Franco Fummi , Dipartimento di Informatica, Università di Verona, Italy
Graziano Pravadelli , Dipartimento di Informatica, Università di Verona, Italy
Mark Hampton , Certess, Moirans, France
Florian Letombe , Certess, Moirans, France
pp. 190-195

A high-level debug environment for communication-centric debug (Abstract)

Kees Goossens , NXP Semiconductors Research / SOC Architectures and Infrastructure, 5656 AE Eindhoven, The Netherlands
Bart Vermeulen , NXP Semiconductors Research / SOC Architectures and Infrastructure, 5656 AE Eindhoven, The Netherlands
Ashkan Beyranvand Nejad , KTH, Royal Institute of Technology, Stockholm, Sweden
pp. 202-207

Cache aware compression for processor debug support (Abstract)

Anant Vishnoi , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
Preeti Ranjan Panda , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
M. Balakrishnan , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
pp. 208-213

A UML frontend for IP-XACT-based IP management (Abstract)

Tim Schattkowsky , Paderborn University/C-LAB, Germany
Tao Xie , Paderborn University/C-LAB, Germany
Wolfgang Mueller , Paderborn University/C-LAB, Germany
pp. 238-243

Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA (Abstract)

Tero Arpinen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
Tapio Koskinen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
Erno Salminen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
Timo D. Hamalainen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
Marko Hannikainen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
pp. 244-249

Configurable links for runtime adaptive on-chip communication (Abstract)

Mohammad Abdullah Al Faruque , University of Karlsruhe, Chair for Embedded Systems, Germany
Thomas Ebi , University of Karlsruhe, Chair for Embedded Systems, Germany
Jorg Henkel , University of Karlsruhe, Chair for Embedded Systems, Germany
pp. 256-261

SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems (Abstract)

Abelardo Jara-Berrocal , NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, Gainesville, 32611, USA
Ann Gordon-Ross , NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, Gainesville, 32611, USA
pp. 268-273

Reliability aware through silicon via planning for 3D stacked ICs (Abstract)

Amirali Shayan , CSE Dept., University of California San Diego, USA
Xiang Hu , ECE Dept., University of California San Diego, USA
He Peng , CSE Dept., University of California San Diego, USA
Chung-Kuan Cheng , CSE Dept., University of California San Diego, USA
Wenjian Yu , EDA Lab, CST Dept., Tsinghua University, Beijing, China
Mikhail Popovich , Qualcomm Inc., San Diego, CA, USA
Thomas Toms , Qualcomm Inc., San Diego, CA, USA
Xiaoming Chen , Qualcomm Inc., San Diego, CA, USA
pp. 288-291

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation (Abstract)

Kelageri Nagaraj , University of Massachusetts, Amherst, USA
Sandip Kundu , University of Massachusetts, Amherst, USA
pp. 292-295

Bitstream relocation with local clock domains for partially reconfigurable FPGAs (Abstract)

Adam Flynn , NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
Ann Gordon-Ross , NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
Alan D. George , NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
pp. 300-303

Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning (Abstract)

Martin Trautmann , Katholieke Universiteit Leuven, Belgium
Stylianos Mamagkakis , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Bruno Bougard , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Jeroen Declerck , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Erik Umans , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Antoine Dejonghe , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Liesbet Van der Perre , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Francky Catthoor , Katholieke Universiteit Leuven, Belgium
pp. 312-315

Gate replacement techniques for simultaneous leakage and aging optimization (Abstract)

Yu Wang , Dept. of E.E., TNList, Tsinghua Univ., Beijing, China
Xiaoming Chen , Dept. of E.E., TNList, Tsinghua Univ., Beijing, China
Wenping Wang , Dept. of E.E., Arizona State Univ., USA
Yu Cao , Dept. of E.E., Arizona State Univ., USA
Yuan Xie , Dept. of CSE, Pennsylvania State Univ., USA
Huazhong Yang , Dept. of E.E., TNList, Tsinghua Univ., Beijing, China
pp. 328-333

Communication minimization for in-network processing in body sensor networks: A buffer assignment technique (Abstract)

Hassan Ghasemzadeh , Embedded Systems and Signal Processing Lab, Department of Electrical Engineering, University of Texas at Dallas, Richardson, 75080-3021, USA
Nisha Jain , Embedded Systems and Signal Processing Lab, Department of Electrical Engineering, University of Texas at Dallas, Richardson, 75080-3021, USA
Marco Sgroi , Wireless Sensor Networks Lab sponsored by Pirelli and Telcom Italia, 1995 University Ave. Suite 225, Berkeley, CA 94704, USA
Roozbeh Jafari , Embedded Systems and Signal Processing Lab, Department of Electrical Engineering, University of Texas at Dallas, Richardson, 75080-3021, USA
pp. 358-363

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors (Abstract)

Subhasish Mitra , Department of Electrical Engineering and Department of Computer Science, Stanford University, CA, USA
Jie Zhang , Department of Electrical Engineering and Department of Computer Science, Stanford University, CA, USA
Nishant Patil , Department of Electrical Engineering and Department of Computer Science, Stanford University, CA, USA
Hai Wei , Department of Electrical Engineering and Department of Computer Science, Stanford University, CA, USA
pp. 436-441

UMTS MPSoC design evaluation using a system level design framework (Abstract)

Douglas Densmore , University of California, Berkeley, USA
Alena Simalatsar , University of Trento, Italy
Abhijit Davare , Intel Corporation, USA
Roberto Passerone , University of Trento, Italy
Alberto Sangiovanni-Vincentelli , University of California, Berkeley, USA
pp. 478-483

Improving yield and reliability of chip multiprocessors (Abstract)

Abhisek Pan , University Of Massachusetts, Amherst, USA
Omer Khan , University Of Massachusetts, Amherst, USA
Sandip Kundu , University Of Massachusetts, Amherst, USA
pp. 490-495

Statistical fault injection: Quantified error and confidence (Abstract)

R. Leveugle , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - France
A. Calvez , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - France
P. Maistri , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - France
P. Vanhauwaert , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - France
pp. 502-506

ReSim, a trace-driven, reconfigurable ILP processor simulator (Abstract)

Sotiria Fytraki , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Dionisios Pnevmatikatos , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
pp. 536-541

Algorithms for the automatic extension of an instruction-set (Abstract)

Carlo Galuzzi , Computer Engineering, Delft University of Technology, The Netherlands
Dimitris Theodoropoulos , Computer Engineering, Delft University of Technology, The Netherlands
Roel Meeuws , Computer Engineering, Delft University of Technology, The Netherlands
Koen Bertels , Computer Engineering, Delft University of Technology, The Netherlands
pp. 548-553

MPSoCs run-time monitoring through Networks-on-Chip (Abstract)

Leandro Fiorin , ALaRI, Faculty of Informatics, University of Lugano, Switzerland
Gianluca Palermo , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
Cristina Silvano , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
pp. 558-561

A link arbitration scheme for quality of service in a latency-optimized network-on-chip (Abstract)

Jonas Diemer , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, Germany
Rolf Ernst , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, Germany
pp. 574-577

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis (Abstract)

Shashikanth Bobba , LSI-EPFL, Lausanne (Switzerland)
Jie Zhang , Stanford University, (USA)
Antonio Pullini , LSI-EPFL, Lausanne (Switzerland)
David Atienza , ESL-EPFL, Lausanne (Switzerland)
Giovanni De Micheli , LSI-EPFL, Lausanne (Switzerland)
pp. 616-621

Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis (Abstract)

M. Haykel Ben Jamaa , Swiss Federal Institute of Technology, Lausanne, Switzerland
Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Giovanni De Micheli , Swiss Federal Institute of Technology, Lausanne, Switzerland
pp. 622-627

Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints (Abstract)

Laurent Sauvage , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
Sylvain Guilley , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
Jean-Luc Danger , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
Yves Mathieu , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
Maxime Nassar , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
pp. 640-645

Architectural support for low overhead detection of memory violations (Abstract)

Saugata Ghose , State University of New York, Binghamton, 13902, USA
Latoya Gilgeous , State University of New York, Binghamton, 13902, USA
Polina Dudnik , State University of New York, Binghamton, 13902, USA
Aneesh Aggarwal , State University of New York, Binghamton, 13902, USA
Corey Waxman , State University of New York, Binghamton, 13902, USA
pp. 652-657

Limiting the number of dirty cache lines (Abstract)

Pepijn de Langen , Computer Engineering Laboratory, Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, Mekelweg 4, 2628 CD, The Netherlands
Ben Juurlink , Computer Engineering Laboratory, Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, Mekelweg 4, 2628 CD, The Netherlands
pp. 670-675

Analysis and optimization of fault-tolerant embedded systems with hardened processors (Abstract)

Viacheslav Izosimov , Dept. of Computer and Inform. Science, Linköping University, SE-581 83, Sweden
Ilia Polian , Institute for Computer Science, Albert-Ludwigs-University of Freiburg, D-79110 Freiburg im Breisgau, Germany
Paul Pop , Dept. of Informatics and Math. Modelling, Technical University of Denmark, DK-2800 Kongens Lyngby, Denmark
Petru Eles , Dept. of Computer and Inform. Science, Linköping University, SE-581 83, Sweden
Zebo Peng , Dept. of Computer and Inform. Science, Linköping University, SE-581 83, Sweden
pp. 682-687

Massively multi-topology sizing of analog integrated circuits (Abstract)

Pieter Palmers , K.U.Leuven - Department of Electrical Engineering - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium)
Trent McConnaghy , K.U.Leuven - Department of Electrical Engineering - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium)
Michiel Steyaert , K.U.Leuven - Department of Electrical Engineering - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium)
Georges Gielen , K.U.Leuven - Department of Electrical Engineering - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium)
pp. 706-711

Computation of IP3 using single-tone moments analysis (Abstract)

Dani Tannir , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada, H3A 2A7
Roni Khazaka , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada, H3A 2A7
pp. 718-723

Using non-volatile memory to save energy in servers (Abstract)

David Roberts , University of Michigan, Department of CSE, Advanced Computer Architecture Lab, USA
Taeho Kgil , Intel Corporation, USA
Trevor Mudge , University of Michigan, Department of CSE, Advanced Computer Architecture Lab, USA
pp. 743-748

A real-time application design methodology for MPSoCs (Abstract)

Giovanni Beltrame , European Space Agency, Noordwijk, The Netherlands
Luca Fossati , Politecnico di Milano, Italy
Donatella Sciuto , Politecnico di Milano, Italy
pp. 767-772

Adaptive prefetching for shared cache based chip multiprocessors (Abstract)

Mahmut Kandemir , Computer Science and Engineering Department, Pennsylvania State University, University Park, 16802, USA
Yuanrui Zhang , Computer Science and Engineering Department, Pennsylvania State University, University Park, 16802, USA
Ozcan Ozturk , Computer Engineering Department, Bilkent University, Ankara, Turkey
pp. 773-778

CUFFS: An instruction count based architectural framework for security of MPSoCs (Abstract)

Krutartha Patel , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Sri Parameswaran , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Roshan G. Ragel , Department of Computer Engineering, University of Peradeniya, Sri Lanka
pp. 779-784

Detecting errors using multi-cycle invariance information (Abstract)

N. Alves , Division of Engineering, Brown University, Providence, RI 02906, USA
K. Nepal , Electrical Engineering Department, Bucknell University, Lewisburg, PA 17837, USA
J. Dworak , Division of Engineering, Brown University, Providence, RI 02906, USA
R. I. Bahar , Division of Engineering, Brown University, Providence, RI 02906, USA
pp. 791-796

Robust non-preemptive hard real-time scheduling for clustered multicore platforms (Abstract)

Michele Lombardi , DEIS - Università di Bologna, Italy
Michela Milano , DEIS - Università di Bologna, Italy
Luca Benini , DEIS - Università di Bologna, Italy
pp. 803-808

Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy (Abstract)

Andrea Marongiu , University of Bologna, Via Risorgimento, 2, 40136 Italy
Luca Benini , University of Bologna, Via Risorgimento, 2, 40136 Italy
pp. 809-814

Using randomization to cope with circuit uncertainty (Abstract)

Hamid Safizadeh , School of Computer Science, Institute for Research in Fundamental Sciences, Tehran, Iran
Mohammad Tahghighi , ECE Dept, Isfahan University of Technology, Iran
Ehsan K. Ardestani , CE Dept, University of California Santa Cruz, Santa Cruz, 95064, USA
Gholamhossein Tavasoli , ECE Dept, Isfahan University of Technology, Iran
Kia Bazargan , ECE Dept, Isfahan University of Technology, Iran
pp. 815-820

Process variation aware thread mapping for Chip Multiprocessors (Abstract)

S. Hong , Department of Computer Science and Enginneering, The Pennsylvania State University, USA
S.H.K. Narayanan , Department of Computer Science and Enginneering, The Pennsylvania State University, USA
M. Kandemir , Department of Computer Science and Enginneering, The Pennsylvania State University, USA
O. Ozturk , Department of Computer Engineering, Bilkent University, Turkey
pp. 821-826

The influence of real-time constraints on the design of FlexRay-based systems (Abstract)

Stephan Reichelt , Audi Electronics Venture GmbH, Germany
Oliver Scheickl , BMW Car IT GmbH, Germany
Gokhan Tabanoglu , Volkswagen AG, Germany
pp. 858-863

Time and memory tradeoffs in the implementation of AUTOSAR components (Abstract)

Alberto Ferrari , Parades, Via San Pantaleo 66, Roma, Italy
Marco Di Natale , ReTiS Lab., Scuola Superiore S. Anna, Via Moruzzi 1, Pisa, Italy
Giacomo Gentile , Magneti Marelli S.p.A., Via Timavo 33, Bologna, Italy
Giovanni Reggiani , Magneti Marelli S.p.A., Via Timavo 33, Bologna, Italy
Paolo Gai , Evidence Srl, Via Carducci 64, Ghezzano (Pi), Italy
pp. 864-869

Hardware/software co-design architecture for thermal management of chip multiprocessors (Abstract)

Omer Khan , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA 01002
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA 01002
pp. 952-957

Cross-architectural design space exploration tool for reconfigurable processors (Abstract)

Lars Bauer , University of Karlsruhe, Chair for Embedded Systems, Germany
Muhammad Shafique , University of Karlsruhe, Chair for Embedded Systems, Germany
Jorg Henkel , University of Karlsruhe, Chair for Embedded Systems, Germany
pp. 958-963

Automatically mapping applications to a self-reconfiguring platform (Abstract)

Karel Bruneel , Ghent University, ELIS Department, Sint-Pietersnieuwstraat 41, 9000 Belgium
Fatma Abouelella , Ghent University, ELIS Department, Sint-Pietersnieuwstraat 41, 9000 Belgium
Dirk Stroobandt , Ghent University, ELIS Department, Sint-Pietersnieuwstraat 41, 9000 Belgium
pp. 964-969

OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems (Abstract)

Andreas Schallenberg , Carl von Ossietzky University, Oldenburg, Germany
Wolfgang Nebel , Carl von Ossietzky University, Oldenburg, Germany
Andreas Herrholz , OFFIS Institute for Information Technology, Oldenburg, Germany
Philipp A. Hartmann , OFFIS Institute for Information Technology, Oldenburg, Germany
Frank Oppenheimer , OFFIS Institute for Information Technology, Oldenburg, Germany
pp. 970-975

Selection of a fault model for fault diagnosis based on unique responses (Abstract)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
Sudhakar M. Reddy , Electrical & Computer Eng. Dept., University of Iowa, 52242, U.S.A.
pp. 994-999

A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors (Abstract)

Aryabartta Sahu , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India, 110016
M. Balakrishnan , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India, 110016
Preeti Ranjan Panda , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India, 110016
pp. 1018-1023

Networked embedded system applications design driven by an abstract middleware environment (Abstract)

F. Fummi , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Italy
G. Perbellini , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Italy
Niccolo' Roncolato , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Italy
pp. 1024-1029

Health-care electronics The market, the challenges, the progress (Abstract)

Wolfgang Eberle , IMEC, Bioelectronic Systems Group, Leuven, Belgium
Ashwin S. Mecheri , IMEC, Bioelectronic Systems Group, Leuven, Belgium
Thi Kim Thoa Nguyen , IMEC, Bioelectronic Systems Group, Leuven, Belgium
Georges Gielen , KU Leuven, MICAS, Belgium
Raymond Campagnolo , CEA LETI, MINATEC, Grenoble, France
Alison Burdett , Toumaz Technology Ltd., Oxford, UK
Chris Toumazou , Institute of Biomed. Eng., Imperial College London, UK
Bart Volckaerts , Cochlear Technology Centre, Mechelen, Belgium
pp. 1030-1034

Design and implementation of scalable, transparent threads for multi-core media processor (Abstract)

Takeshi Kodaka , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Shunsuke Sasaki , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Takahiro Tokuyoshi , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Ryuichiro Ohyama , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Nobuhiro Nonogaki , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Koji Kitayama , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Tatsuya Mori , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Yasuyuki Ueda , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Hideho Arakida , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Yuji Okuda , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Toshiki Kizu , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Yoshiro Tsuboi , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Nobu Matsumoto , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
pp. 1035-1039

Embedded tutorial - Understanding multicore technologies (PDF)

A. Jerraya , CEA-LETI, France
G. Nicolescu , Polytechnique Montreal, Canada
pp. 1051

An efficent dynamic multicast routing protocol for distributing traffic in NOCs (Abstract)

Masoumeh Ebrahimi , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Masoud Daneshtalab , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Mohammad Hossein Neishaburi , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Siamak Mohammadi , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Ali Afzali-Kusha , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Juha Plosila , Department of Information Technology, University of Turku, Finland
Hannu Tenhunen , Department of Information Technology, University of Turku, Finland
pp. 1064-1069

Priority based forced requeue to reduce worst-case latencies for bursty traffic (Abstract)

Mikael Millberg , ECS - ICT - KTH, Royal Institute of Technology, Sweden
Axel Jantsch , ECS - ICT - KTH, Royal Institute of Technology, Sweden
pp. 1070-1075

CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. (Abstract)

Tobias Ziermann , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Stefan Wildermann , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
pp. 1088-1093

Shock immunity enhancement via resonance damping in gyroscopes for automotive applications (Abstract)

E. Marchetti , Dept. of Information Engineering, University of Pisa, Italy
L. Fanucci , Dept. of Information Engineering, University of Pisa, Italy
A. Rocchi , Sensordynamics AG, Navacchio (PI), Italy
M. De Marinis , Sensordynamics AG, Navacchio (PI), Italy
pp. 1094-1099

Finite Precision bit-width allocation using SAT-Modulo Theory (Abstract)

Adam B. Kinsman , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
pp. 1106-1111

Generation of compact test sets with high defect coverage (Abstract)

Xrysovalantis Kavousianos , Dept. of Computer Science, University of Ioannina, 45110, Greece
Krishnendu Chakrabarty , Dept. of Electrical & Computer Engineering, Duke University, 27708 Durham, NC, USA
pp. 1130-1135

A scalable method for the generation of small test sets (Abstract)

Santiago Remersaro , Mentor Graphics Corporation, USA
Janusz Rajski , Mentor Graphics Corporation, USA
Sudhakar M. Reddy , The University of Iowa, USA
Irith Pomeranz , Purdue University, USA
pp. 1136-1141

An automated flow for integrating hardware IP into the automotive systems engineering process (Abstract)

Jan-Hendrik Oetjens , Robert Bosch GmbH, AE/EIM3, Postfach 1342, 72703 Reutlingen, Germany
Ralph Gorgen , OFFIS Institute, R&D Division Transportation, Escherweg 2, 26121 Oldenburg, Germany
Joachim Gerlach , Robert Bosch GmbH, AE/EIM3, Postfach 1342, 72703 Reutlingen, Germany
Wolfgang Nebel , Carl v. Ossietzky University Embedded Hardware-/Software-Systems 26111 Oldenburg, Germany
pp. 1196-1201

EMC-aware design on a microcontroller for automotive applications (Abstract)

Patrice Joubert Doriol , STMicroelectronics, Agrate Brianza, 20041 Italy
Yamarita Villavicencio , Politecnico di Torino, 10129 Italy
Cristiano Forzan , STMicroelectronics, Agrate Brianza, 20041 Italy
Mario Rotigni , STMicroelectronics, Agrate Brianza, 20041 Italy
Giovanni Graziosi , STMicroelectronics, Agrate Brianza, 20041 Italy
Davide Pandini , STMicroelectronics, Agrate Brianza, 20041 Italy
pp. 1208-1213

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs (Abstract)

F. Abate , Politecnico di Torino, DAUIN - Dipartimento di Automatica e Informatica, Italy
L. Sterpone , Politecnico di Torino, DAUIN - Dipartimento di Automatica e Informatica, Italy
M. Violante , Politecnico di Torino, DAUIN - Dipartimento di Automatica e Informatica, Italy
F. Lima Kastensmidt , Universidade Federal do Rio Grande do Sul, Instituto de Informatica, Porto Alegre, Brasil
pp. 1226-1229

Finite precision processing in wireless applications (Abstract)

David Novo , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Min Li , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Bruno Bougard , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Liesbet Van der Perre , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Francky Catthoor , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
pp. 1230-1233

Test exploration and validation using transaction level models (Abstract)

Michael A. Kochte , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Christian G. Zoellin , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Michael E. Imhof , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Rauf Salimi Khaligh , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Martin Radetzki , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Hans-Joachim Wunderlich , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Stefano Di Carlo , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 TO, Italy
Paolo Prinetto , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 TO, Italy
pp. 1250-1253

Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes (Abstract)

Varun Subramanian , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
Michael Gilberti , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
Alex Doboli , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
pp. 1273-1278

Debugging of Toffoli networks (Abstract)

Robert Wille , Institute of Computer Science, University of Bremen, 28359, Germany
Daniel Grosse , Institute of Computer Science, University of Bremen, 28359, Germany
Stefan Frehse , Institute of Computer Science, University of Bremen, 28359, Germany
Gerhard W. Dueck , Faculty of Computer Science, University of New Brunswick, Fredericton, Canada
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 1284-1289

Error correction in single-hop wireless sensor networks - A case study (Abstract)

Daniel Schmidt , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663, Germany
Matthias Berning , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663, Germany
Norbert Wehn , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663, Germany
pp. 1296-1301

GCS: High-performance gate-level simulation with GPGPUs (Abstract)

Debapriya Chatterjee , Department of Computer Science and Engineering, University of Michigan, USA
Andrew DeOrio , Department of Computer Science and Engineering, University of Michigan, USA
Valeria Bertacco , Department of Computer Science and Engineering, University of Michigan, USA
pp. 1332-1337

Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing (Abstract)

Saqib Khursheed , School of ECS, University of Southampton, UK
Bashir M. Al-Hashimi , School of ECS, University of Southampton, UK
Peter Harrod , ARM Limited, Cambridge, UK
pp. 1349-1354

A diagnosis algorithm for extreme space compaction (Abstract)

Stefan Holst , Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47; D-70569, Germany
Hans-Joachim Wunderlich , Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47; D-70569, Germany
pp. 1355-1360

Using dynamic compilation for continuing execution under reduced memory availability (Abstract)

Ozcan Ozturk , Computer Engineering Department, Bilkent University, Ankara, Turkey
Mahmut Kandemir , Computer Science and Engineering Department, Pennsylvania State University, University Park, 16802, USA
pp. 1373-1378

Optimal sizing of configurable devices to reduce variability in integrated circuits (Abstract)

Peter Wilson , Electronics System Design Group, School of Electronics and Computer Science, University of Southampton, UK
Reuben Wilcock , Electronics System Design Group, School of Electronics and Computer Science, University of Southampton, UK
pp. 1385-1390

Dynamic thermal management in 3D multicore architectures (Abstract)

Ayse K. Coskun , Computer Science and Engineering Dept. (CSE), University of California, San Diego, USA
Jose L. Ayala , Computer Architecture and Automation Dept. (DACYA), Complutense University of Madrid, Spain
David Atienza , Embedded Systems Laboratory (ESL), Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Tajana Simunic Rosing , Computer Science and Engineering Dept. (CSE), University of California, San Diego, USA
Yusuf Leblebici , Microelectronics Systems Laboratory (LSM), EPFL, Switzerland
pp. 1410-1415

Energy minimization for real-time systems with non-convex and discrete operation modes (Abstract)

Foad Dabiri , Computer Science Department, University of California Los Angeles, USA
Alireza Vahdatpour , Computer Science Department, University of California Los Angeles, USA
Miodrag Potkonjak , Computer Science Department, University of California Los Angeles, USA
Majid Sarrafzadeh , Computer Science Department, University of California Los Angeles, USA
pp. 1416-1421

Visual quality analysis for dynamic backlight scaling in LCD systems (Abstract)

Andrea Bartolini , University of Bologna, DEIS, via Risorgimento 2, 40133, Italy
Martino Ruggiero , University of Bologna, DEIS, via Risorgimento 2, 40133, Italy
Luca Benini , University of Bologna, DEIS, via Risorgimento 2, 40133, Italy
pp. 1428-1433

Sequential logic synthesis using symbolic bi-decomposition (Abstract)

Victor N. Kravets , IBM TJ Watson Research Center, Yorktown Heights, NY USA
Alan Mishchenko , Department of EECS, University of California, Berkeley, USA
pp. 1458-1463

LFSR-based test-data compression with self-stoppable seeds (Abstract)

M. Koutsoupia , Comp. Eng. & Inf. Dept., University of Patras, Greece
E. Kalligeros , Information & Comm. Systems Eng., Dept., Univ. of the Aegean, Greece
X. Kavousianos , Computer Science Dept., Univ. of Ioannina, Greece
D. Nikolos , Comp. Eng. & Inf. Dept., University of Patras, Greece
pp. 1482-1487

SC-DEVS: An efficient SystemC extension for the DEVS model of computation (Abstract)

Felix Madlener , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
H. Gregor Molter , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
Sorin A. Huss , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
pp. 1518-1523

Runtime reconfiguration of custom instructions for real-time embedded systems (Abstract)

Huynh Phung Huynh , School of Computing, National University of Singapore
Tulika Mitra , School of Computing, National University of Singapore
pp. 1536-1541

Performance optimal speed control of multi-core processors under thermal constraints (Abstract)

Vinay Hanumaiah , Computer Science and Engineering Department, Arizona State University, Tempe 85281 USA
Sarma Vrudhula , Computer Science and Engineering Department, Arizona State University, Tempe 85281 USA
Karam S. Chatha , Computer Science and Engineering Department, Arizona State University, Tempe 85281 USA
pp. 1548-1551

Distributed peak power management for many-core architectures (Abstract)

John Sartori , Coordinated Science Laboratory, 1308West Main St, Urbana, IL 61801, USA
Rakesh Kumar , Coordinated Science Laboratory, 1308West Main St, Urbana, IL 61801, USA
pp. 1556-1559

Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC (Abstract)

Diego Puschini , CEA, LETI, MINATEC, F38054 Grenoble, France
Fabien Clermidy , CEA, LETI, MINATEC, F38054 Grenoble, France
Pascal Benoit , LIRMM, CNRS and University of Montpellier 2, France
Gilles Sassatelli , LIRMM, CNRS and University of Montpellier 2, France
Lionel Torres , CEA, LETI, MINATEC, F38054 Grenoble, France
pp. 1564-1567

Faster SAT solving with better CNF generation (Abstract)

Benjamin Chambers , Northeastern University, USA
Panagiotis Manolios , Northeastern University, USA
Daron Vroon , General Theological Seminary of the Episcopal Church, USA
pp. 1590-1595

Exploiting structure in an AIG based QBF solver (Abstract)

Florian Pigorsch , Albert-Ludwigs-Universität Freiburg, Institut für Informatik, D-79110 Freiburg im Breisgau, Germany
Christoph Scholl , Albert-Ludwigs-Universität Freiburg, Institut für Informatik, D-79110 Freiburg im Breisgau, Germany
pp. 1596-1601

ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications (Abstract)

Atif Raza Jafri , Institut TELECOM; TELECOM Bretagne; UMR CNRS 3192 Lab-STICC, Electronics Department, Technopôle Brest Iroise CS 83818, 29238 Brest Université Européenne de Bretagne, France
Daoud Karakolah , Institut TELECOM; TELECOM Bretagne; UMR CNRS 3192 Lab-STICC, Electronics Department, Technopôle Brest Iroise CS 83818, 29238 Brest Université Européenne de Bretagne, France
Amer Baghdadi , Institut TELECOM; TELECOM Bretagne; UMR CNRS 3192 Lab-STICC, Electronics Department, Technopôle Brest Iroise CS 83818, 29238 Brest Université Européenne de Bretagne, France
Michel Jezequel , Institut TELECOM; TELECOM Bretagne; UMR CNRS 3192 Lab-STICC, Electronics Department, Technopôle Brest Iroise CS 83818, 29238 Brest Université Européenne de Bretagne, France
pp. 1620-1625

Increased accuracy through noise injection in abstract RTOS simulation (Abstract)

Henning Zabel , Universität Paderborn, C-LAB, Fürstenallee 11, D-33102, Germany
Wolfgang Mueller , Universität Paderborn, C-LAB, Fürstenallee 11, D-33102, Germany
pp. 1632-1637

Selective state retention design using symbolic simulation (Abstract)

Ashish Darbari , School of Electronics and Computer Science, University of Southampton, England
Bashir M. Al Hashimi , School of Electronics and Computer Science, University of Southampton, England
David Flynn , ARM, Cambridge, England, UK
John Biggs , ARM, Cambridge, England, UK
pp. 1644-1649

A novel self-healing methodology for RF Amplifier circuits based on oscillation principles (Abstract)

Abhilash Goyal , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA-30332, USA
Madhavan Swaminathan , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA-30332, USA
Abhijit Chatterjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA-30332, USA
pp. 1656-1661

Enrichment of limited training sets in machine-learning-based analog/RF test (Abstract)

Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
Salvador Mir , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
Yiorgos Makris , Department of Electrical Engineering, Yale University, 10 Hillhouse Ave., New Haven, CT 06520, USA
pp. 1668-1673

Speculative reduction-based scalable redundancy identification (Abstract)

Hari Mony , IBM Systems & Technology Group, Austin, TX, USA
Jason Baumgartner , IBM Systems & Technology Group, Austin, TX, USA
Alan Mishchenko , Department of EECS, University of California, Berkeley, USA
Robert Brayton , Department of EECS, University of California, Berkeley, USA
pp. 1674-1679

Speeding up model checking by exploiting explicit and hidden verification constraints (Abstract)

G. Cabodi , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
P. Camurati , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
L. Garcia , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
M. Murciano , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
S. Nocco , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
S. Quer , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
pp. 1686-1691
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