The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2009)
Nice France
Apr. 20, 2009 to Apr. 24, 2009
ISSN: 1530-1591
ISBN: 978-1-4244-3781-8
TABLE OF CONTENTS

Start (PDF)

pp. i

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip (PDF)

Huaxi Gu , ECE, Hong Kong University of Science and Technology, China
Jiang Xu , ECE, Hong Kong University of Science and Technology, China
Wei Zhang , EE, Princeton University, NJ, USA
pp. 3-8

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips (Abstract)

Ciprian Seiculescu , LSI, EPFL, Lausanne, Switzerland
Srinivasan Murali , iNoCs, Lausanne, Switzerland
Luca Benini , DEIS, Univerity of Bologna, Italy
Giovanni De Micheli , LSI, EPFL, Lausanne, Switzerland
pp. 9-14

User-centric design space exploration for heterogeneous Network-on-Chip platforms (PDF)

Chen-Ling Chou , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
Radu Marculescu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
pp. 15-20

A highly resilient routing algorithm for fault-tolerant NoCs (Abstract)

David Fick , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
Andrew DeOrio , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
Gregory Chen , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
Valeria Bertacco , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
Dennis Sylvester , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
David Blaauw , Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA
pp. 21-26

Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture (Abstract)

Sean Whitty , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig 38106, Germany
Henning Sahlbach , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig 38106, Germany
Rolf Ernst , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig 38106, Germany
Wolfram Putzke-Roming , Deutsche Thomson OHG, 30625 Hannover, Germany
pp. 27-32

An ILP formulation for task mapping and scheduling on multi-core architectures (PDF)

Ying Yi , University of Edinburgh, The King's Buildings, Mayfield Road, Edinburgh, EH9 3JL, UK
Wei Han , University of Edinburgh, The King's Buildings, Mayfield Road, Edinburgh, EH9 3JL, UK
Xin Zhao , University of Edinburgh, The King's Buildings, Mayfield Road, Edinburgh, EH9 3JL, UK
Ahmet T. Erdogan , University of Edinburgh, The King's Buildings, Mayfield Road, Edinburgh, EH9 3JL, UK
Tughrul Arslan , University of Edinburgh, The King's Buildings, Mayfield Road, Edinburgh, EH9 3JL, UK
pp. 33-38

DPR in high energy physics (Abstract)

Wenxue Gao , Lehrstuhl Informatik V, B6,26, 68131 Mannheim, Germany
Andreas Kugel , Lehrstuhl Informatik V, B6,26, 68131 Mannheim, Germany
Reinhard Manner , Lehrstuhl Informatik V, B6,26, 68131 Mannheim, Germany
Norbert Abel , Kirchhoff Institute for Physics, Im Neuenheimer Feld 227, 69120 Heidelberg, Germany
Nick Meier , Kirchhoff Institute for Physics, Im Neuenheimer Feld 227, 69120 Heidelberg, Germany
Udo Kebschull , Kirchhoff Institute for Physics, Im Neuenheimer Feld 227, 69120 Heidelberg, Germany
pp. 39-44

A flexible layered architecture for accurate digital baseband algorithm development and verification (Abstract)

Amirhossein Alimohammad , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Saeed F. Fard , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
Bruce F. Cockburn , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2V4, Canada
pp. 45-50

Lifetime reliability-aware task allocation and scheduling for MPSoC platforms (PDF)

Lin Huang , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Feng Yuan , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
pp. 51-56

Integrated scheduling and synthesis of control applications on distributed embedded systems (Abstract)

Soheil Samii , Department of Computer and Information Science, Linköping University, Sweden
Anton Cervin , Department of Automatic Control, Lund University, Sweden
Petru Eles , Department of Computer and Information Science, Linköping University, Sweden
Zebo Peng , Department of Computer and Information Science, Linköping University, Sweden
pp. 57-62

Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude (PDF)

Chengmo Yang , Computer Science and Engineering Department, University of California, San Diego, 9500 Gilman Drive, La Jolla, 92093, USA
Alex Orailoglu , Computer Science and Engineering Department, University of California, San Diego, 9500 Gilman Drive, La Jolla, 92093, USA
pp. 63-68

Pipelined data parallel task mapping/scheduling technique for MPSoC (PDF)

Hoeseok Yang , School of EECS, Seoul National University, Korea
Soonhoi Ha , School of EECS, Seoul National University, Korea
pp. 69-74

Joint logic restructuring and pin reordering against NBTI-induced performance degradation (PDF)

Kai-Chiang Wu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
Diana Marculescu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA
pp. 75-80

A self-adaptive system architecture to address transistor aging (Abstract)

Omer Khan , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA 01002
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA 01002
pp. 81-86

Masking timing errors on speed-paths in logic circuits (Abstract)

Mihir R. Choudhury , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005 USA
Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005 USA
pp. 87-92

WCRT algebra and interfaces for esterel-style synchronous processing (Abstract)

Michael Mendler , Faculty of Inform. Sys. and Appl. Comp. Sciences, The University of Bamberg, Germany
Reinhard von Hanxleden , Department of Computer Science, Christian-Albrechts-Universität zu Kiel, Germany
Claus Traulsen , Department of Computer Science, Christian-Albrechts-Universität zu Kiel, Germany
pp. 93-98

Reliable mode changes in real-time systems with fixed priority or EDF scheduling (Abstract)

Nikolay Stoimenov , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
Simon Perathoner , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
Lothar Thiele , Computer Engineering and Networks Laboratory, ETH Zurich, 8092, Switzerland
pp. 99-104

Improved worst-case response-time calculations by upper-bound conditions (Abstract)

Victor Pollex , Ulm University, Institute of Embedded Systems/Real-Time Systems, Germany
Steffen Kollmann , Ulm University, Institute of Embedded Systems/Real-Time Systems, Germany
Karsten Albers , Ulm University, Institute of Embedded Systems/Real-Time Systems, Germany
Frank Slomka , Ulm University, Institute of Embedded Systems/Real-Time Systems, Germany
pp. 105-110

A generalized scheduling approach for dynamic dataflow applications (Abstract)

William Plishker , Electrical and Computer Engineering Department, University of Maryland, College Park, USA
Nimish Sane , Electrical and Computer Engineering Department, University of Maryland, College Park, USA
Shuvra S. Bhattacharyya , Electrical and Computer Engineering Department, University of Maryland, College Park, USA
pp. 111-116

Optimizing data flow graphs to minimize hardware implementation (PDF)

D. Gomez-Prado , ECE Dept., University of Massachusetts, Amherst, 01003, USA
Q. Ren , ECE Dept., University of Massachusetts, Amherst, 01003, USA
M. Ciesielski , ECE Dept., University of Massachusetts, Amherst, 01003, USA
J. Guillot , LAB-STICC, CNRS, Université de Bretagne Sud, Université Européenne de Bretagne, France
E. Boutillon , LAB-STICC, CNRS, Université de Bretagne Sud, Université Européenne de Bretagne, France
pp. 117-122

Multi-clock Soc design using protocol conversion (Abstract)

Roopak Sinha , University of Auckland, New Zealand
Partha S. Roop , University of Auckland, New Zealand
Samik Basu , Iowa State University, USA
Zoran Salcic , Starfleet Academy, University of Auckland, New Zealand
pp. 123-128

A formal approach to design space exploration of protocol converters (Abstract)

Karin Avnit , School of Computer Science and Engineering, The University of New South Wales, Sydney Australia
Arcot Sowmya , School of Computer Science and Engineering, The University of New South Wales, Sydney Australia
pp. 129-134

Model-based synthesis and optimization of static multi-rate image processing algorithms (Abstract)

Joachim Keinert , Fraunhofer IIS, Digital Cinema Department, Erlangen, Germany
Hritam Dutta , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Frank Hannig , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Christian Haubelt , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
pp. 135-140

Variation resilient adaptive controller for subthreshold circuits (PDF)

Biswajit Mishra , Electronic Systems and Devices Group, School of Electronics and Computer Science, University of Southampton, UK SO17 1BJ
Bashir M. Al-Hashimi , Electronic Systems and Devices Group, School of Electronics and Computer Science, University of Southampton, UK SO17 1BJ
Mark Zwolinski , Electronic Systems and Devices Group, School of Electronics and Computer Science, University of Southampton, UK SO17 1BJ
pp. 142-147

Minimization of NBTI performance degradation using internal node control (Abstract)

David R. Bild , EECS Department, University of Michigan, Ann Arbor, 48109, USA
Gregory E. Bok , Nico Trading, 311 S. Wacker Drive, Suite 900, Chicago, IL 60606, USA
Robert P. Dick , EECS Department, University of Michigan, Ann Arbor, 48109, USA
pp. 148-153

Physically clustered forward body biasing for variability compensation in nanometer CMOS design (Abstract)

Ashoka Sathanur , Politecnico di Torino, Ecole Polytechnique Fédérale de Lausanne, Switzerland
Antonio Pullini , Ecole Polytechnique Fédérale de Lausanne, Switzerland
Luca Benini , Università di Bologna, Italy
Giovanni De Micheli , Ecole Polytechnique Fédérale de Lausanne, Switzerland
Enrico Macii , Politecnico di Torino, Italy
pp. 154-159

An event-guided approach to reducing voltage noise in processors (PDF)

Meeta S. Gupta , School of Engineering and Applied Sciences, Harvard University, Cambridge, MA, USA
Vijay Janapa Reddi , School of Engineering and Applied Sciences, Harvard University, Cambridge, MA, USA
Glenn Holloway , School of Engineering and Applied Sciences, Harvard University, Cambridge, MA, USA
Gu-Yeon Wei , School of Engineering and Applied Sciences, Harvard University, Cambridge, MA, USA
David M. Brooks , School of Engineering and Applied Sciences, Harvard University, Cambridge, MA, USA
pp. 160-165

Design and implementation of a database filter for BLAST acceleration (Abstract)

Panagiotis Afratis , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Constantinos Galanakis , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Euripides Sotiriades , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Georgios-Grigorios Mplemenos , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Grigorios Chrysos , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Ioannis Papaefstathiou , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Dionisios Pnevmatikatos , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
pp. 166-171

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs (PDF)

Kostas Siozios , School of Electrical and Computer Engineering, National Technical University of Athens, Greece
Vasilis F. Pavlidis , LSI-EPFL, 1015 Lausanne, Switzerland
Dimitrios Soudris , School of Electrical and Computer Engineering, National Technical University of Athens, Greece
pp. 172-177

Priority-based packet communication on a bus-shaped structure for FPGA-systems (Abstract)

Oliver Sander , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
Benjamin Glas , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
Christoph Roth , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
Jurgen Becker , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
Klaus D. Muller-Glaser , Institute for Information Processing Technology (ITIV), Karlsruhe Institute of Technology (KIT), Germany
pp. 178-183

Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor (Abstract)

Syed Zahid Ahmed , Menta, France
Julien Eydoux , Menta, France
Laurent Rouge , Menta, France
Jean-Baptiste Cuelle , Menta, France
Gilles Sassatelli , University of Montpellier 2, UMR CNRS 5506, LIRMM, France
Lionel Torres , University of Montpellier 2, UMR CNRS 5506, LIRMM, France
pp. 184-189

Functional qualification of TLM verification (PDF)

Nicola Bombieri , Dipartimento di Informatica, Università di Verona, Italy
Franco Fummi , Dipartimento di Informatica, Università di Verona, Italy
Graziano Pravadelli , Dipartimento di Informatica, Università di Verona, Italy
Mark Hampton , Certess, Moirans, France
Florian Letombe , Certess, Moirans, France
pp. 190-195

Solver technology for system-level to RTL equivalence checking (PDF)

Alfred Koelbl , Verification Group, Synopsys, Inc., 2025 NW Cornelius Pass Rd., Hillsboro, OR 97124, USA
Reily Jacoby , Verification Group, Synopsys, Inc., 2025 NW Cornelius Pass Rd., Hillsboro, OR 97124, USA
Himanshu Jain , Verification Group, Synopsys, Inc., 2025 NW Cornelius Pass Rd., Hillsboro, OR 97124, USA
Carl Pixley , Verification Group, Synopsys, Inc., 2025 NW Cornelius Pass Rd., Hillsboro, OR 97124, USA
pp. 196-201

A high-level debug environment for communication-centric debug (Abstract)

Kees Goossens , NXP Semiconductors Research / SOC Architectures and Infrastructure, 5656 AE Eindhoven, The Netherlands
Bart Vermeulen , NXP Semiconductors Research / SOC Architectures and Infrastructure, 5656 AE Eindhoven, The Netherlands
Ashkan Beyranvand Nejad , KTH, Royal Institute of Technology, Stockholm, Sweden
pp. 202-207

Cache aware compression for processor debug support (Abstract)

Anant Vishnoi , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
Preeti Ranjan Panda , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
M. Balakrishnan , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India
pp. 208-213

Fault insertion testing of a novel CPLD-based fail-safe system (PDF)

Gerhard Griessnig , AVL LIST GMBH, Graz, Austria
Roland Mader , Graz University of Technology, Institute for Technical Informatics (ITI), Austria
Christian Steger , Graz University of Technology, Institute for Technical Informatics (ITI), Austria
Reinhold Weiss , Graz University of Technology, Institute for Technical Informatics (ITI), Austria
pp. 214-219

Test architecture design and optimization for three-dimensional SoCs (PDF)

Li Jiang , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Lin Huang , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
pp. 220-225

A co-design approach for embedded system modeling and code generation with UML and MARTE (PDF)

Jorgiano Vidal , European University of Brittany - UBS - CNRS, UMR 3192, Lab-STICC, Centre de Recherche - BP 92116 - F-56321 Lorient Cedex - FRANCE
Florent de Lamotte , European University of Brittany - UBS - CNRS, UMR 3192, Lab-STICC, Centre de Recherche - BP 92116 - F-56321 Lorient Cedex - FRANCE
Guy Gogniat , European University of Brittany - UBS - CNRS, UMR 3192, Lab-STICC, Centre de Recherche - BP 92116 - F-56321 Lorient Cedex - FRANCE
Philippe Soulard , SODIUS - 6 rue de Cornouaille - F-44300 NANTES - FRANCE
Jean-Philippe Diguet , European University of Brittany - UBS - CNRS, UMR 3192, Lab-STICC, Centre de Recherche - BP 92116 - F-56321 Lorient Cedex - FRANCE
pp. 226-231

Componentizing hardware/software interface design (PDF)

Kecheng Hao , Department of Computer Science, Portland State University, OR 97207, USA
Fei Xie , Department of Computer Science, Portland State University, OR 97207, USA
pp. 232-237

A UML frontend for IP-XACT-based IP management (Abstract)

Tim Schattkowsky , Paderborn University/C-LAB, Germany
Tao Xie , Paderborn University/C-LAB, Germany
Wolfgang Mueller , Paderborn University/C-LAB, Germany
pp. 238-243

Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA (Abstract)

Tero Arpinen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
Tapio Koskinen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
Erno Salminen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
Timo D. Hamalainen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
Marko Hannikainen , Tampere University of Technology, Department of Computer Systems, P.O. Box 553, FI-33101, Finland
pp. 244-249

Aelite: A flit-synchronous Network on Chip with composable and predictable services (PDF)

Andreas Hansson , Electronic Systems Group, Eindhoven University of Technology, The Netherlands
Mahesh Subburaman , Electrical Engineering, Linköping Institute of Technology, Sweden
Kees Goossens , Corporate Research Department, NXP Semiconductors, Eindhoven, The Netherlands
pp. 250-255

Configurable links for runtime adaptive on-chip communication (Abstract)

Mohammad Abdullah Al Faruque , University of Karlsruhe, Chair for Embedded Systems, Germany
Thomas Ebi , University of Karlsruhe, Chair for Embedded Systems, Germany
Jorg Henkel , University of Karlsruhe, Chair for Embedded Systems, Germany
pp. 256-261

Synthesis of low-overhead configurable source routing tables for network interfaces (PDF)

Igor Loi , DEIS, University of Bologna, Italy
Federico Angiolini , DEIS, University of Bologna, Italy
Luca Benini , DEIS, University of Bologna, Italy
pp. 262-267

SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems (Abstract)

Abelardo Jara-Berrocal , NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, Gainesville, 32611, USA
Ann Gordon-Ross , NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, Gainesville, 32611, USA
pp. 268-273

Analog layout synthesis - Recent advances in topological approaches (PDF)

H. Graeb , Institute for EDA, Technische Universitaet Muenchen, Germany
F. Balasa , Dept. of Computer Science and Information Systems, Southern Utah University, USA
R. Castro-Lopez , Institute of Microelectronics of Sevilla, CSIC and University of Sevilla, Spain
Y.-W. Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan
F.V. Fernandez , Institute of Microelectronics of Sevilla, CSIC and University of Sevilla, Spain
P.-H. Lin , Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan
M. Strasser , Institute for EDA, Technische Universitaet Muenchen, Germany
pp. 274-279

An accurate interconnect thermal model using equivalent transmission line circuit (PDF)

Baohua Wang , Dept. of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
Pinaki Mazumder , Dept. of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA
pp. 280-283

Analogue mixed signal simulation using spice and SystemC (PDF)

Tobias Kirchner , Robert Bosch GmbH, Corporate Sector Research and Advance Engineering, P.O. Box 30 02 40, 70442 Stuttgart, Germany
Nico Bannow , Robert Bosch GmbH, Corporate Sector Research and Advance Engineering, P.O. Box 30 02 40, 70442 Stuttgart, Germany
Christoph Grimm , Vienna University of Technology, Institute of Computer Technology, Austria
pp. 284-287

Reliability aware through silicon via planning for 3D stacked ICs (Abstract)

Amirali Shayan , CSE Dept., University of California San Diego, USA
Xiang Hu , ECE Dept., University of California San Diego, USA
He Peng , CSE Dept., University of California San Diego, USA
Chung-Kuan Cheng , CSE Dept., University of California San Diego, USA
Wenjian Yu , EDA Lab, CST Dept., Tsinghua University, Beijing, China
Mikhail Popovich , Qualcomm Inc., San Diego, CA, USA
Thomas Toms , Qualcomm Inc., San Diego, CA, USA
Xiaoming Chen , Qualcomm Inc., San Diego, CA, USA
pp. 288-291

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation (Abstract)

Kelageri Nagaraj , University of Massachusetts, Amherst, USA
Sandip Kundu , University of Massachusetts, Amherst, USA
pp. 292-295

Analysis and optimization of NBTI induced clock skew in gated clock trees (PDF)

Ashutosh Chakraborty , ECE Department, University of Texas at Austin, 78712, USA
Gokul Ganesan , ECE Department, University of Texas at Austin, 78712, USA
Anand Rajaram , ECE Department, University of Texas at Austin, 78712, USA
David Z. Pan , ECE Department, University of Texas at Austin, 78712, USA
pp. 296-299

Bitstream relocation with local clock domains for partially reconfigurable FPGAs (Abstract)

Adam Flynn , NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
Ann Gordon-Ross , NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
Alan D. George , NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA
pp. 300-303

Parallel transistor level full-chip circuit simulation (PDF)

He Peng , Department of Computer Science and Engineering, University of California, San Diego, La Jolla, 92093-0404, USA
Chung-Kuan Cheng , Department of Computer Science and Engineering, University of California, San Diego, La Jolla, 92093-0404, USA
pp. 304-307

Performance-driven dual-rail insertion for chip-level pre-fabricated design (PDF)

Fu-Wei Chen , Dept. of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Yi-Yu Liu , Dept. of Computer Science and Engineering, Yuan Ze University, Chungli, Taiwan, R.O.C.
pp. 308-311

Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning (Abstract)

Martin Trautmann , Katholieke Universiteit Leuven, Belgium
Stylianos Mamagkakis , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Bruno Bougard , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Jeroen Declerck , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Erik Umans , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Antoine Dejonghe , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Liesbet Van der Perre , Interuniversity Microelectronics Center (IMEC), Leuven, Belgium
Francky Catthoor , Katholieke Universiteit Leuven, Belgium
pp. 312-315

Fast and accurate protocol specific bus modeling using TLM 2.0 (PDF)

H.W.M. van Moll , Technical University Eindhoven, The Netherlands
H. Corporaal , Technical University Eindhoven, The Netherlands
V. Reyes , NXP Semiconductors, Eindhoven, The Netherlands
M. Boonen , NXP Semiconductors, Eindhoven, The Netherlands
pp. 316-319

Incorporating graceful degradation into embedded system design (PDF)

Michael Glass , University of Erlangen-Nuremberg, Germany
Martin Lukasiewycz , University of Erlangen-Nuremberg, Germany
Christian Haubelt , University of Erlangen-Nuremberg, Germany
Jurgen Teich , University of Erlangen-Nuremberg, Germany
pp. 320-323

Rewiring using IRredundancy Removal and Addition (PDF)

Chun-Chi Lin , Dept. of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Chun-Yao Wang , Dept. of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
pp. 324-327

Gate replacement techniques for simultaneous leakage and aging optimization (Abstract)

Yu Wang , Dept. of E.E., TNList, Tsinghua Univ., Beijing, China
Xiaoming Chen , Dept. of E.E., TNList, Tsinghua Univ., Beijing, China
Wenping Wang , Dept. of E.E., Arizona State Univ., USA
Yu Cao , Dept. of E.E., Arizona State Univ., USA
Yuan Xie , Dept. of CSE, Pennsylvania State Univ., USA
Huazhong Yang , Dept. of E.E., TNList, Tsinghua Univ., Beijing, China
pp. 328-333

Enabling concurrent clock and power gating in an industrial design flow (PDF)

Leticia Bolzani , Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY
Andrea Calimera , Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY
Alberto Macii , Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY
Enrico Macii , Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY
Massimo Poncino , Dipartimento di Automatica e Informatica, Politecnico di Torino, ITALY
pp. 334-339

TRAM: A tool for Temperature and Reliability Aware Memory Design (PDF)

Amin Khajeh , University of California, Irvine, USA
Aseem Gupta , University of California, Irvine, USA
Nikil Dutt , University of California, Irvine, USA
Fadi Kurdahi , University of California, Irvine, USA
Ahmed Eltawil , University of California, Irvine, USA
Kamal Khouri , Freescale Semiconductor Inc., 92697 USA Austin, TX 78729 USA
Magdy Abadir , Freescale Semiconductor Inc., 92697 USA Austin, TX 78729 USA
pp. 340-345

Aircraft integration real-time simulator modeling with AADL for architecture tradeoffs (PDF)

Jean Casteres , Simulation Industry Department, Airbus, 316 Route de Bayonne F-31060, Toulouse Cedex 9, France
Tovo Ramaherirariny , Simulation Industry Department, Airbus, 316 Route de Bayonne F-31060, Toulouse Cedex 9, France
pp. 346-351

A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips (PDF)

M. Sonza Reorda , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
C. Meinhardt , Unviersidade Federal do Rio Grande do Sul, Porto Alegre, Brasil
R. Reis , Unviersidade Federal do Rio Grande do Sul, Porto Alegre, Brasil
pp. 352-357

Communication minimization for in-network processing in body sensor networks: A buffer assignment technique (Abstract)

Hassan Ghasemzadeh , Embedded Systems and Signal Processing Lab, Department of Electrical Engineering, University of Texas at Dallas, Richardson, 75080-3021, USA
Nisha Jain , Embedded Systems and Signal Processing Lab, Department of Electrical Engineering, University of Texas at Dallas, Richardson, 75080-3021, USA
Marco Sgroi , Wireless Sensor Networks Lab sponsored by Pirelli and Telcom Italia, 1995 University Ave. Suite 225, Berkeley, CA 94704, USA
Roozbeh Jafari , Embedded Systems and Signal Processing Lab, Department of Electrical Engineering, University of Texas at Dallas, Richardson, 75080-3021, USA
pp. 358-363

A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standard (PDF)

Luca Larcher , DISMI - Università degli Studi di Modena e Reggio Emilia - Via Amendola 2, 42100, Italy
Riccardo Brama , DISMI - Università degli Studi di Modena e Reggio Emilia - Via Amendola 2, 42100, Italy
Marcello Ganzerli , DISMI - Università degli Studi di Modena e Reggio Emilia - Via Amendola 2, 42100, Italy
Jacopo Iannacci , Bruno Kessler Foundation - Via Sommarive 18, 38050 Povo, Trento, Italy
Marco Bedani , DEIS/ARCES - University of Bologna - Viale Risorgimento 2, 40136, Italy
Antonio Gnudi , DEIS/ARCES - University of Bologna - Viale Risorgimento 2, 40136, Italy
pp. 364-368

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing (PDF)

J. A. Diaz-Madrid , Integrated Circuit Design - Analog, Fraunhofer Institute for Integrated Circuits, Erlangen, Germany
H. Neubauer , Integrated Circuit Design - Analog, Fraunhofer Institute for Integrated Circuits, Erlangen, Germany
H. Hauer , Integrated Circuit Design - Analog, Fraunhofer Institute for Integrated Circuits, Erlangen, Germany
G. Domenech-Asensi , Dpto. de Electrónica y Tecnología de Computadoras, Universidad Politécnica de Cartagena, Spain
R. Ruiz-Merino , Dpto. de Electrónica y Tecnología de Computadoras, Universidad Politécnica de Cartagena, Spain
pp. 369-373

Analyzing the impact of process variations on parametric measurements: Novel models and applications (PDF)

Sherief Reda , Division of Engineering, Brown University, Providence, RI 02912, USA
Sani R. Nassif , Austin Research Laboratory, IBM Corporation, TX 78758, USA
pp. 375-380

On linewidth-based yield analysis for nanometer lithography (PDF)

Aswin Sreedhar , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA
pp. 381-386

A file-system-aware FTL design for flash-memory storage systems (PDF)

Po-Liang Wu , Department of Computer Science and Information Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C.
Yuan-Hao Chang , Department of Computer Science and Information Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C.
Tei-Wei Kuo , Department of Computer Science and Information Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C.
pp. 393-398

FSAF: File system aware flash translation layer for NAND Flash Memories (PDF)

Sai Krishna Mylavarapu , Department of Computer Science and Engineering, Arizona State University, United States
Siddharth Choudhuri , Center for Embedded Computer Systems, University of California, Irvine, United States
Aviral Shrivastava , Department of Computer Science and Engineering, Arizona State University, United States
Jongeun Lee , Department of Computer Science and Engineering, Arizona State University, United States
Tony Givargis , Department of Computer Science and Engineering, Arizona State University, United States
pp. 399-404

A set-based mapping strategy for flash-memory reliability enhancement (PDF)

Yuan-Sheng Chu , Wireless Communication BU, MediaTek Inc., Taiwan, R.O.C.
Jen-Wei Hsieh , National Taiwan University of Science and Technology, R.O.C.
Yuan-Hao Chang , National Taiwan University, R.O.C.
Tei-Wei Kuo , National Taiwan University, R.O.C.
pp. 405-410

Energy efficient multiprocessor task scheduling under input-dependent variation (PDF)

Jason Cong , Department of Computer Science, University of California, Los Angeles, 90095, USA
Karthik Gururaj , Department of Computer Science, University of California, Los Angeles, 90095, USA
pp. 411-416

Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling (PDF)

Jungsoo Kim , Dept. of EECS at KAIST, Korea
Sungjoo Yoo , Dept. of EE at POSTECH, Korea
Chong-Min Kyung , Dept. of EECS at KAIST, Korea
pp. 417-422

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration (PDF)

Andrew B. Kahng , CSE Department, University of California, San Diego, La Jolla, USA
Bin Li , EE Department, Princeton University, NJ, USA
Li-Shiuan Peh , EE Department, Princeton University, NJ, USA
Kambiz Samadi , ECE Department, University of California, San Diego, La Jolla, USA
pp. 423-428

Nano-electronics challenge chip designers meet real nano-electronics in 2010s? (PDF)

Shinobu Fujita , Toshiba Corporation, Corporate R&D Center, Kawasaki, Japan
pp. 431-432

MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues (PDF)

Shoun Matsunaga , Laboratory for Brainware Systems, Research Institute of Electrical Communication (RIEC), Tohoku University, Sendai, Japan
Jun Hayakawa , Hitachi Advanced Research Laboratory, Tokyo, Japan
Shoji Ikeda , Laboratory for Nanoelectronics and Spintronics, RIEC, Tohoku University, Sendai, Japan
Katsuya Miura , Hitachi Advanced Research Laboratory, Tokyo, Japan
Tetsuo Endoh , Center for Interdisciplinary Research, Tohoku University, Sendai, Japan
Hideo Ohno , Laboratory for Nanoelectronics and Spintronics, RIEC, Tohoku University, Sendai, Japan
Takahiro Hanyu , Laboratory for Brainware Systems, Research Institute of Electrical Communication (RIEC), Tohoku University, Sendai, Japan
pp. 433-435

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors (Abstract)

Subhasish Mitra , Department of Electrical Engineering and Department of Computer Science, Stanford University, CA, USA
Jie Zhang , Department of Electrical Engineering and Department of Computer Science, Stanford University, CA, USA
Nishant Patil , Department of Electrical Engineering and Department of Computer Science, Stanford University, CA, USA
Hai Wei , Department of Electrical Engineering and Department of Computer Science, Stanford University, CA, USA
pp. 436-441

Reconfigurable circuit design with nanomaterials (PDF)

Chen Dong , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Scott Chilstedt , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Deming Chen , Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
pp. 442-447

An architecture for secure software defined radio (PDF)

Chunxiao Li , Department of EE, Princeton University, USA
Anand Raghunathan , School of ECE, Purdue University, USA
Niraj K. Jha , Department of EE, Princeton University, USA
pp. 448-453

Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage (PDF)

Xu Guo , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
Patrick Schaumont , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
pp. 454-459

Hardware aging-based software metering (PDF)

Foad Dabiri , Computer Science Department, University of California Los Angeles, USA
Miodrag Potkonjak , Computer Science Department, University of California Los Angeles, USA
pp. 460-465

On-chip communication architecture exploration for processor-pool-based MPSoC (PDF)

Young-Pyo Joo , School of EECS, Seoul National University, Korea
Sungchan Kim , School of EECS, Seoul National University, Korea
Soonhoi Ha , School of EECS, Seoul National University, Korea
pp. 466-471

Combined system synthesis and communication architecture exploration for MPSoCs (PDF)

Martin Lukasiewycz , University of Erlangen-Nuremberg, Germany
Martin Streubuhr , University of Erlangen-Nuremberg, Germany
Michael Glass , University of Erlangen-Nuremberg, Germany
Christian Haubelt , University of Erlangen-Nuremberg, Germany
Jurgen Teich , University of Erlangen-Nuremberg, Germany
pp. 472-477

UMTS MPSoC design evaluation using a system level design framework (Abstract)

Douglas Densmore , University of California, Berkeley, USA
Alena Simalatsar , University of Trento, Italy
Abhijit Davare , Intel Corporation, USA
Roberto Passerone , University of Trento, Italy
Alberto Sangiovanni-Vincentelli , University of California, Berkeley, USA
pp. 478-483

Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips (PDF)

Mikael Vayrynen , Department of Computer Science, Linköping University, Sweden
Virendra Singh , Supercomputer Education and Research Centre, Indian Institute of Science, India
Erik Larsson , Department of Computer Science, Linköping University, Sweden
pp. 484-489

Improving yield and reliability of chip multiprocessors (Abstract)

Abhisek Pan , University Of Massachusetts, Amherst, USA
Omer Khan , University Of Massachusetts, Amherst, USA
Sandip Kundu , University Of Massachusetts, Amherst, USA
pp. 490-495

A unified online Fault Detection scheme via checking of Stability Violation (PDF)

Guihai Yan , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Yinhe Han , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 100190
pp. 496-501

Statistical fault injection: Quantified error and confidence (Abstract)

R. Leveugle , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - France
A. Calvez , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - France
P. Maistri , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - France
P. Vanhauwaert , TIMA Laboratory (Grenoble INP, UJF, CNRS), 46 Avenue Félix Viallet - 38031 Cedex - France
pp. 502-506

KAST: K-associative sector translation for NAND flash memory in real-time systems (PDF)

Hyunjin Cho , School of ICE, Sungkyunkwan University, Suwon, Korea
Dongkun Shin , School of ICE, Sungkyunkwan University, Suwon, Korea
Young Ik Eom , School of ICE, Sungkyunkwan University, Suwon, Korea
pp. 507-512

White box performance analysis considering static non-preemptive software scheduling (PDF)

Alexander Viehl , FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany
Michael Pressler , FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany
Oliver Bringmann , FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany
Wolfgang Rosenstiel , FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany
pp. 513-518

Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systems (PDF)

Frank Konig , Carl von Ossietzky University Oldenburg, Germany
Dave Boers , Carl von Ossietzky University Oldenburg, Germany
Frank Slomka , Department of Embedded Systems/Real-Time Systems, Faculty of Engineering Science and Computer Sciences, Ulm University, 89069, Germany
Ulrich Margull , 1 mal 1 Software GmbH, Maxstraße 31, D-90762 Fürth, Germany
Michael Niemetz , Continental Automotive GmbH, P.O. Box 100943, D-93009 Regensburg, Germany
Gerhard Wirrer , Continental Automotive GmbH, P.O. Box 100943, D-93009 Regensburg, Germany
pp. 519-523

Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources (PDF)

Mircea Negrean , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, D-38106 Germany
Simon Schliecker , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, D-38106 Germany
Rolf Ernst , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, D-38106 Germany
pp. 524-529

Light NUCA: A proposal for bridging the inter-cache latency gap (PDF)

Dario Suarez , gaZ-DIIS-I3A, Universidad de Zaragoza, Spain
Teresa Monreal , gaZ-DIIS-I3A, Universidad de Zaragoza, Spain
Fernando Vallejo , Computer Architecture Group, Universidad de Cantabria, Spain
Ramon Beivide , Computer Architecture Group, Universidad de Cantabria, Spain
Victor Vinals , gaZ-DIIS-I3A, Universidad de Zaragoza, Spain
pp. 530-535

ReSim, a trace-driven, reconfigurable ILP processor simulator (Abstract)

Sotiria Fytraki , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
Dionisios Pnevmatikatos , Department of Electronic and Computer Engineering, Technical University of Crete, Chania, GR 73100, Greece
pp. 536-541

Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration (PDF)

Giovanni Ansaloni , Faculty of Informatics, University of Lugano (USI), Switzerland
Paolo Bonzini , Faculty of Informatics, University of Lugano (USI), Switzerland
Laura Pozzi , Faculty of Informatics, University of Lugano (USI), Switzerland
pp. 542-547

Algorithms for the automatic extension of an instruction-set (Abstract)

Carlo Galuzzi , Computer Engineering, Delft University of Technology, The Netherlands
Dimitris Theodoropoulos , Computer Engineering, Delft University of Technology, The Netherlands
Roel Meeuws , Computer Engineering, Delft University of Technology, The Netherlands
Koen Bertels , Computer Engineering, Delft University of Technology, The Netherlands
pp. 548-553

Dimensioning heterogeneous MPSoCs via parallelism analysis (PDF)

Bastian Ristau , TU Dresden, Vodafone Chair Mobile Communications Systems, 01062, Germany
Torsten Limberg , TU Dresden, Vodafone Chair Mobile Communications Systems, 01062, Germany
Oliver Arnold , TU Dresden, Vodafone Chair Mobile Communications Systems, 01062, Germany
Gerhard Fettweis , TU Dresden, Vodafone Chair Mobile Communications Systems, 01062, Germany
pp. 554-557

MPSoCs run-time monitoring through Networks-on-Chip (Abstract)

Leandro Fiorin , ALaRI, Faculty of Informatics, University of Lugano, Switzerland
Gianluca Palermo , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
Cristina Silvano , Politecnico di Milano, Dipartimento di Elettronica e Informazione, Italy
pp. 558-561

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints (PDF)

D. Ludovici , Computer Engineering Lab., Delft University of Technology, The Netherlands
F. Gilabert , Dept. of Computer Engineering, Universidad Politecnica de Valencia, Spain
S. Medardoni , ENDIF, University of Ferrara, 44100, Italy
C. Gomez , Dept. of Computer Engineering, Universidad Politecnica de Valencia, Spain
M.E. Gomez , Dept. of Computer Engineering, Universidad Politecnica de Valencia, Spain
P. Lopez , Dept. of Computer Engineering, Universidad Politecnica de Valencia, Spain
G.N. Gaydadjiev , Computer Engineering Lab., Delft University of Technology, The Netherlands
D. Bertozzi , ENDIF, University of Ferrara, 44100, Italy
pp. 562-565

A hybrid packet-circuit switched on-chip network based on SDM (PDF)

Mehdi Modarressi , Computer Engineering Department, Sharif University of Technology, Tehran, Iran
Hamid Sarbazi-Azad , Computer Engineering Department, Sharif University of Technology, Tehran, Iran
Mohammad Arjomand , Computer Engineering Department, Sharif University of Technology, Tehran, Iran
pp. 566-569

SecBus: Operating System controlled hierarchical page-based memory bus protection (PDF)

Lifeng Su , STMicroelectronics, 13106 Rousset, France
Stephan Courcambeck , STMicroelectronics, 13106 Rousset, France
Pierre Guillemin , STMicroelectronics, 13106 Rousset, France
Christian Schwarz , STMicroelectronics, 13106 Rousset, France
Renaud Pacalet , Institut TELECOM ; TELECOM ParisTech ; CNRS LTCI, 06904 Sophia Antipolis, France
pp. 570-573

A link arbitration scheme for quality of service in a latency-optimized network-on-chip (Abstract)

Jonas Diemer , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, Germany
Rolf Ernst , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, Germany
pp. 574-577

Flow regulation for on-chip communication (PDF)

Zhonghai Lu , Royal Institute of Technology (KTH), Sweden
Mikael Millberg , Royal Institute of Technology (KTH), Sweden
Axel Jantsch , Royal Institute of Technology (KTH), Sweden
Alistair Bruce , ARM, France
Pieter van der Wolf , NXP Semiconductors Research, UK
Tomas Henriksson , NXP Semiconductors Research, UK
pp. 578-581

Customizing IP cores for system-on-chip designs using extensive external don't-cares (PDF)

Kai-hui Chang , EECS Department, University of Michigan, Ann Arbor, USA
Valeria Bertacco , EECS Department, University of Michigan, Ann Arbor, USA
Igor L. Markov , EECS Department, University of Michigan, Ann Arbor, USA
pp. 582-585

Extending IP-XACT to support an MDE based approach for SoC design (PDF)

Amin El Mrabti , TIMA Laboratory, 46 Ave Felix Viallet, 38031 Grenoble CEDEX, FRANCE
Frederic Petrot , TIMA Laboratory, 46 Ave Felix Viallet, 38031 Grenoble CEDEX, FRANCE
Aimen Bouchhima , TIMA Laboratory, 46 Ave Felix Viallet, 38031 Grenoble CEDEX, FRANCE
pp. 586-589

Overcoming limitations of the SystemC data introspection (PDF)

Christian Genz , Institute of Computer Science, University of Bremen, 28359, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 590-593

Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage (PDF)

Power Reduction , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030, USA
Hao Xu , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030, USA
Ranga Vemuri , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030, USA
Wen-Ben Jone , Department of Electrical and Computer Engineering, University of Cincinnati, Ohio 45221-0030, USA
pp. 594-597

A power-efficient migration mechanism for D-NUCA caches (PDF)

A. Bardine , Dipartimento di Ingegneria dell'Informazione, Università di Pisa, Via Diotisalvi 2, 56126, Italy
M. Comparetti , Dipartimento di Ingegneria dell'Informazione, Università di Pisa, Via Diotisalvi 2, 56126, Italy
P. Foglia , Dipartimento di Ingegneria dell'Informazione, Università di Pisa, Via Diotisalvi 2, 56126, Italy
G. Gabrielli , Dipartimento di Ingegneria dell'Informazione, Università di Pisa, Via Diotisalvi 2, 56126, Italy
C. A. Prete , Dipartimento di Ingegneria dell'Informazione, Università di Pisa, Via Diotisalvi 2, 56126, Italy
pp. 598-601

System-level process variability analysis and mitigation for 3D MPSoCs (PDF)

Siddharth Garg , Carnegie Mellon University, USA
Diana Marculescu , Carnegie Mellon University, USA
pp. 604-609

Co-design of signal, power, and thermal distribution networks for 3D ICs (PDF)

Young-Joon Lee , Electrical And Computer Engineering, Georgia Institute of Technology, USA
Yoon Jo Kim , Mechanical Engineering, Georgia Institute of Technology, USA
Gang Huang , Intel Corporation, USA
Muhannad Bakir , Electrical And Computer Engineering, Georgia Institute of Technology, USA
Yogendra Joshi , Mechanical Engineering, Georgia Institute of Technology, USA
Andrei Fedorov , Mechanical Engineering, Georgia Institute of Technology, USA
Sung Kyu Lim , Electrical And Computer Engineering, Georgia Institute of Technology, USA
pp. 610-615

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis (Abstract)

Shashikanth Bobba , LSI-EPFL, Lausanne (Switzerland)
Jie Zhang , Stanford University, (USA)
Antonio Pullini , LSI-EPFL, Lausanne (Switzerland)
David Atienza , ESL-EPFL, Lausanne (Switzerland)
Giovanni De Micheli , LSI-EPFL, Lausanne (Switzerland)
pp. 616-621

Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis (Abstract)

M. Haykel Ben Jamaa , Swiss Federal Institute of Technology, Lausanne, Switzerland
Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, USA
Giovanni De Micheli , Swiss Federal Institute of Technology, Lausanne, Switzerland
pp. 622-627

Enhancing correlation electromagnetic attack using planar near-field cartography (PDF)

Denis Real , CELAR - IETR, 35170 Bruz, France
Frederic Valette , CELAR, 35170 Bruz, France
Mhamed Drissi , IETR, 35043 Rennes, France
pp. 628-633

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA (PDF)

Victor Lomne , LIRMM, UMR 5506, University Montpellier 2, CNRS, 161, rue Ada, 34392, France
Philippe Maurine , LIRMM, UMR 5506, University Montpellier 2, CNRS, 161, rue Ada, 34392, France
Lionel Torres , LIRMM, UMR 5506, University Montpellier 2, CNRS, 161, rue Ada, 34392, France
Michel Robert , LIRMM, UMR 5506, University Montpellier 2, CNRS, 161, rue Ada, 34392, France
Rafael Soares , Pontifícia Universidade, Católica do Rio Grande do Sul, Faculdade de Informática, FACIN, PUCRS, Av. Ipiranga, 6681, 90619-900 Porto Allegre, Brazil
Ney Calazans , Pontifícia Universidade, Católica do Rio Grande do Sul, Faculdade de Informática, FACIN, PUCRS, Av. Ipiranga, 6681, 90619-900 Porto Allegre, Brazil
pp. 634-639

Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints (Abstract)

Laurent Sauvage , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
Sylvain Guilley , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
Jean-Luc Danger , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
Yves Mathieu , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
Maxime Nassar , Institut TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), Dèpartement COMELEC, 46 rue Barrault, 75 634 Cedex 13, FRANCE
pp. 640-645

Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT (PDF)

L. Henzen , Integrated Systems Laboratory, ETH Zurich, Switzerland
F. Carbognani , Integrated Systems Laboratory, ETH Zurich, Switzerland
N. Felber , Integrated Systems Laboratory, ETH Zurich, Switzerland
W. Fichtner , Integrated Systems Laboratory, ETH Zurich, Switzerland
pp. 646-651

Architectural support for low overhead detection of memory violations (Abstract)

Saugata Ghose , State University of New York, Binghamton, 13902, USA
Latoya Gilgeous , State University of New York, Binghamton, 13902, USA
Polina Dudnik , State University of New York, Binghamton, 13902, USA
Aneesh Aggarwal , State University of New York, Binghamton, 13902, USA
Corey Waxman , State University of New York, Binghamton, 13902, USA
pp. 652-657

Caspar: Hardware patching for multicore processors (PDF)

Ilya Wagner , University of Michigan, Ann Arbor, 48109, USA
Valeria Bertacco , University of Michigan, Ann Arbor, 48109, USA
pp. 658-663

A new speculative addition architecture suitable for two's complement operations (PDF)

Alessandro Cilardo , Università degli Studi di Napoli Federico II, Dipartimento di Informatica e Sistemistica, Via Claudio 21, 80125, Italy
pp. 664-669

Limiting the number of dirty cache lines (Abstract)

Pepijn de Langen , Computer Engineering Laboratory, Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, Mekelweg 4, 2628 CD, The Netherlands
Ben Juurlink , Computer Engineering Laboratory, Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, Mekelweg 4, 2628 CD, The Netherlands
pp. 670-675

Contactless testing: Possibility or pipe-dream? (PDF)

Erik Jan Marinissen , IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Dae Young Lee , Adv. Computer Architecture Lab., University of Michigan, Ann Arbor, 48109, United States of America
John P. Hayes , Adv. Computer Architecture Lab., University of Michigan, Ann Arbor, 48109, United States of America
Chris Sellathamby , Scanimetrics, 10230 Jasper Avenue, Edmonton, Alberta, Canada T5J 4P6
Brian Moore , Scanimetrics, 10230 Jasper Avenue, Edmonton, Alberta, Canada T5J 4P6
Steven Slupsky , Scanimetrics, 10230 Jasper Avenue, Edmonton, Alberta, Canada T5J 4P6
Laurence Pujol , Beamind 21, rue de la Tuilerie, 38170 Seyssinet Pariset, France
pp. 676-681

Analysis and optimization of fault-tolerant embedded systems with hardened processors (Abstract)

Viacheslav Izosimov , Dept. of Computer and Inform. Science, Linköping University, SE-581 83, Sweden
Ilia Polian , Institute for Computer Science, Albert-Ludwigs-University of Freiburg, D-79110 Freiburg im Breisgau, Germany
Paul Pop , Dept. of Informatics and Math. Modelling, Technical University of Denmark, DK-2800 Kongens Lyngby, Denmark
Petru Eles , Dept. of Computer and Inform. Science, Linköping University, SE-581 83, Sweden
Zebo Peng , Dept. of Computer and Inform. Science, Linköping University, SE-581 83, Sweden
pp. 682-687

On bounding response times under software transactional memory in distributed multiprocessor real-time systems (PDF)

Sherif F. Fahmy , ECE Dept., Virginia Tech, Blacksburg, 24061, USA
Binoy Ravindran , ECE Dept., Virginia Tech, Blacksburg, 24061, USA
E.D. Jensen , The MITRE Corporation, Bedford, MA 01730, USA
pp. 688-693

An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems (PDF)

Chuan-Yue Yang , Department of Computer Science and Information Engineering, National Taiwan University, Taiwan
Jian-Jia Chen , Computer Engineering and Networks Laboratory (TIK), ETH Zürich, Switzerland
Tei-Wei Kuo , Department of Computer Science and Information Engineering, National Taiwan University, Taiwan
Lothar Thiele , Computer Engineering and Networks Laboratory (TIK), ETH Zürich, Switzerland
pp. 694-699

A graph grammar based approach to automated multi-objective analog circuit design (PDF)

Angan Das , Department of Electrical and Computer Engineering, University of Cincinnati, OH 45221-0030, USA
Ranga Vemuri , Department of Electrical and Computer Engineering, University of Cincinnati, OH 45221-0030, USA
pp. 700-705

Massively multi-topology sizing of analog integrated circuits (Abstract)

Pieter Palmers , K.U.Leuven - Department of Electrical Engineering - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium)
Trent McConnaghy , K.U.Leuven - Department of Electrical Engineering - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium)
Michiel Steyaert , K.U.Leuven - Department of Electrical Engineering - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium)
Georges Gielen , K.U.Leuven - Department of Electrical Engineering - ESAT/MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium)
pp. 706-711

Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits (PDF)

Sawal Ali , Electronics System Devices Group, School of Electronics and Computer Science, University of Southampton, UK
Li Ke , Electronics System Devices Group, School of Electronics and Computer Science, University of Southampton, UK
Reuben Wilcock , Electronics System Devices Group, School of Electronics and Computer Science, University of Southampton, UK
Peter Wilson , Electronics System Devices Group, School of Electronics and Computer Science, University of Southampton, UK
pp. 712-717

Computation of IP3 using single-tone moments analysis (Abstract)

Dani Tannir , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada, H3A 2A7
Roni Khazaka , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada, H3A 2A7
pp. 718-723

Formal approaches to analog circuit verification (PDF)

Erich Barke , Institute of Microelectronic Systems, Leibniz Universitaet Hannover, Germany
Darius Grabowski , Institute of Microelectronic Systems, Leibniz Universitaet Hannover, Germany
Helmut Graeb , Institute for EDA, Technische Universitaet Muenchen, Germany
Lars Hedrich , Institute of Computer Science, Goethe University of Frankfurt/Main, Germany
Stefan Heinen , Chair of Integrated Analog Circuits, RWTH Aachen University, Germany
Ralf Popp , edacentrum GmbH, Germany
Sebastian Steinhorst , Institute of Computer Science, Goethe University of Frankfurt/Main, Germany
Yifan Wang , Chair of Integrated Analog Circuits, RWTH Aachen University, Germany
pp. 724-729

Panel session - ESL methodology for SoC (PDF)

L. Toda , Mentor Graphics, US
W. Rhines , Mentor Graphics, US
pp. 730

An overview of non-volatile memory technology and the implication for tools and architectures (PDF)

Hai Li , Alternative Technology Group, Seagate Technology LLC, Bloomington, MN, USA
Yiran Chen , Alternative Technology Group, Seagate Technology LLC, Bloomington, MN, USA
pp. 731-736

Power and performance of read-write aware Hybrid Caches with non-volatile memories (PDF)

Xiaoxia Wu , IBM Austin Research Laboratory, USA
Jian Li , IBM Austin Research Laboratory, USA
Lixin Zhang , IBM Austin Research Laboratory, USA
Evan Speight , IBM Austin Research Laboratory, USA
Yuan Xie , Computer Science and Engineering Department, The Pennsylvania State University, University Park, 16802, USA
pp. 737-742

Using non-volatile memory to save energy in servers (Abstract)

David Roberts , University of Michigan, Department of CSE, Advanced Computer Architecture Lab, USA
Taeho Kgil , Intel Corporation, USA
Trevor Mudge , University of Michigan, Department of CSE, Advanced Computer Architecture Lab, USA
pp. 743-748

aEqualized: A novel routing algorithm for the Spidergon Network On Chip (PDF)

Nicola Concer , Dipartimento di Scienze dell'Informazione, Université di Bologna, Italy
Salvatore Iamundo , Dipartimento di Scienze dell'Informazione, Université di Bologna, Italy
Luciano Bononi , Dipartimento di Scienze dell'Informazione, Université di Bologna, Italy
pp. 749-754

Group-caching for NoC based multicore cache coherent systems (PDF)

Wang Zuo , High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China
Shi Feng , High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China
Zuo Qi , High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China
Ji Weixing , High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China
Li Jiaxin , High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China
Deng Ning , High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China
Xue Licheng , High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China
Tan Yuan , High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China
Qiao Baojun , High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China
pp. 755-760

A monitor interconnect and support subsystem for multicore processors (PDF)

Sailaja Madduri , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, United States
Ramakrishna Vadlamani , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, United States
Wayne Burleson , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, United States
Russell Tessier , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, United States
pp. 761-766

A real-time application design methodology for MPSoCs (Abstract)

Giovanni Beltrame , European Space Agency, Noordwijk, The Netherlands
Luca Fossati , Politecnico di Milano, Italy
Donatella Sciuto , Politecnico di Milano, Italy
pp. 767-772

Adaptive prefetching for shared cache based chip multiprocessors (Abstract)

Mahmut Kandemir , Computer Science and Engineering Department, Pennsylvania State University, University Park, 16802, USA
Yuanrui Zhang , Computer Science and Engineering Department, Pennsylvania State University, University Park, 16802, USA
Ozcan Ozturk , Computer Engineering Department, Bilkent University, Ankara, Turkey
pp. 773-778

CUFFS: An instruction count based architectural framework for security of MPSoCs (Abstract)

Krutartha Patel , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Sri Parameswaran , School of Computer Science and Engineering, University of New South Wales, Sydney, Australia
Roshan G. Ragel , Department of Computer Engineering, University of Peradeniya, Sri Lanka
pp. 779-784

Design as you see FIT: System-level soft error analysis of sequential circuits (PDF)

Daniel Holcomb , EECS Department, UC Berkeley, USA
Wenchao Li , EECS Department, UC Berkeley, USA
Sanjit A. Seshia , EECS Department, UC Berkeley, USA
pp. 785-790

Detecting errors using multi-cycle invariance information (Abstract)

N. Alves , Division of Engineering, Brown University, Providence, RI 02906, USA
K. Nepal , Electrical Engineering Department, Bucknell University, Lewisburg, PA 17837, USA
J. Dworak , Division of Engineering, Brown University, Providence, RI 02906, USA
R. I. Bahar , Division of Engineering, Brown University, Providence, RI 02906, USA
pp. 791-796

A novel approach to entirely integrate Virtual Test into test development flow (PDF)

Ping Lu , Chair of Computer Aided Circuit Design, Friedrich-Alexander-University Erlangen-Nuremberg, Germany
Daniel Glaser , Chair of Computer Aided Circuit Design, Friedrich-Alexander-University Erlangen-Nuremberg, Germany
Gurkan Uygur , Chair of Computer Aided Circuit Design, Friedrich-Alexander-University Erlangen-Nuremberg, Germany
Klaus Helmreich , Chair of Computer Aided Circuit Design, Friedrich-Alexander-University Erlangen-Nuremberg, Germany
pp. 797-802

Robust non-preemptive hard real-time scheduling for clustered multicore platforms (Abstract)

Michele Lombardi , DEIS - Università di Bologna, Italy
Michela Milano , DEIS - Università di Bologna, Italy
Luca Benini , DEIS - Università di Bologna, Italy
pp. 803-808

Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy (Abstract)

Andrea Marongiu , University of Bologna, Via Risorgimento, 2, 40136 Italy
Luca Benini , University of Bologna, Via Risorgimento, 2, 40136 Italy
pp. 809-814

Using randomization to cope with circuit uncertainty (Abstract)

Hamid Safizadeh , School of Computer Science, Institute for Research in Fundamental Sciences, Tehran, Iran
Mohammad Tahghighi , ECE Dept, Isfahan University of Technology, Iran
Ehsan K. Ardestani , CE Dept, University of California Santa Cruz, Santa Cruz, 95064, USA
Gholamhossein Tavasoli , ECE Dept, Isfahan University of Technology, Iran
Kia Bazargan , ECE Dept, Isfahan University of Technology, Iran
pp. 815-820

Process variation aware thread mapping for Chip Multiprocessors (Abstract)

S. Hong , Department of Computer Science and Enginneering, The Pennsylvania State University, USA
S.H.K. Narayanan , Department of Computer Science and Enginneering, The Pennsylvania State University, USA
M. Kandemir , Department of Computer Science and Enginneering, The Pennsylvania State University, USA
O. Ozturk , Department of Computer Engineering, Bilkent University, Turkey
pp. 821-826

Gate sizing for large cell-based designs (PDF)

Stephan Held , Research Institute for Discrete Mathematics, University of Bonn, Lennéstr. 2, 53113, Germany
pp. 827-832

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network (PDF)

Naser MohammadZadeh , Department of Computer Engineering, Amirkabir University of Technology, Tehran, Iran
Minoo Mirsaeedi , Department of Computer Engineering, Amirkabir University of Technology, Tehran, Iran
Ali Jahanian , Department of Electrical and Computer Engineering, Shahid Beheshti University, G. C., Tehran, Iran
Morteza Saheb Zamani , Department of Computer Engineering, Amirkabir University of Technology, Tehran, Iran
pp. 833-838

Decoupling capacitor planning with analytical delay model on RLC power grid (PDF)

Ye Tao , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
Sung Kyu Lim , School of Electrical and Computer Engineering, Georgia Institute of Technology, USA
pp. 839-844

Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design (PDF)

Chao-Hung Lu , Department of Electrical Engineering, National Central University, Taoyuan, Taiwan
Hung-Ming Chen , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
Chien-Nan Jimmy Liu , Department of Electrical Engineering, National Central University, Taoyuan, Taiwan
Wen-Yu Shih , Department of Electrical Engineering, National Central University, Taoyuan, Taiwan
pp. 845-850

Learning early-stage platform dimensioning from late-stage timing verification (PDF)

Kai Richter , Symtavision GmbH, Braunschweig, Germany
Marek Jersak , Symtavision GmbH, Braunschweig, Germany
Rolf Ernst , Institut für Datentechnik und Kommunikationsnetze, Technische Universität Braunschweig, Germany
pp. 851-857

The influence of real-time constraints on the design of FlexRay-based systems (Abstract)

Stephan Reichelt , Audi Electronics Venture GmbH, Germany
Oliver Scheickl , BMW Car IT GmbH, Germany
Gokhan Tabanoglu , Volkswagen AG, Germany
pp. 858-863

Time and memory tradeoffs in the implementation of AUTOSAR components (Abstract)

Alberto Ferrari , Parades, Via San Pantaleo 66, Roma, Italy
Marco Di Natale , ReTiS Lab., Scuola Superiore S. Anna, Via Moruzzi 1, Pisa, Italy
Giacomo Gentile , Magneti Marelli S.p.A., Via Timavo 33, Bologna, Italy
Giovanni Reggiani , Magneti Marelli S.p.A., Via Timavo 33, Bologna, Italy
Paolo Gai , Evidence Srl, Via Carducci 64, Ghezzano (Pi), Italy
pp. 864-869

Systolic like soft-detection architecture for 4×4 64-QAM MIMO system (PDF)

Pankaj Bhagawat , Dept. of E.C.E, Texas A&M University, College-Station, TX-77840, USA
Rajballav Dash , Dept. of E.C.E, Texas A&M University, College-Station, TX-77840, USA
Gwan Choi , Dept. of E.C.E, Texas A&M University, College-Station, TX-77840, USA
pp. 870-873

Co-simulation based platform for wireless protocols design explorations (PDF)

Alain Fourmigue , Ecole Polytechnique de Montréal, Canada
Bruno Girodias , Ecole Polytechnique de Montréal, Canada
Gabriela Nicolescu , Ecole Polytechnique de Montréal, Canada
El Mostapha Aboulhamid , Ecole Polytechnique de Montréal, Canada
pp. 874-877

How to speed-up your NLFSR-based stream cipher (PDF)

Elena Dubrova , Royal Institute of Technology (KTH), Stockholm, Sweden
pp. 878-881

A high performance reconfigurable Motion Estimation hardware architecture (PDF)

O. Tasdizen , Faculty of Engineering and Natural Sciences, Sabanci University, 34956 Tuzla, Istanbul, Turkey
H. Kukner , Faculty of Engineering and Natural Sciences, Sabanci University, 34956 Tuzla, Istanbul, Turkey
A. Akin , Faculty of Engineering and Natural Sciences, Sabanci University, 34956 Tuzla, Istanbul, Turkey
I. Hamzaoglu , Faculty of Engineering and Natural Sciences, Sabanci University, 34956 Tuzla, Istanbul, Turkey
pp. 882-885

Partition-based exploration for reconfigurable JPEG designs (PDF)

Philip G. Potter , Imperial College, London, UK
Wayne Luk , Imperial College, London, UK
Peter Cheung , Imperial College, London, UK
pp. 886-889

Automated synthesis of streaming C applications to process networks in hardware (PDF)

Sven van Haastregt , LIACS, Leiden University, Niels Bohrweg 1, 2333 CA, The Netherlands
Bart Kienhuis , LIACS, Leiden University, Niels Bohrweg 1, 2333 CA, The Netherlands
pp. 890-893

Distributed sensor for steering wheel rip force measurement in driver fatigue detection (PDF)

Federico Baronti , Dipartimento di Ingeneria dell'Informazione: Elettronica, Informatica, Telecomunicazioni, Università di Pisa, Via Caruso, 16, 56122, Italy
Francesco Lenzi , Dipartimento di Ingeneria dell'Informazione: Elettronica, Informatica, Telecomunicazioni, Università di Pisa, Via Caruso, 16, 56122, Italy
Roberto Roncella , Dipartimento di Ingeneria dell'Informazione: Elettronica, Informatica, Telecomunicazioni, Università di Pisa, Via Caruso, 16, 56122, Italy
Roberto Saletti , Dipartimento di Ingeneria dell'Informazione: Elettronica, Informatica, Telecomunicazioni, Università di Pisa, Via Caruso, 16, 56122, Italy
pp. 894-897

Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy (PDF)

Saturnino Garcia , Department of Computer Science and Engineering, University of California, San Diego, 9500 Gilman Drive, La Jolla, 92037, USA
Alex Orailoglu , Department of Computer Science and Engineering, University of California, San Diego, 9500 Gilman Drive, La Jolla, 92037, USA
pp. 898-901

Machine learning-based volume diagnosis (PDF)

Seongmoon Wang , NEC Labs. America, Princeton, New Jersey, USA
Wenlong Wei , NEC Labs. America, Princeton, New Jersey, USA
pp. 902-905

Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip (PDF)

Francesco Paterna , DEIS - University of Bologna, V.le Risorgimento 2, Italy
Luca Benini , DEIS - University of Bologna, V.le Risorgimento 2, Italy
Francesco Papariello , ST Microelectronics, Agrate, Italy
Giuseppe Desoli , ST Microelectronics, Agrate, Italy
Andrea Acquaviva , DAUIN - Politecnico di Torino, Corso Duca Degli Abruzzi 24, 10129, Italy
Mauro Olivieri , DIE - Universit ¿La Sapienza¿ di Roma, Italy
pp. 906-909

Panel session - Architectures and integration for programmable SoC's (PDF)

G. Schreiner , The MathWorks GmbH, Germany
E. Schubert , ESIC GmbH, Germany
pp. 910

Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling (PDF)

Avesta Sasan , University of California Irvine, USA
Houman Homayoun , University of California Irvine, USA
Ahmed Eltawil , University of California Irvine, USA
Fadi Kurdahi , University of California Irvine, USA
pp. 911-916

Single ended 6T SRAM with isolated read-port for low-power embedded systems (PDF)

Jawar Singh , Department of Computer Science, University of Bristol, UK
Dhiraj K. Pradhan , Department of Computer Science, University of Bristol, UK
Simon Hollis , Department of Computer Science, University of Bristol, UK
Saraju P. Mohanty , Department of Computer Science and Engineering, University of North Texas, USA
J. Mathew , Department of Computer Science, University of Bristol, UK
pp. 917-922

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications (PDF)

Marco Facchini , IMEC - Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001 Heverlee, Belgium
Trevor Carlson , IMEC - Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001 Heverlee, Belgium
Anselme Vignon , ESAT-MICAS Katholieke University Leuven, Kasteelpark Aremberg 10, B-3001 Heverlee, Belgium
Martin Palkovic , IMEC - Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001 Heverlee, Belgium
Francky Catthoor , IMEC - Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001 Heverlee, Belgium
Wim Dehaene , ESAT-MICAS Katholieke University Leuven, Kasteelpark Aremberg 10, B-3001 Heverlee, Belgium
Luca Benini , DEIS - Università di Bologna, Viale Risorgimento 2, 40136, Italy
Paul Marchal , IMEC - Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001 Heverlee, Belgium
pp. 923-928

A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. (PDF)

Anselme Vignon , K.U. Leuven, ESAT - MICAS Laboratory, Kasteelpark Arenberg 10, Belgium
Stefan Cosemans , K.U. Leuven, ESAT - MICAS Laboratory, Kasteelpark Arenberg 10, Belgium
Wim Dehaene , K.U. Leuven, ESAT - MICAS Laboratory, Kasteelpark Arenberg 10, Belgium
Pol Marchal , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Marco Facchini , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
pp. 929-933

A case for multi-channel memories in video recording (PDF)

Eero Aho , Nokia Research Center, Tampere, Finland
Jari Nikara , Nokia Research Center, Tampere, Finland
Petri A. Tuominen , Nokia Research Center, Tampere, Finland
Kimmo Kuusilinna , Nokia Research Center, Tampere, Finland
pp. 934-939

High level H.264/AVC video encoder parallelization for multiprocessor implementation (PDF)

Hajer Krichene Zrida , Department of Electrical Engineering, CES Laboratory, ENIS Institute, Sfax University, Tunisia
Abderrazek Jemai , LIP2 Laboratory, Faculty of Science of Tunis, Tunisia
Ahmed C. Ammari , Unité de recherche en Matériaux Mesures et Applications (MMA) INSAT, Tunisia
Mohamed Abid , Department of Electrical Engineering, CES Laboratory, ENIS Institute, Sfax University, Tunisia
pp. 940-945

Temperature-aware scheduler based on thermal behavior grouping in multicore systems (PDF)

Inchoon Yeo , Department of Computer Science and Engineering, Texas A&M University, College Station, TX77840, USA
Eun Jung Kim , Department of Computer Science and Engineering, Texas A&M University, College Station, TX77840, USA
pp. 946-951

Hardware/software co-design architecture for thermal management of chip multiprocessors (Abstract)

Omer Khan , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA 01002
Sandip Kundu , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA 01002
pp. 952-957

Cross-architectural design space exploration tool for reconfigurable processors (Abstract)

Lars Bauer , University of Karlsruhe, Chair for Embedded Systems, Germany
Muhammad Shafique , University of Karlsruhe, Chair for Embedded Systems, Germany
Jorg Henkel , University of Karlsruhe, Chair for Embedded Systems, Germany
pp. 958-963

Automatically mapping applications to a self-reconfiguring platform (Abstract)

Karel Bruneel , Ghent University, ELIS Department, Sint-Pietersnieuwstraat 41, 9000 Belgium
Fatma Abouelella , Ghent University, ELIS Department, Sint-Pietersnieuwstraat 41, 9000 Belgium
Dirk Stroobandt , Ghent University, ELIS Department, Sint-Pietersnieuwstraat 41, 9000 Belgium
pp. 964-969

OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems (Abstract)

Andreas Schallenberg , Carl von Ossietzky University, Oldenburg, Germany
Wolfgang Nebel , Carl von Ossietzky University, Oldenburg, Germany
Andreas Herrholz , OFFIS Institute for Information Technology, Oldenburg, Germany
Philipp A. Hartmann , OFFIS Institute for Information Technology, Oldenburg, Germany
Frank Oppenheimer , OFFIS Institute for Information Technology, Oldenburg, Germany
pp. 970-975

Design optimizations to improve placeability of partial reconfiguration modules (PDF)

Markus Koester , Department of Computing, Imperial College London, UK
Wayne Luk , Department of Computing, Imperial College London, UK
Jens Hagemeyer , System and Circuit Technology, University of Paderborn, Germany
Mario Porrmann , System and Circuit Technology, University of Paderborn, Germany
pp. 976-981

Automated data analysis solutions to silicon debug (PDF)

Yu-Shen Yang , Dept. of ECE, University of Toronto, M5S 3G4, Canada
Nicola Nicolici , Dept. of ECE, McMaster University, Hamilton, L8S 4K1, Canada
Andreas Veneris , Dept. of ECE & CS, University of Toronto, M5S 3G4, Canada
pp. 982-987

Efficient and accurate method for intra-gate defect diagnoses in nanometer technology and volume data (PDF)

Aymen Ladhar , STMicroelectronics, Tunisia
Mohamed Masmoudi , Electronics, Micro-technology and Communication Research Group, Tunisia
Laroussi Bouzaida , STMicroelectronics, Tunisia
pp. 988-993

Selection of a fault model for fault diagnosis based on unique responses (Abstract)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
Sudhakar M. Reddy , Electrical & Computer Eng. Dept., University of Iowa, 52242, U.S.A.
pp. 994-999

Improving compressed test pattern generation for multiple scan chain failure diagnosis (PDF)

Xun Tang , Department of Electrical and Computer Engineering, University of Iowa, 52242, USA
Ruifeng Guo , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR 97070, USA
Wu-Tung Cheng , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR 97070, USA
Sudhakar M. Reddy , Department of Electrical and Computer Engineering, University of Iowa, 52242, USA
pp. 1000-1005

A case study in distributed deployment of embedded software for camera networks (PDF)

Francesco Leonardi , Dept. of Computer Science, Columbia University, New York, USA
Alessandro Pinto , United Technologies Research Center, United Technologies, Hartford, CT USA
Luca P. Carloni , Dept. of Computer Science, Columbia University, New York, USA
pp. 1006-1011

pTest: An adaptive testing tool for concurrent software on embedded multicore processors (PDF)

Shou-Wei Chang , Department of Computer Science, National Tsing-Hua University, Hsin-Chu, Taiwan
Kun-Yuan Hsieh , Department of Computer Science, National Tsing-Hua University, Hsin-Chu, Taiwan
Jenq Kuen Lee , Department of Computer Science, National Tsing-Hua University, Hsin-Chu, Taiwan
pp. 1012-1017

A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors (Abstract)

Aryabartta Sahu , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India, 110016
M. Balakrishnan , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India, 110016
Preeti Ranjan Panda , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India, 110016
pp. 1018-1023

Networked embedded system applications design driven by an abstract middleware environment (Abstract)

F. Fummi , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Italy
G. Perbellini , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Italy
Niccolo' Roncolato , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Italy
pp. 1024-1029

Health-care electronics The market, the challenges, the progress (Abstract)

Wolfgang Eberle , IMEC, Bioelectronic Systems Group, Leuven, Belgium
Ashwin S. Mecheri , IMEC, Bioelectronic Systems Group, Leuven, Belgium
Thi Kim Thoa Nguyen , IMEC, Bioelectronic Systems Group, Leuven, Belgium
Georges Gielen , KU Leuven, MICAS, Belgium
Raymond Campagnolo , CEA LETI, MINATEC, Grenoble, France
Alison Burdett , Toumaz Technology Ltd., Oxford, UK
Chris Toumazou , Institute of Biomed. Eng., Imperial College London, UK
Bart Volckaerts , Cochlear Technology Centre, Mechelen, Belgium
pp. 1030-1034

Design and implementation of scalable, transparent threads for multi-core media processor (Abstract)

Takeshi Kodaka , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Shunsuke Sasaki , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Takahiro Tokuyoshi , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Ryuichiro Ohyama , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Nobuhiro Nonogaki , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Koji Kitayama , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Tatsuya Mori , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Yasuyuki Ueda , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Hideho Arakida , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Yuji Okuda , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Toshiki Kizu , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Yoshiro Tsuboi , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
Nobu Matsumoto , Toshiba Corporation, Semiconductor Company, Center for Semiconductor Research and Development, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, Kanagawa, Japan
pp. 1035-1039

High data rate fully flexible SDR modem advanced configurable architecture & development methodology (PDF)

F. Kasperski , THALES Communication, 160 bd de Valmy, 92704 Colombes, FRANCE
O. Pierrelee , THALES Communication, 160 bd de Valmy, 92704 Colombes, FRANCE
F. Dotto , THALES Communication, 160 bd de Valmy, 92704 Colombes, FRANCE
M. Sarlotte , THALES Communication, 160 bd de Valmy, 92704 Colombes, FRANCE
pp. 1040-1044

Cross-coupling in 65nm fully integrated EDGE System On Chip Design and cross-coupling prevention of complex 65nm SoC (PDF)

Pierre-Henri Bonnaud , Mobile Phone Platform, Infineon Technologies, Sophia-Antipolis, France
Grit Sommer , Package Layout, Infineon Technologies AG, 85579 Neubiberg, Germany
pp. 1045-1050

Embedded tutorial - Understanding multicore technologies (PDF)

A. Jerraya , CEA-LETI, France
G. Nicolescu , Polytechnique Montreal, Canada
pp. 1051

Latency criticality aware on-chip communication (PDF)

Zheng Li , Tsinghua National Laboratory for Information Science and Technology, Inst. of Microelectronics, Tsinghua University, Beijing 100084, China
Jie Wu , Tsinghua National Laboratory for Information Science and Technology, Inst. of Microelectronics, Tsinghua University, Beijing 100084, China
Li Shang , Dept. of Electrical and Computer Engineering, University of Colorado, Boulder, 80309, U.S.A.
Robert P. Dick , Dept. of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, U.S.A.
Yihe Sun , Tsinghua National Laboratory for Information Science and Technology, Inst. of Microelectronics, Tsinghua University, Beijing 100084, China
pp. 1052-1057

In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem (PDF)

Woo-Cheol Kwon , Computing Platform, System LSI Division, Semiconductor Business, Samsung Electronics, Korea
Sungjoo Yoo , Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, Korea
Junhyung Um , Computing Platform, System LSI Division, Semiconductor Business, Samsung Electronics, Korea
Seh-Woong Jeong , Computing Platform, System LSI Division, Semiconductor Business, Samsung Electronics, Korea
pp. 1058-1063

An efficent dynamic multicast routing protocol for distributing traffic in NOCs (Abstract)

Masoumeh Ebrahimi , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Masoud Daneshtalab , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Mohammad Hossein Neishaburi , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Siamak Mohammadi , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Ali Afzali-Kusha , Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran
Juha Plosila , Department of Information Technology, University of Turku, Finland
Hannu Tenhunen , Department of Information Technology, University of Turku, Finland
pp. 1064-1069

Priority based forced requeue to reduce worst-case latencies for bursty traffic (Abstract)

Mikael Millberg , ECS - ICT - KTH, Royal Institute of Technology, Sweden
Axel Jantsch , ECS - ICT - KTH, Royal Institute of Technology, Sweden
pp. 1070-1075

Optimizations of an application-level protocol for enhanced dependability in FlexRay (PDF)

Wenchao Li , EECS Department, UC Berkeley, CA, USA
Marco Di Natale , Scuola Superiore S. Anna, Pisa, Italy
Wei Zheng , EECS Department, UC Berkeley, CA, USA
Paolo Giusto , General Motors, Palo Alto, CA, USA
Alberto Sangiovanni-Vincentelli , EECS Department, UC Berkeley, CA, USA
Sanjit A. Seshia , EECS Department, UC Berkeley, CA, USA
pp. 1076-1081

Remote measurement of local oscillator drifts in FlexRay networks (PDF)

Eric Armengaud , Vienna University of Technology, Embedded Computing Systems Group E182-2, Austria
Andreas Steininger , Vienna University of Technology, Embedded Computing Systems Group E182-2, Austria
pp. 1082-1087

CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. (Abstract)

Tobias Ziermann , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Stefan Wildermann , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
pp. 1088-1093

Shock immunity enhancement via resonance damping in gyroscopes for automotive applications (Abstract)

E. Marchetti , Dept. of Information Engineering, University of Pisa, Italy
L. Fanucci , Dept. of Information Engineering, University of Pisa, Italy
A. Rocchi , Sensordynamics AG, Navacchio (PI), Italy
M. De Marinis , Sensordynamics AG, Navacchio (PI), Italy
pp. 1094-1099

Integration of an advanced emergency call subsystem into a car-gateway platform (PDF)

N. Martinez Madrid , Dpto. de Ingeniería Telemática, Universidad Carlos III de Madrid, Leganés, Spain
R. Seepold , Dpto. de Ingeniería Telemática, Universidad Carlos III de Madrid, Leganés, Spain
A. Reina Nieves , Dpto. de Ingeniería Telemática, Universidad Carlos III de Madrid, Leganés, Spain
J. Saez Gomez , Dpto. de Ingeniería Telemática, Universidad Carlos III de Madrid, Leganés, Spain
A. los Santos Aransay , División Automóvil Conectado, Telefónica I+D, Spain
P. Sanz Velasco , División Automóvil Conectado, Telefónica I+D, Spain
C. Rueda Morales , Dpto. de I+D, Deimos Aplicaciones Tecnológicas, Boecillo, Valladolid, Spain
F. Ares , Dpto. de I+D, Deimos Aplicaciones Tecnológicas, Boecillo, Valladolid, Spain
pp. 1100-1105

Finite Precision bit-width allocation using SAT-Modulo Theory (Abstract)

Adam B. Kinsman , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
pp. 1106-1111

HLS-l: High-level synthesis of high performance latch-based circuits (PDF)

Seungwhun Paik , Department of Electrical Engineering, KAIST, Daejeon 305-701, Korea
Insup Shin , Department of Electrical Engineering, KAIST, Daejeon 305-701, Korea
Youngsoo Shin , Department of Electrical Engineering, KAIST, Daejeon 305-701, Korea
pp. 1112-1117

Automatic generation of streaming datapaths for arbitrary fixed permutations (PDF)

Peter A. Milder , Carnegie Mellon University, Electrical and Computer Engineering Department, Pittsburgh, PA, U.S.A.
James C. Hoe , Carnegie Mellon University, Electrical and Computer Engineering Department, Pittsburgh, PA, U.S.A.
Markus Puschel , Carnegie Mellon University, Electrical and Computer Engineering Department, Pittsburgh, PA, U.S.A.
pp. 1118-1123

SEU-aware resource binding for modular redundancy based designs on FPGAs (PDF)

Shahin Golshan , Computer Sciences Department, University of California, Irvine, USA
Eli Bozorgzadeh , Computer Sciences Department, University of California, Irvine, USA
pp. 1124-1129

Generation of compact test sets with high defect coverage (Abstract)

Xrysovalantis Kavousianos , Dept. of Computer Science, University of Ioannina, 45110, Greece
Krishnendu Chakrabarty , Dept. of Electrical & Computer Engineering, Duke University, 27708 Durham, NC, USA
pp. 1130-1135

A scalable method for the generation of small test sets (Abstract)

Santiago Remersaro , Mentor Graphics Corporation, USA
Janusz Rajski , Mentor Graphics Corporation, USA
Sudhakar M. Reddy , The University of Iowa, USA
Irith Pomeranz , Purdue University, USA
pp. 1136-1141

QC-Fill: An X-Fill method for quick-and-cool scan test (PDF)

Chao-Wen Tzeng , EE Dept., National Tsing-Hua University, Taiwan
Shi-Yu Huang , EE Dept., National Tsing-Hua University, Taiwan
pp. 1142-1147

Exploring parallelizations of applications for MPSoC platforms using MPA (PDF)

Rogier Baert , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Erik Brockmeyer , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Sven Wuytack , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Thomas J. Ashby , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
pp. 1148-1153

An MDE methodology for the development of high-integrity real-time systems (PDF)

Silvia Mazzini , Intecs SpA, Pisa, Italy
Stefano Puri , Intecs SpA, Pisa, Italy
Tullio Vardanega , University of Padua, Italy
pp. 1154-1159

Mode-based reconfiguration of critical software component architectures (PDF)

Etienne Borde , THALES Land and Joint Systems 5, avenue Carnot 91883 Massy cedex, France
Gregory Haik , THALES Land and Joint Systems 5, avenue Carnot 91883 Massy cedex, France
Laurent Pautet , TelecomParisTech, 46, rue Barrault 75013, France
pp. 1160-1165

Towards a formal semantics for the AADL behavior annex (PDF)

Zhibin Yang , School of Computer Science and Engineering, Beihang University, Beijing, China
Kai Hu , School of Computer Science and Engineering, Beihang University, Beijing, China
Dianfu Ma , School of Computer Science and Engineering, Beihang University, Beijing, China
Lei Pi , IRIT, CNRS, Université Paul Sabatier, Toulouse, France
pp. 1166-1171

On the efficient reduction of complete EM based parametric models (PDF)

Jorge Fernandez Villena , INESC ID / IST - TU Lisbon. Rua Alves Redol 9, 1000-029, Portugal
Gabriela Ciuprina , LMN, Politehnica University of Bucharest. Spl. Independentei 313, 060042, Romania
Daniel Ioan , LMN, Politehnica University of Bucharest. Spl. Independentei 313, 060042, Romania
Luis Miguel Silveira , INESC ID / IST - TU Lisbon. Rua Alves Redol 9, 1000-029, Portugal
pp. 1172-1177

Efficient compression and handling of current source model library waveforms (PDF)

Safar Hatami , Department of Electrical Engineering, University of Southern California, Los Angeles, USA
Peter Feldmann , IBM T.J. Watson Research Lab, Yorktown Heights, NY, USA
Soroush Abbaspour , IBM Hudson Valley Research Park, Hopewell Junction, NY, USA
Massoud Pedram , Department of Electrical Engineering, University of Southern California, Los Angeles, USA
pp. 1178-1183

New simulation methodology of 3D surface roughness loss for interconnects modeling (PDF)

Quan Chen , Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong
Ngai Wong , Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong
pp. 1184-1189

An efficient decoupling capacitance optimization using piecewise polynomial models (PDF)

Xiaoyi Wang , Department of Computer Science and Technology, TsingHua University, Beijing, China, 100084
Yici Cai , Department of Computer Science and Technology, TsingHua University, Beijing, China, 100084
Sheldon X.-D. Tan , Department of Electrical Engineering, University of California, Riverside, 92521, USA
Xianlong Hong , Department of Computer Science and Technology, TsingHua University, Beijing, China, 100084
Jacob Relles , Department of Electrical Engineering, University of California, Riverside, 92521, USA
pp. 1190-1195

An automated flow for integrating hardware IP into the automotive systems engineering process (Abstract)

Jan-Hendrik Oetjens , Robert Bosch GmbH, AE/EIM3, Postfach 1342, 72703 Reutlingen, Germany
Ralph Gorgen , OFFIS Institute, R&D Division Transportation, Escherweg 2, 26121 Oldenburg, Germany
Joachim Gerlach , Robert Bosch GmbH, AE/EIM3, Postfach 1342, 72703 Reutlingen, Germany
Wolfgang Nebel , Carl v. Ossietzky University Embedded Hardware-/Software-Systems 26111 Oldenburg, Germany
pp. 1196-1201

EMC-aware design on a microcontroller for automotive applications (Abstract)

Patrice Joubert Doriol , STMicroelectronics, Agrate Brianza, 20041 Italy
Yamarita Villavicencio , Politecnico di Torino, 10129 Italy
Cristiano Forzan , STMicroelectronics, Agrate Brianza, 20041 Italy
Mario Rotigni , STMicroelectronics, Agrate Brianza, 20041 Italy
Giovanni Graziosi , STMicroelectronics, Agrate Brianza, 20041 Italy
Davide Pandini , STMicroelectronics, Agrate Brianza, 20041 Italy
pp. 1208-1213

Semiformal verification of temporal properties in automotive hardware dependent software (PDF)

Djones Lettnin , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 - Germany
Pradeep K. Nalla , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 - Germany
Jorg Behrend , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 - Germany
Jurgen Ruf , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 - Germany
Joachim Gerlach , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 - Germany
Thomas Kropf , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 - Germany
Wolfgang Rosenstiel , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 - Germany
Volker Schonknecht , NEC Electronics (Europe) GmbH, Arcadiastrasse 10, 40472 Düsseldorf - Germany
Stephan Reitemeyer , NEC Electronics (Europe) GmbH, Arcadiastrasse 10, 40472 Düsseldorf - Germany
pp. 1214-1217

System-level hardware-based protection of memories against soft-errors (PDF)

Valentin Gherman , CEA, LIST, Laboratoire de Fiabilisation des Systèmes Embarqués, PC 94, Gif-sur-Yvette, F-91191 France
Samuel Evain , CEA, LIST, Laboratoire de Fiabilisation des Systèmes Embarqués, PC 94, Gif-sur-Yvette, F-91191 France
Mickael Cartron , CEA, LIST, Laboratoire de Fiabilisation des Systèmes Embarqués, PC 94, Gif-sur-Yvette, F-91191 France
Nathaniel Seymour , CEA, LIST, Laboratoire de Fiabilisation des Systèmes Embarqués, PC 94, Gif-sur-Yvette, F-91191 France
Yannick Bonhomme , CEA, LIST, Laboratoire de Fiabilisation des Systèmes Embarqués, PC 94, Gif-sur-Yvette, F-91191 France
pp. 1222-1225

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs (Abstract)

F. Abate , Politecnico di Torino, DAUIN - Dipartimento di Automatica e Informatica, Italy
L. Sterpone , Politecnico di Torino, DAUIN - Dipartimento di Automatica e Informatica, Italy
M. Violante , Politecnico di Torino, DAUIN - Dipartimento di Automatica e Informatica, Italy
F. Lima Kastensmidt , Universidade Federal do Rio Grande do Sul, Instituto de Informatica, Porto Alegre, Brasil
pp. 1226-1229

Finite precision processing in wireless applications (Abstract)

David Novo , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Min Li , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Bruno Bougard , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Liesbet Van der Perre , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
Francky Catthoor , IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium
pp. 1230-1233

A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test (PDF)

Wen-Wen Hsieh , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
I-Sheng Lin , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
TingTing Hwang , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
pp. 1234-1237

Efficient reliability simulation of analog ICs including variability and time-varying stress (PDF)

Elie Maricau , ESAT-MICAS KULeuven, Heverlee-Leuven, Belgium 3001
Georges Gielen , ESAT-MICAS KULeuven, Heverlee-Leuven, Belgium 3001
pp. 1238-1241

A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications (PDF)

Fabien Demangel , R-interface, Marseille Innovation BP 20038, 13302 Cedex 03, France
Nicolas Fau , R-interface, Marseille Innovation BP 20038, 13302 Cedex 03, France
Nicolas Drabik , R-interface, Marseille Innovation BP 20038, 13302 Cedex 03, France
Francois Charot , Irisa, Inria, University of Rennes 1, Campus de Beaulieu, 35042 Cedex, France
Christophe Wolinski , Irisa, Inria, University of Rennes 1, Campus de Beaulieu, 35042 Cedex, France
pp. 1242-1245

Property analysis and design understanding (PDF)

Ulrich Kuhne , Institute of Computer Science, University of Bremen, 28359, Germany
Daniel Grosse , Institute of Computer Science, University of Bremen, 28359, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 1246-1249

Test exploration and validation using transaction level models (Abstract)

Michael A. Kochte , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Christian G. Zoellin , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Michael E. Imhof , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Rauf Salimi Khaligh , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Martin Radetzki , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Hans-Joachim Wunderlich , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, 70569, Germany
Stefano Di Carlo , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 TO, Italy
Paolo Prinetto , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 TO, Italy
pp. 1250-1253

Heterogeneous multi-core platform for consumer multimedia applications (PDF)

Peter Kollig , NXP Semiconductors, Southampton, U.K.
Colin Osborne , NXP Semiconductors, Southampton, U.K.
Tomas Henriksson , NXP Semiconductors Research, Eindhoven, The Netherlands
pp. 1254-1259

Multi-core for mobile phones (PDF)

C.H. van Berkel , ST-NXP Wireless, Advanced R&D, High Tech Campus 32, 5656 AE Eindhoven, The Netherlands
pp. 1260-1265

Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks (PDF)

Hengyu Long , TNList, EE Dept., Tsinghua University, Beijing, 100084, China
Yongpan Liu , TNList, EE Dept., Tsinghua University, Beijing, 100084, China
Xiaoguang Fan , TNList, EE Dept., Tsinghua University, Beijing, 100084, China
Robert P. Dick , EECS Dept., University of Michigan, Ann Arbor, 48109, U.S.A.
Huazhong Yang , TNList, EE Dept., Tsinghua University, Beijing, 100084, China
pp. 1267-1272

Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes (Abstract)

Varun Subramanian , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
Michael Gilberti , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
Alex Doboli , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, 11794-2350, USA
pp. 1273-1278

Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability (PDF)

Yexin Zheng , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
Chao Huang , Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, 24061, USA
pp. 1279-1283

Debugging of Toffoli networks (Abstract)

Robert Wille , Institute of Computer Science, University of Bremen, 28359, Germany
Daniel Grosse , Institute of Computer Science, University of Bremen, 28359, Germany
Stefan Frehse , Institute of Computer Science, University of Bremen, 28359, Germany
Gerhard W. Dueck , Faculty of Computer Science, University of New Brunswick, Fredericton, Canada
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 1284-1289

Cross-contamination avoidance for droplet routing in digital microfluidic biochips (PDF)

Yang Zhao , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
pp. 1290-1295

Error correction in single-hop wireless sensor networks - A case study (Abstract)

Daniel Schmidt , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663, Germany
Matthias Berning , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663, Germany
Norbert Wehn , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663, Germany
pp. 1296-1301

Design of an application-specific instruction set processor for high-throughput and scalable FFT (PDF)

Xuan Guan , Dept. of Electrical & Computer Engineering, University of Connecticut, Storrs, USA
Hai Lin , Dept. of Electrical & Computer Engineering, University of Connecticut, Storrs, USA
Yunsi Fei , Dept. of Electrical & Computer Engineering, University of Connecticut, Storrs, USA
pp. 1302-1307

A novel LDPC decoder for DVB-S2 IP (PDF)

Stefan Muller , THOMSON - System Architecture Group - Herman-Schwer-Str. 3 78048 Villingen-Schwenningen, Germany
Manuel Schreger , THOMSON - System Architecture Group - Herman-Schwer-Str. 3 78048 Villingen-Schwenningen, Germany
Marten Kabutz , THOMSON - System Architecture Group - Herman-Schwer-Str. 3 78048 Villingen-Schwenningen, Germany
Matthias Alles , University of Kaiserslautern - Microelectronic Systems Design Research Group - Erwin-Schroedinger-Str., 67663, Germany
Frank Kienle , University of Kaiserslautern - Microelectronic Systems Design Research Group - Erwin-Schroedinger-Str., 67663, Germany
Norbert Wehn , University of Kaiserslautern - Microelectronic Systems Design Research Group - Erwin-Schroedinger-Str., 67663, Germany
pp. 1308-1313

A flexible floating-point wavelet transform and wavelet packet processor (PDF)

Andre Guntoro , Department of Electrical Engineering and Information Technology, Institute of Microelectronic Systems, Technische Universität Darmstadt, Germany
Manfred Glesner , Department of Electrical Engineering and Information Technology, Institute of Microelectronic Systems, Technische Universität Darmstadt, Germany
pp. 1314-1319

On hierarchical statistical static timing analysis (PDF)

Bing Li , Technische Universitaet Muenchen, Arcisstrasse 21, 80333 Munich, Germany
Ning Chen , Technische Universitaet Muenchen, Arcisstrasse 21, 80333 Munich, Germany
Manuel Schmidt , Technische Universitaet Muenchen, Arcisstrasse 21, 80333 Munich, Germany
Walter Schneider , Technische Universitaet Muenchen, Arcisstrasse 21, 80333 Munich, Germany
Ulf Schlichtmann , Technische Universitaet Muenchen, Arcisstrasse 21, 80333 Munich, Germany
pp. 1320-1325

Increasing the accuracy of SAT-based debugging (PDF)

Andre Sulflow , Institute of Computer Science, University of Bremen, 28359, Germany
Gorschwin Fey , Institute of Computer Science, University of Bremen, 28359, Germany
Cecile Braunstein , Laboratoire LIP6-SoC, University Paris VI, 75252 Paris, France
Ulrich Kuhne , Institute of Computer Science, University of Bremen, 28359, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 1326-1331

GCS: High-performance gate-level simulation with GPGPUs (Abstract)

Debapriya Chatterjee , Department of Computer Science and Engineering, University of Michigan, USA
Andrew DeOrio , Department of Computer Science and Engineering, University of Michigan, USA
Valeria Bertacco , Department of Computer Science and Engineering, University of Michigan, USA
pp. 1332-1337

Trace signal selection for visibility enhancement in post-silicon validation (PDF)

Xiao Liu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
pp. 1338-1343

A new design-for-test technique for SRAM core-cell stability faults (PDF)

A. Ney , LIRMM - University of Montpellier /CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
L. Dilillo , LIRMM - University of Montpellier /CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
P. Girard , LIRMM - University of Montpellier /CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
S. Pravossoudovitch , LIRMM - University of Montpellier /CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
A. Virazel , LIRMM - University of Montpellier /CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
M. Bastian , Infineon Technologies France, 2600, route des Crêtes - 06560 Sophia-Antipolis, France
V. Gouin , Infineon Technologies France, 2600, route des Crêtes - 06560 Sophia-Antipolis, France
pp. 1344-1348

Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing (Abstract)

Saqib Khursheed , School of ECS, University of Southampton, UK
Bashir M. Al-Hashimi , School of ECS, University of Southampton, UK
Peter Harrod , ARM Limited, Cambridge, UK
pp. 1349-1354

A diagnosis algorithm for extreme space compaction (Abstract)

Stefan Holst , Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47; D-70569, Germany
Hans-Joachim Wunderlich , Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47; D-70569, Germany
pp. 1355-1360

Thermal-aware memory mapping in 3D designs (PDF)

Ang-Chih Hsieh , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
TingTing Hwang , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300
pp. 1361-1366

Static analysis to mitigate soft errors in register files (PDF)

Jongeun Lee , Department of Computer Science and Engineering, Arizona State University, Tempe, 85281, USA
Aviral Shrivastava , Department of Computer Science and Engineering, Arizona State University, Tempe, 85281, USA
pp. 1367-1372

Using dynamic compilation for continuing execution under reduced memory availability (Abstract)

Ozcan Ozturk , Computer Engineering Department, Bilkent University, Ankara, Turkey
Mahmut Kandemir , Computer Science and Engineering Department, Pennsylvania State University, University Park, 16802, USA
pp. 1373-1378

A design methodology for fully reconfigurable Delta-Sigma data converters (PDF)

Yi Ke , Katholieke Universiteit Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001, Belgium
Jan Craninckx , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Georges Gielen , Katholieke Universiteit Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001, Belgium
pp. 1379-1384

Optimal sizing of configurable devices to reduce variability in integrated circuits (Abstract)

Peter Wilson , Electronics System Design Group, School of Electronics and Computer Science, University of Southampton, UK
Reuben Wilcock , Electronics System Design Group, School of Electronics and Computer Science, University of Southampton, UK
pp. 1385-1390

An automated design flow for vibration-based energy harvester systems (PDF)

Leran Wang , School of Electronics and Computer Science, University of Southampton, UK
Tom J. Kazmierski , School of Electronics and Computer Science, University of Southampton, UK
Bashir M. Al-Hashimi , School of Electronics and Computer Science, University of Southampton, UK
Steve P. Beeby , School of Electronics and Computer Science, University of Southampton, UK
Dibin Zhu , School of Electronics and Computer Science, University of Southampton, UK
pp. 1391-1396

Enhanced design of filterless class-D audio amplifier (PDF)

Chun Wei Lin , Department of Electronic Engineering, National Yunlin University of Science & Technology, 64002, Taiwan
Bing-Shiun Hsieh , Department of Electronic Engineering, National Yunlin University of Science & Technology, 64002, Taiwan
Yu Cheng Lin , Department of Electronic Engineering, National Yunlin University of Science & Technology, 64002, Taiwan
pp. 1397-1402

Panel session - Multicore, will Startups drive innovation? (PDF)

A. Jerraya , CEA-LETI, France
R. Ernst , TU Braunschweig, Germany
pp. 1403

Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels (PDF)

Giacomo Paci , DEIS, University of Bologna, 40136, Italy
Davide Bertozzi , ENDIF, University of Ferrara, 44100, Italy
Luca Benini , DEIS, University of Bologna, 40136, Italy
pp. 1404-1409

Dynamic thermal management in 3D multicore architectures (Abstract)

Ayse K. Coskun , Computer Science and Engineering Dept. (CSE), University of California, San Diego, USA
Jose L. Ayala , Computer Architecture and Automation Dept. (DACYA), Complutense University of Madrid, Spain
David Atienza , Embedded Systems Laboratory (ESL), Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Tajana Simunic Rosing , Computer Science and Engineering Dept. (CSE), University of California, San Diego, USA
Yusuf Leblebici , Microelectronics Systems Laboratory (LSM), EPFL, Switzerland
pp. 1410-1415

Energy minimization for real-time systems with non-convex and discrete operation modes (Abstract)

Foad Dabiri , Computer Science Department, University of California Los Angeles, USA
Alireza Vahdatpour , Computer Science Department, University of California Los Angeles, USA
Miodrag Potkonjak , Computer Science Department, University of California Los Angeles, USA
Majid Sarrafzadeh , Computer Science Department, University of California Los Angeles, USA
pp. 1416-1421

Exploiting narrow-width values for thermal-aware register file designs (PDF)

Shuai Wang , Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, 07102, USA
Jie Hu , Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, 07102, USA
Sotirios G. Ziavras , Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, 07102, USA
Sung Woo Chung , Division of Computer and Communication Engineering, Korea University, Seoul 136-713, Korea
pp. 1422-1427

Visual quality analysis for dynamic backlight scaling in LCD systems (Abstract)

Andrea Bartolini , University of Bologna, DEIS, via Risorgimento 2, 40133, Italy
Martino Ruggiero , University of Bologna, DEIS, via Risorgimento 2, 40133, Italy
Luca Benini , University of Bologna, DEIS, via Risorgimento 2, 40133, Italy
pp. 1428-1433

A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec (PDF)

Muhammad Shafique , University of Karlsruhe, Chair for Embedded Systems, Germany
Lars Bauer , University of Karlsruhe, Chair for Embedded Systems, Germany
Jorg Henkel , University of Karlsruhe, Chair for Embedded Systems, Germany
pp. 1434-1439

Efficient constant-time entropy decoding for H.264 (PDF)

Nabeel Iqbal , University of Karlsruhe, Chair for Embedded systems, Germany
Jorg Henkel , University of Karlsruhe, Chair for Embedded systems, Germany
pp. 1440-1445

Predictive models for multimedia applications power consumption based on use-case and OS level analysis (PDF)

Patrick Bellasi , Dipartimento di Elettronica e Informazione, Politecnico di Milano, P.zza Leonardo da Vinci, 32. 20133, Italy
William Fornaciari , Dipartimento di Elettronica e Informazione, Politecnico di Milano, P.zza Leonardo da Vinci, 32. 20133, Italy
David Siorpaes , Advanced System Technology, STMicroelectronics, Via C. Olivetti, 2. 20041 - Agrate Brianza, Italy
pp. 1446-1451

Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis (PDF)

Sivaram Gopalakrishnan , Synopsys Inc, Hillsboro, OR USA
Priyank Kalla , Electrical & Computer Engineering, University of Utah, Salt Lake City, USA
pp. 1452-1457

Sequential logic synthesis using symbolic bi-decomposition (Abstract)

Victor N. Kravets , IBM TJ Watson Research Center, Yorktown Heights, NY USA
Alan Mishchenko , Department of EECS, University of California, Berkeley, USA
pp. 1458-1463

On decomposing Boolean functions via extended cofactoring (PDF)

Anna Bernasconi , Department of Computer Science, University of Pisa, Italy
Valentina Ciriani , Department of Information Technologies, University of Milano, Italy
Gabriella Trucco , Department of Information Technologies, University of Milano, Italy
Tiziano Villa , Department of Computer Science, University of Verona, Italy
pp. 1464-1469

Register placement for high-performance circuits (PDF)

Mei-Fang Chiang , Graduate School of IPS, Waseda University, Kitakyushu 808-0135, Japan
Takumi Okamoto , NEC Corporation, Kanagawa 211-8666, Japan
Takeshi Yoshimura , Graduate School of IPS, Waseda University, Kitakyushu 808-0135, Japan
pp. 1470-1475

Scalable Adaptive Scan (SAS) (PDF)

Anshuman Chandra , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, Canada
Rohit Kapur , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, Canada
Yasunari Kanzawa , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, Canada
pp. 1476-1481

LFSR-based test-data compression with self-stoppable seeds (Abstract)

M. Koutsoupia , Comp. Eng. & Inf. Dept., University of Patras, Greece
E. Kalligeros , Information & Comm. Systems Eng., Dept., Univ. of the Aegean, Greece
X. Kavousianos , Computer Science Dept., Univ. of Ioannina, Greece
D. Nikolos , Comp. Eng. & Inf. Dept., University of Patras, Greece
pp. 1482-1487

Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects (PDF)

Mahmut Yilmaz , Design for Test Group, Advanced Micro Devices, 1 AMD Pl. Sunnyvale, CA 94085, USA
Krishnendu Chakrabarty , Dept. Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
pp. 1488-1493

A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment (PDF)

Xiao Liu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Qiang Xu , CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong
pp. 1494-1499

Correct-by-construction generation of device drivers based on RTL testbenches (PDF)

Nicola Bombieri , Dipartimento di Informatica, Università di Verona, Italy
Franco Fummi , Dipartimento di Informatica, Università di Verona, Italy
Graziano Pravadelli , Dipartimento di Informatica, Università di Verona, Italy
Sara Vinco , Dipartimento di Informatica, Università di Verona, Italy
pp. 1500-1505

Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures (PDF)

Jun Zhu , Royal Institute of Technology, Stockholm, Sweden
Ingo Sander , Royal Institute of Technology, Stockholm, Sweden
Axel Jantsch , Royal Institute of Technology, Stockholm, Sweden
pp. 1506-1511

A formal approach for specification-driven AMS behavioral model generation (PDF)

Subhankar Mukherjee , Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, West Bengal, India 721302
Antara Ain , Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, West Bengal, India 721302
S. K. Panda , Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, West Bengal, India 721302
Rajdeep Mukhopadhyay , Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, West Bengal, India 721302
Pallab Dasgupta , Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, West Bengal, India 721302
pp. 1512-1517

SC-DEVS: An efficient SystemC extension for the DEVS model of computation (Abstract)

Felix Madlener , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
H. Gregor Molter , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
Sorin A. Huss , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
pp. 1518-1523

Exploiting clock skew scheduling for FPGA (PDF)

Sungmin Bae , CSE Department, Pennsylvania State University, University Park, 16801, USA
Prasanth Mangalagiri , CSE Department, Pennsylvania State University, University Park, 16801, USA
N. Vijaykrishnan , CSE Department, Pennsylvania State University, University Park, 16801, USA
pp. 1524-1529

Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing (PDF)

Xiaoheng Chen , Department of Electrical and Computer Engineering, University of California, Davis, 95616, USA
Jingyu Kang , Department of Electrical and Computer Engineering, University of California, Davis, 95616, USA
Shu Lin , Department of Electrical and Computer Engineering, University of California, Davis, 95616, USA
Venkatesh Akella , Department of Electrical and Computer Engineering, University of California, Davis, 95616, USA
pp. 1530-1535

Runtime reconfiguration of custom instructions for real-time embedded systems (Abstract)

Huynh Phung Huynh , School of Computing, National University of Singapore
Tulika Mitra , School of Computing, National University of Singapore
pp. 1536-1541

Digital design at a crossroads How to make statistical design methodologies industrially relevant (PDF)

Ulf Schlichtmann , Technische Universität München, Munich, Germany
Manuel Schmidt , Technische Universität München, Munich, Germany
Harald Kinzelbach , Infineon Technologies AG, Munich, Germany
Michael Pronath , MunEDA GmbH, Munich, Germany
Volker Glockel , MunEDA GmbH, Munich, Germany
Manfred Dietrich , Fraunhofer IIS/EAS Dresden, Dresden, Germany
Uwe Eichler , Fraunhofer IIS/EAS Dresden, Dresden, Germany
Joachim Haase , Fraunhofer IIS/EAS Dresden, Dresden, Germany
pp. 1542-1547

Performance optimal speed control of multi-core processors under thermal constraints (Abstract)

Vinay Hanumaiah , Computer Science and Engineering Department, Arizona State University, Tempe 85281 USA
Sarma Vrudhula , Computer Science and Engineering Department, Arizona State University, Tempe 85281 USA
Karam S. Chatha , Computer Science and Engineering Department, Arizona State University, Tempe 85281 USA
pp. 1548-1551

Scalable compile-time scheduler for multi-core architectures (PDF)

Maxime Pelcat , IETR/INSA, UMR CNRS 6164, Rennes, France
Pierrick Menuet , IETR/INSA, UMR CNRS 6164, Rennes, France
Slaheddine Aridhi , Texas Instruments, CIV Division, Villeneuve Loubet, France
Jean-Francois Nezan , IETR/INSA, UMR CNRS 6164, Rennes, France
pp. 1552-1555

Distributed peak power management for many-core architectures (Abstract)

John Sartori , Coordinated Science Laboratory, 1308West Main St, Urbana, IL 61801, USA
Rakesh Kumar , Coordinated Science Laboratory, 1308West Main St, Urbana, IL 61801, USA
pp. 1556-1559

Generating the trace qualification configuration for MCDS from a high level language (PDF)

Jens Braunes , pls Development Tools, Technologiepark, 02991 Lauta, Germany
Rainer G. Spallek , Technische Universität Dresden, 01062, Germany
pp. 1560-1563

Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC (Abstract)

Diego Puschini , CEA, LETI, MINATEC, F38054 Grenoble, France
Fabien Clermidy , CEA, LETI, MINATEC, F38054 Grenoble, France
Pascal Benoit , LIRMM, CNRS and University of Montpellier 2, France
Gilles Sassatelli , LIRMM, CNRS and University of Montpellier 2, France
Lionel Torres , CEA, LETI, MINATEC, F38054 Grenoble, France
pp. 1564-1567

A MILP-based approach to path sensitization of embedded software (PDF)

Jose C. Costa , TU Lisbon, IST / INESC-ID, 1000-029 Lisboa, Portugal
Jose C. Monteiro , TU Lisbon, IST / INESC-ID, 1000-029 Lisboa, Portugal
pp. 1568-1571

Toward a runtime system for reconfigurable computers: A virtualization approach (PDF)

Mojtaba Sabeghi , Computer Engineering Laboratory, Delft University of Technology, the Netherlands
Koen Bertels , Computer Engineering Laboratory, Delft University of Technology, the Netherlands
pp. 1576-1579

Separate compilation and execution of imperative synchronous modules (PDF)

Eric Vecchie , INRIA Rennes - Bretagne Atlantique, Campus de Beaulieu, 35042 Rennes Cedex, France
Jean-Pierre Talpin , INRIA Rennes - Bretagne Atlantique, Campus de Beaulieu, 35042 Rennes Cedex, France
Klaus Schneider , University of Kaiserslautern, P.O. Box 3049, 67653, Germany
pp. 1580-1583

Programming MPSoC platforms: Road works ahead! (PDF)

Rainer Leupers , RWTH Aachen University, Germany
Andras Vajda , Ericsson SW Research, USA
Marco Bekooij , NXP, The Netherlands
Soonhoi Ha , Seoul National University, Korea
Rainer Domer , UC Irvine, USA
Achim Nohl , CoWare Inc, USA
pp. 1584-1589

Faster SAT solving with better CNF generation (Abstract)

Benjamin Chambers , Northeastern University, USA
Panagiotis Manolios , Northeastern University, USA
Daron Vroon , General Theological Seminary of the Episcopal Church, USA
pp. 1590-1595

Exploiting structure in an AIG based QBF solver (Abstract)

Florian Pigorsch , Albert-Ludwigs-Universität Freiburg, Institut für Informatik, D-79110 Freiburg im Breisgau, Germany
Christoph Scholl , Albert-Ludwigs-Universität Freiburg, Institut für Informatik, D-79110 Freiburg im Breisgau, Germany
pp. 1596-1601

An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification (PDF)

Nannan He , Department of Electrical and Computer Engineering, Virginia Tech Blacksburg, 24061, USA
Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech Blacksburg, 24061, USA
pp. 1602-1607

A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing (PDF)

Christian Bachmann , Institute for Technical Informatics, Graz University of Technology, Inffeldgasse 16, 8010, Austria
Andreas Genser , Institute for Technical Informatics, Graz University of Technology, Inffeldgasse 16, 8010, Austria
Jos Hulzink , IMEC Netherlands, Holst Centre, High Tech Campus 31, 5656 AE Eindhoven, The Netherlands
Mladen Berekovic , IDA, TU Braunschweig, Hans-Sommer-Str. 66, 38106, Germany
Christian Steger , Institute for Technical Informatics, Graz University of Technology, Inffeldgasse 16, 8010, Austria
pp. 1614-1619

ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications (Abstract)

Atif Raza Jafri , Institut TELECOM; TELECOM Bretagne; UMR CNRS 3192 Lab-STICC, Electronics Department, Technopôle Brest Iroise CS 83818, 29238 Brest Université Européenne de Bretagne, France
Daoud Karakolah , Institut TELECOM; TELECOM Bretagne; UMR CNRS 3192 Lab-STICC, Electronics Department, Technopôle Brest Iroise CS 83818, 29238 Brest Université Européenne de Bretagne, France
Amer Baghdadi , Institut TELECOM; TELECOM Bretagne; UMR CNRS 3192 Lab-STICC, Electronics Department, Technopôle Brest Iroise CS 83818, 29238 Brest Université Européenne de Bretagne, France
Michel Jezequel , Institut TELECOM; TELECOM Bretagne; UMR CNRS 3192 Lab-STICC, Electronics Department, Technopôle Brest Iroise CS 83818, 29238 Brest Université Européenne de Bretagne, France
pp. 1620-1625

Implementation of a reduced-lattice MIMO detector for OFDM Systems (PDF)

Josep Soler-Garrido , Toshiba Research Europe Ltd., Telecommunications Research Laboratory, 32 Queen Square, Bristol BS1 4ND United Kingdom
Henning Vetter , Toshiba Research Europe Ltd., Telecommunications Research Laboratory, 32 Queen Square, Bristol BS1 4ND United Kingdom
Magnus Sandell , Toshiba Research Europe Ltd., Telecommunications Research Laboratory, 32 Queen Square, Bristol BS1 4ND United Kingdom
David Milford , Toshiba Research Europe Ltd., Telecommunications Research Laboratory, 32 Queen Square, Bristol BS1 4ND United Kingdom
Andy Lillie , Toshiba Research Europe Ltd., Telecommunications Research Laboratory, 32 Queen Square, Bristol BS1 4ND United Kingdom
pp. 1626-1631

Increased accuracy through noise injection in abstract RTOS simulation (Abstract)

Henning Zabel , Universität Paderborn, C-LAB, Fürstenallee 11, D-33102, Germany
Wolfgang Mueller , Universität Paderborn, C-LAB, Fürstenallee 11, D-33102, Germany
pp. 1632-1637

Flexible energy-aware simulation of heterogenous wireless sensor networks (PDF)

Franco Fummi , Dipartimento di Informatica, Universitá di Verona, Strada le Grazie 15, I-37134, Italy
Giovanni Perbellini , Dipartimento di Informatica, Universitá di Verona, Strada le Grazie 15, I-37134, Italy
Davide Quaglia , Dipartimento di Informatica, Universitá di Verona, Strada le Grazie 15, I-37134, Italy
Andrea Acquaviva , DAUIN - Politecnico di Torino, Corso Duca Degli Abruzzi 24, 10129, Italy
pp. 1638-1643

Selective state retention design using symbolic simulation (Abstract)

Ashish Darbari , School of Electronics and Computer Science, University of Southampton, England
Bashir M. Al Hashimi , School of Electronics and Computer Science, University of Southampton, England
David Flynn , ARM, Cambridge, England, UK
John Biggs , ARM, Cambridge, England, UK
pp. 1644-1649

A loopback-based INL test method for D/A and A/D converters employing a stimulus identification technique (PDF)

Esa Korhonen , Department of Electrical and Information Engineering, University of Oulu, PO Box 4500, 90014, Finland
Juha Kostamovaara , Department of Electrical and Information Engineering, University of Oulu, PO Box 4500, 90014, Finland
pp. 1650-1655

A novel self-healing methodology for RF Amplifier circuits based on oscillation principles (Abstract)

Abhilash Goyal , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA-30332, USA
Madhavan Swaminathan , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA-30332, USA
Abhijit Chatterjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA-30332, USA
pp. 1656-1661

An approach to linear model-based testing for nonlinear cascaded mixed-signal systems (PDF)

Reik Muller , Technische Universität Dresden, Germany
Carsten Wegener , Infineon Technologies, Munich, Germany
Hans-Joachim Jentschel , Technische Universität Dresden, Germany
Sebastian Sattler , Infineon Technologies, Munich, Germany
Heinz Mattes , Infineon Technologies, Munich, Germany
pp. 1662-1667

Enrichment of limited training sets in machine-learning-based analog/RF test (Abstract)

Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
Salvador Mir , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031, France
Yiorgos Makris , Department of Electrical Engineering, Yale University, 10 Hillhouse Ave., New Haven, CT 06520, USA
pp. 1668-1673

Speculative reduction-based scalable redundancy identification (Abstract)

Hari Mony , IBM Systems & Technology Group, Austin, TX, USA
Jason Baumgartner , IBM Systems & Technology Group, Austin, TX, USA
Alan Mishchenko , Department of EECS, University of California, Berkeley, USA
Robert Brayton , Department of EECS, University of California, Berkeley, USA
pp. 1674-1679

Scalable liveness checking via property-preserving transformations (PDF)

Jason Baumgartner , IBM Systems & Technology Group, Austin, TX, USA
Hari Mony , IBM Systems & Technology Group, Austin, TX, USA
pp. 1680-1685

Speeding up model checking by exploiting explicit and hidden verification constraints (Abstract)

G. Cabodi , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
P. Camurati , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
L. Garcia , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
M. Murciano , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
S. Nocco , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
S. Quer , Dipartimento di Automatica ed Informatica Politecnico di Torino, Italy
pp. 1686-1691

Strengthening properties using abstraction refinement (PDF)

Mitra Purandare , Computer Systems Institute, ETH Zurich, Switzerland
Thomas Wahl , Computing Laboratory, Oxford University, U.K.
Daniel Kroening , Computing Laboratory, Oxford University, U.K.
pp. 1692-1697

Sequential logic rectifications with approximate SPFDs (PDF)

Yu-Shen Yang , Dept. of ECE, University of Toronto, Canada
Subarna Sinha , Synopsys Inc., Mountain View, United States
Andreas Veneris , Dept. of ECE, University of Toronto, Canada
Robert K. Brayton , Dept. of EECS, University of California, Berkeley, United States
Duncan Smith , Vennsa Inc., Toronto, Canada
pp. 1698-1703

Variable-latency design by function speculation (PDF)

D. Baneres , Universitat Oberta de Catalunya, Barcelona, Spain
J. Cortadella , Universitat Politècnica de Catalunya, Barcelona, Spain
M. Kishinevsky , Strategic CAD Lab, Intel Corp., Hillsboro, OR USA
pp. 1704-1709

Fixed points for multi-cycle path detection (PDF)

Vijay D'Silva , Computing Laboratory, Oxford University, U.K.
Daniel Kroening , Computing Laboratory, Oxford University, U.K.
pp. 1710-1715
88 ms
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