The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2008)
Munich, Germany
Mar. 10, 2008 to Mar. 14, 2008
ISBN: 978-3-9810801-3-1
TABLE OF CONTENTS
Papers

Table of contents (PDF)

pp. iv-xxvii

date executive committee (PDF)

pp. xxviii-xxix

Reviewers (PDF)

pp. xxxv-xxxviii

Foreword (PDF)

pp. xxxix-xl

Automatically Realising Embedded Systems from High-Level Functional Models (PDF)

Christos Cassandras , Boston U, US
Don Orofino , The MathWorks, US
Wido Kruijtzer , NXP, NL
Pieter J Mosterman , The MathWorks, US
Janos Sztipanovits , Vanderbilt U, US
Grant Martin , Tensilica, US
Ahmed Jerraya , CEA-LETI, FR
V Reyes , NXP, NL
pp. xlii

Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems (PDF)

Vera Lauer , DaimlerChrysler AG, DE
Andreas Herkersdorf , TU Munich, DE
Walter Stechele , TU Munich, DE
Juergen Becker , Karlsruhe U, DE
Robert Esser , Xilinx, Dublin, IE
Michael Huebner , Karlsruhe U, DE
Juergen Becker , Karlsruhe U, DE
Michael Huebner , Karlsruhe U, DE
pp. xlii

Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level (PDF)

Diana Marculescu , Carnegie Mellon University, US
Diana Marculescu , Carnegie Mellon University, US
Sani Nassif , IBM, US
pp. xliii

Power Gating for Ultra-low Leakage: Physics, Design, and Analysis (PDF)

Jerry Frenkil , Sequence Design, US
Kimiyoshi Usami , Shibaura Institute of Technology, JP
Ken Choi , Illinois Institute of Technology, US
Jerry Frenkil , Sequence Design, US
pp. xliii

Heterogeneous System-level Specification Using SystemC (PDF)

Tim Kogel , CoWare, DE
Axel Jantsch , KTH, SE
Eugenio Villar , Cantabria U, ES
Eugenio Villar , Cantabria U, ES
Christoph Grimm , TU Vienna, AT
pp. xliii-xliv

Power-Aware Testing and Test Strategies for Low Power Devices (PDF)

Patrick Girard , LIRMM, FR
Dimitris Gizopoulos , Piraeus U, GR
Xiaoqing Wen , Kyushu Institute of Technology, JP
Nicola Nicolici , McMaster University, CA
Kaushik Roy , Purdue University, USA
pp. xliv

From Transistor to PLL - Analogue Design and EDA Methods (PDF)

David M Binkley , U of NC at Charlotte, US
Jaijeet Roychowdhury , U of Minn Twin Cities, US
David M Binkley , U of NC at Charlotte, US
Helmut Graeb , TU Munich, DE
Georges G E Gielen , KU Leuven, BE
pp. xliv

DfM in the Analogue and Digital World (PDF)

Emmanuel Blanc , Mentor Graphics, FR
Carsten Elgert , Mentor Graphics, DE
Volker Herbig , X-Fab, DE
Thomas Harms , IFX, DE
Anton Ossner , Chartered Semiconductor, DE
pp. xliv-xlv

Formal Methods in System and MpSoC Performance Analysis and Optimisation (PDF)

Samarjit Chakraborty , National U of Singapore, SG
Rolf Ernst , TU Braunschweig, DE
Marco Bekooij , NXP, NE
Rolf Ernst , TU Braunschweig, DE
Marek Jersak , Symtavision, DE
Hans Sarnowski , BMW, DE
pp. xlv

EDAA/DATE PhD Forum (PDF)

pp. vli-vlii

Call for Papers (PDF)

pp. vliii

Designing Micro/Nano Systems for a Safer and Healthier Tomorrow (PDF)

Giovanni De Micheli , Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPFL, Lausanne, Switzerland
pp. 1

Cycle-approximate Retargetable Performance Estimation at the Transaction Level (Abstract)

Yonghyun Hwang , Center for Embedded Computer Systems, University of California, Irvine, 92617-2625. e-mail: yonghyuh@uci.edu
Samar Abdi , Center for Embedded Computer Systems, University of California, Irvine, 92617-2625. e-mail: sabdi@uci.edu
Daniel Gajski , Center for Embedded Computer Systems, University of California, Irvine, 92617-2625. e-mail: gajski@uci.edu
pp. 3-8

A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip (Abstract)

Florence Maraninchi , VERIMAG. Centre Équation - 2, avenue de Vignate, 38610 GI
Laurent Maillet-Contoz , STMicroelectronics, System Platforms Group., 12 rue Jules Horowitz - B.P. 217, 38019 GRENOBLE Cedex ¿ France. laurent.maillet-contoz@st.com
Jerome Cornet , VERIMAG. Centre Équation - 2, avenue de Vignate, 38610 GI
pp. 9-14

Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation (Abstract)

Nicola Bombieri , Dipartimento di Informatica, Università di Verona, Italy. bombieri@sci.univr.it
Franco Fummi , Dipartimento di Informatica, Università di Verona, Italy. fummi@sci.univr.it
Nicola Deganello , Dipartimento di Informatica, Università di Verona, Italy. deganello@sci.univr.it
pp. 15-20

On the Verification of High-Order Constraint Compliance in IC Design (Abstract)

Wolfgang Nebel , University of Oldenburg and OFFIS, Oldenburg, Germany
Goran Jerke , Robert Bosch GmbH, Automotive Electronics, Division AE/EIM3, Reutlingen, Germany
Joachim Gerlach , Robert Bosch GmbH, Automotive Electronics, Division AE/EIM3, Reutlingen, Germany
Jan Freuer , Robert Bosch GmbH, Automotive Electronics, Division AE/EIM3, Reutlingen, Germany
pp. 26-31

Industrial IP Integration Flows based on IP-XACT¿ Standards (Abstract)

Wolfgang Ecker , Infineon Technologies, Germany
Emmanuel Vaumorin , Magillem Design Services, France
Jan Stuyt , NXP Semiconductors, The Netherlands
Albrecht Mayer , Infineon Technologies, Germany
Pieter van der Wolf , NXP Semiconductors, The Netherlands
Wido Kruijtzer , NXP Semiconductors, The Netherlands. Wido.Kruijtzer@nxp.com
Serge Hustin , STMicroelectronics, Belgium
Serge de Paoli , STMicroelectronics, France
Christophe Amerijckx , STMicroelectronics, Belgium
Erwin de Kock , NXP Semiconductors, The Netherlands
pp. 32-37

A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment (Abstract)

Timo Vogt , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany. vogt@eit.uni-kl.de
Norbert Wehn , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany. wehn@eit.uni-kl.de
pp. 38-43

Using Reconfigurable Logic to Optimise GPU Memory Accesses (Abstract)

Wayne Luk , Department of Computing, Imperial College London
Peter Y.K. Cheung , Department of Electrical&Electronic Engineering, Imperial College London
Ben Cope , Department of Electrical&Electronic Engineering, Imperial College London
pp. 44-49

Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs (Abstract)

Michael Hubner , Universität Karlsruhe (TH), Germany. huebner@itiv.uni-karlsruhe.de
Katarina Paulsson , Universität Karlsruhe (TH), Germany. paulsson@itiv.uni-karlsruhe.de
Jurgen Becker , Universität Karlsruhe (TH), Germany. becker@itiv.uni-karlsruhe.de
pp. 50-55

Design flow for embedded FPGAs based on a flexible architecture template (Abstract)

T. G. Noll , Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Schinkelstr. 2, 52062 Aachen, Germany. email: tgn@eecs.rwth-aachen.de
B. Neumann , Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Schinkelstr. 2, 52062 Aachen, Germany. email: neumann@eecs.rwth-aachen.de
T. von Sydow , Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Schinkelstr. 2, 52062 Aachen, Germany. email: sydow@eecs.rwth-aachen.de
H. Blume , Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Schinkelstr. 2, 52062 Aachen, Germany. email: blume@eecs.rwth-aachen.de
pp. 56-61

Optimal High-Resolution Spectral Analyzer (Abstract)

H. Mattes , Dept. of Analog Design for Test, Infineon Technologies, Munich, Germany. heinz.mattes@infineon.com
A. Tchegho , Institute of Electronic Design Automation, Technische Universitaet Muenchen, Munich, Germany. aurelien.tchegho@tum.de
S. Sattler , Dept. of Analog Design for Test, Infineon Technologies, Munich, Germany. sebastian.sattler@infineon.com
pp. 62-67

A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation (Abstract)

Salvador Mir , TIMA Laboratory/CNRS, 46 Av. Félix Viallet, 38031 Grenoble, France
Jeanne Tongbong , TIMA Laboratory/CNRS, 46 Av. Félix Viallet, 38031 Grenoble, France
Haralampos-G. Stratigopoulos , TIMA Laboratory/CNRS, 46 Av. Félix Viallet, 38031 Grenoble, France
pp. 68-73

Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters (Abstract)

Jose Pineda de Gyvez , NXP Semiconductors Research, HighTech Campus 37, 5656 AE Eindhoven, The Netherlands; Eindhoven University of Technology, Den Dolech 2, 5612 AZ Eindhoven, The Netherlands
Amir Zjajo , NXP Semiconductors Research, HighTech Campus 37, 5656 AE Eindhoven, The Netherlands. e-mail: amir.zjajo@nxp.com
pp. 74-79

Practical Implementation of a Network Analyzer for Analog BIST Applications (Abstract)

Manuel J. Barragan , Instituto de Microelectrónica de Sevilla/Centro Nacional de Microelectrónica/Consejo Superior de, Investigaciones Científicas (IMSE-CNM-CSIC)/Universidad de Sevilla, Ed. CICA-CNM,
Diego Vazquez , Instituto de Microelectrónica de Sevilla/Centro Nacional de Microelectrónica/Consejo Superior de, Investigaciones Científicas (IMSE-CNM-CSIC)/Universidad de Sevilla, Ed. CICA-CNM,
Adoracion Rueda , Instituto de Microelectrónica de Sevilla/Centro Nacional de Microelectrónica/Consejo Superior de, Investigaciones Científicas (IMSE-CNM-CSIC)/Universidad de Sevilla, Ed. CICA-CNM,
pp. 80-85

Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis Techniques (Abstract)

Joost-Pieter Katoen , RWTH Aachen University, Aachen, Germany. katoen@cs.rwth-aachen.de
pp. 86-87

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures (Abstract)

Yvain Thonnart , CEA/Leti, Grenoble, France. yvain.thonnart@cea.fr
Hubert Garavel , INRIA, Grenoble, France. hubert.garavel@inria.fr
Meriem Zidouni , Bull, Les Clayes-sous-Bois, France. meriem.zidouni@bull.net
Nicolas Coste , STMicroelectronics, Grenoble, France. nicolas.coste@st.com
Holger Hermanns , Saarland University, Saarbrücken, Germany. hermanns@cs.uni-sb.de
Richard Hersemeule , STMicroelectronics, Grenoble, France. richard.hersemeule@st.com
pp. 88-89

Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices (Abstract)

Lucia Cloth , University of Twente, 7500 AE Enschede, The Netherlands. lucia@cs.utwente.nl
Boudewijn R. Haverkort , University of Twente, 7500 AE Enschede, The Netherlands. brh@cs.utwente.nl
pp. 90-91

A Framework of Stochastic Power Management Using Hidden Markov Model (Abstract)

Ying Tan , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, New York 13902, USA. ying@binghamton.edu
Qinru Qiu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, New York 13902, USA. qqiu@binghamton.edu
pp. 92-97

Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement (Abstract)

Somnath Paul , Department of EECS, Case Western Reserve University. sxp190@case.edu
Swarup Bhunia , Department of EECS, Case Western Reserve University. skb21@case.edu
Yu Zhou , Department of EECS, Case Western Reserve University. yxz77@case.edu
pp. 98-103

An Efficient Solar Energy Harvester for Wireless Sensor Nodes (Abstract)

Luca Benini , University of Bologna, Italy. luca.benini@unibo.it
Clemens Moser , Swiss Federal Institute of Technology Zurich. moser@tik.ee.ethz.ch
Lothar Thiele , Swiss Federal Institute of Technology Zurich. thiele@tik.ee.ethz.ch
Davide Brunelli , University of Bologna, Italy. davide.brunelli@unibo.it
pp. 104-109

Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization (Abstract)

Srinivasan Murali , LSI, EPFL, Switzerland. srinivasan.murali@epfl.ch
Giovanni De Micheli , LSI, EPFL, Switzerland. giovanni.demicheli@epfl.ch
David Atienza , LSI, EPFL, Switzerland; DACYA, Complutense University of Madrid (UCM), Spain. david.atienza@epfl.ch
Stephen Boyd , Department of Electrical Engineering, Stanford University, USA. boyd@tanford.edu
Almir Mutapcic , Department of Electrical Engineering, Stanford University, USA. almirm@tanford.edu
Luca Benini , DEIS, University of Bologna, Italy. lbenini@deis.unibo.it
Rajesh Gupta , Department of Computer Science and Engineering, UCSD, USA. rgupta@ucsd.edu
pp. 110-115

Parametric Throughput Analysis of Synchronous Data Flow Graphs (Abstract)

S. Stuijk , Eindhoven University of Technology, Electronic Systems Group
A.H. Ghamarian , Eindhoven University of Technology, Electronic Systems Group. a.h.ghamarian@tue.nl
M.C.W. Geilen , Eindhoven University of Technology, Electronic Systems Group
T. Basten , Eindhoven University of Technology, Electronic Systems Group
pp. 116-121

Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling (Abstract)

Rainer Domer , Center of Embedded Computer Systems, University of California Irvine E-mail: doemer@uci.edu
Gunar Schirner , Center of Embedded Computer Systems, University of California Irvine E-mail: hschirne@uci.edu
pp. 122-127

SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder (Abstract)

Wolfgang Nebel , OFFIS e.V., Germany
Frank Oppenheimer , OFFIS e.V., Germany
Kim Gruttner , OFFIS e.V., Germany
Fabien Colas-Bigey , Thales Communications, France
Anne-Marie Fouilliart , Thales Communications, France
pp. 128-133

Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN (Abstract)

Karsten Einwich , Fraunhofer IIS/EAS, Dresden, Germany. karsten.einwich@eas.iis.fraunhofer.de
Nicolas Beilleau , University Paris VI, Pierre&Marie Curie LIP6-SoC Laboratory, 75252 Paris, France, nicolas.beilleau@lip6.fr
Michel Vasilevski , University Paris VI, Pierre&Marie Curie LIP6-SoC Laboratory, 75252 Paris, France, michel.vasilevski@lip6.fr
Francois Pecheux , University Paris VI, Pierre&Marie Curie LIP6-SoC Laboratory, 75252 Paris, France, francois.pecheux@lip6.fr
Hassan Aboushady , University Paris VI, Pierre&Marie Curie LIP6-SoC Laboratory, 75252 Paris, France, hassan.aboushady@lip6.fr
pp. 134-139

Sizing Rules for Bipolar Analog Circuit Design (Abstract)

Helmut Graeb , Institute for Electronic Design Automation, Technische Universitaet Muenchen
Ulf Schlichtmann , Institute for Electronic Design Automation, Technische Universitaet Muenchen
Tobias Massier , Institute for Electronic Design Automation, Technische Universitaet Muenchen
pp. 140-145

Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density (Abstract)

Tom J Kazmierski , School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, UK. tjk@ecs.soton.ac.uk
Bashir M Al-Hashimi , School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, UK. bmah@ecs.soton.ac.uk
Dafeng Zhou , School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, UK. dz05r@ecs.soton.ac.uk
pp. 146-151

A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits (Abstract)

Peter Wilson , Electronics System Design Group, School of Electronics and Computer Science, University of Southampton, UK. prw@ecs.soton.ac.uk
Sawal Ali , Electronics System Design Group, School of Electronics and Computer Science, University of Southampton, UK. shma05r@ecs.soton.ac.uk
Andrew Brown , Electronics System Design Group, School of Electronics and Computer Science, University of Southampton, UK. adb@ecs.soton.ac.uk
Reuben Wilcock , Electronics System Design Group, School of Electronics and Computer Science, University of Southampton, UK. rw3@ecs.soton.ac.uk
pp. 152-157

Symbolic Reliability Analysis and Optimization of ECU Networks (Abstract)

Jurgen Teich , University of Erlangen-Nuremberg, Germany. teich@cs.fau.de
Christian Haubelt , University of Erlangen-Nuremberg, Germany. haubelt@cs.fau.de
Felix Reimann , University of Erlangen-Nuremberg, Germany. felix.reimann@cs.fau.de
Martin Lukasiewycz , University of Erlangen-Nuremberg, Germany. martin.lukasiewycz@cs.fau.de
Michael GlaB , University of Erlangen-Nuremberg, Germany. glass@cs.fau.de
pp. 158-163

Verification of Temporal Properties in Automotive Embedded Software (Abstract)

Jurgen Ruf , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 Tübingen - Germany. E-mail: ruf@informatik.uni-tuebingen.de
Pradeep K. Nalla , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 Tübingen - Germany. E-mail: nalla@informatik.uni-tuebingen.de
Stephan Reitemeyer , NEC Electronics (Europe) GmbH, Arcadiastrasse 10, 40472 Düsseldorf - Germany. E-mail: Stephan.Reitemeyer@eu.necel.com
Djones Lettnin , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 Tübingen - Germany; CNPq scholarship holder, Brazil. E-mail: lettnin@informatik.uni-tuebingen.de
Volker Schonknecht , NEC Electronics (Europe) GmbH, Arcadiastrasse 10, 40472 Düsseldorf - Germany. E-mail: Volker.Schoenknecht@eu.necel.com
Tobias Kirsten , NEC Electronics (Europe) GmbH, Arcadiastrasse 10, 40472 Düsseldorf - Germany. E-mail: Tobias.Kirsten@eu.necel.com
Thomas Kropf , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 Tübingen - Germany. E-mail: kropf@informatik.uni-tuebingen.de
Wolfgang Rosenstiel , University of Tübingen, Department of Computer Engineering - Sand 13, 72076 Tübingen - Germany. E-mail: rosenstiel@informatik.uni-tuebingen.de
pp. 164-169

A Novel Approach for EMI Design of Power Electronics (Abstract)

Bernd Stube , Mentor Graphics Corporation, System Design Division, Berlin, Germany. Bernd_Stube@mentor.com
Eckart Hoene , Fraunhofer Institute for Reliability and Microintegration, System Design&Integration, Berlin, Germany. Eckart.Hoene@izm.fraunhofer.de
Bernd Schroeder , Mentor Graphics Corporation, System Design Division, Berlin, Germany. Bernd_Schroeder@mentor.com
Andre Lissner , Fraunhofer Institute for Reliability and Microintegration, System Design&Integration, Berlin, Germany. Andre.Lissner@izm.fraunhofer.de
pp. 170-175

Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments (Abstract)

Christopher Claus , Technische Universität München, Lehrstuhl für Integrierte Systeme, Theresienstrasse 90, 80333 München, Germany. christopher.claus@tum.de
Nicolas Alt , Technische Universität München, Lehrstuhl für Integrierte Systeme, Theresienstrasse 90, 80333 München, Germany. n.alt@mytum.de
Walter Stechele , Technische Universität München, Lehrstuhl für Integrierte Systeme, Theresienstrasse 90, 80333 München, Germany. walter.stechele@tum.de
pp. 176-181

Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing (Abstract)

Erik Jan Marinissen , NXP Semiconductors, Corporate Innovation&Technology, Eindhoven, The Netherlands. erik.jan.marinissen@nxp.com
Ozgur Sinanoglu , Kuwait University, Math&Computer Science Dept., Safat, Kuwait. ozgur@sci.kuniv.edu.kw
pp. 182-187

Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns (Abstract)

Erik Larsson , Embedded Systems Laboratory, Linköpings Universitet, SE-582 83 Linköping, Sweden
Petru Eles , Embedded Systems Laboratory, Linköpings Universitet, SE-582 83 Linköping, Sweden
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham NC 27708, USA
Anders Larsson , Embedded Systems Laboratory, Linköpings Universitet, SE-582 83 Linköping, Sweden
Zebo Peng , Embedded Systems Laboratory, Linköpings Universitet, SE-582 83 Linköping, Sweden
pp. 188-193

An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers (Abstract)

M. Sonza Reorda , Dipartimento di automatica e Informatica, Politecnico di Torino, IT
P. Bernardi , Dipartimento di automatica e Informatica, Politecnico di Torino, IT
pp. 194-199

Performance Analysis of SoC Architectures Based on Latency-Rate Servers (Abstract)

Pieter van der Wolf , NXP Semiconductors Research, Eindhoven, the Netherlands. E-mail: pieter.van.der.wolf@nxp.com
Jelte Peter Vink , Eindhoven University of Technology, Eindhoven, the Netherlands. E-mail: jelte.peter.vink@philips.com
Kees van Berkel , NXP Semiconductors Research, Eindhoven, the Netherlands. E-mail: kees.van.berkel@nxp.com
pp. 200-205

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs (Abstract)

Rolf Drechsler , Dept. of Computer Science, University of Bremen, Germany. drechsle@informatik.uni-bremen.de
Sujan Pandey , NXP Semiconductors Research, Eindhoven, The Netherlands. sujan.pandey@nxp.com
pp. 206-211

Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC) (Abstract)

Jan Kuper , University of Twente, Department of Electrical Engineering, Mathematics and Computer Science, P.O. Box 217, 7500 AE Enschede, The Netherlands
Philip K.F. Holzenspies , University of Twente, Department of Electrical Engineering, Mathematics and Computer Science, P.O. Box 217, 7500 AE Enschede, The Netherlands. p.k.f.holzenspies@utwente.nl
Johann L. Hurink , University of Twente, Department of Electrical Engineering, Mathematics and Computer Science, P.O. Box 217, 7500 AE Enschede, The Netherlands
Gerard J.M. Smit , University of Twente, Department of Electrical Engineering, Mathematics and Computer Science, P.O. Box 217, 7500 AE Enschede, The Netherlands
pp. 212-217

Architecture Exploration of NAND Flash-based Multimedia Card (Abstract)

Sungchan Kim , School of EECS, Seoul National University, Korea. sungchan.kim@iris.snu.ac.kr
Soonhoi Ha , School of EECS, Seoul National University, Korea. sha@iris.snu.ac.kr
Chanik Park , Memory division, Semiconductor Business, Samsung Electronics Co., Korea. ci.park@samsung.com
pp. 218-223

Resilient Dynamic Power Management under Uncertainty (Abstract)

Hwisung Jung , Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089. hwijung@usc.edu
Massoud Pedram , Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089. pedram@usc.edu
pp. 224-229

Robust and Low Complexity Rate Control for Solar Powered Sensors (Abstract)

Clemens Moser , Swiss Federal Institute of Technology Zurich. moser@tik.ee.ethz.ch
Davide Brunelli , University of Bologna. dbrunelli@deis.unibo.it
Lothar Thiele , Swiss Federal Institute of Technology Zurich. thiele@tik.ee.ethz.ch
Luca Benini , University of Bologna. lbenini@deis.unibo.it
pp. 230-235

Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting (Abstract)

Qinru Qiu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, New York 13902, USA. qqiu@binghamton.edu
Shaobo Liu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, New York 13902, USA. sliu5@binghamton.edu
Qing Wu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, New York 13902, USA. qwu@binghamton.edu
pp. 236-241

Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution (Abstract)

Sungpack Hong , EE Department, Stanford University
Taehwan Kim , EECS, Seoul National University
Sungjoo Yoo , Samsung Electronics
Soo-Kwan Eo , Samsung Electronics
Byeong Bin , Samsung Electronics
Kyu-Myung Choi , Samsung Electronics
pp. 242-247

Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs (Abstract)

Robert P. Dick , Department of EECS, Northwestern University, Evanston, IL 60208. dickrp@northwestern.edu
Thidapat Chantem , Department of CSE, University of Notre Dame, Notre Dame, IN 46556. tchantem@nd.edu
X. Sharon Hu , Department of CSE, University of Notre Dame, Notre Dame, IN 46556. shu@nd.edu
pp. 288-293

A Formal Approach To The Protocol Converter Problem (Abstract)

Sri Parameswaran , The University of NSW, Sydney, Australia. sridevan@cse.unsw.edu.au
Karin Avnit , The University of NSW, Sydney, Australia. kavnit@cse.unsw.edu.au
S. Ramesh , GM India Science Lab, Bangalore India. rameshari1958@gmail.com
Vijay D'Silva , ETH, Zurich, Switzerland. vdsilva@inf.ethz.ch
Arcot Sowmya , The University of NSW, Sydney, Australia. sowmya@cse.unsw.edu.au
pp. 294-299

Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip (Abstract)

Arno Moonen , University of Technology, Eindhoven, The Netherlands. A.J.M.Moonen@tue.nl
Marco Bekooij , NXP Semiconductors, The Netherlands
Rene van den Berg , NXP Semiconductors, The Netherlands
Jef van Meerbergen , University of Technology, Eindhoven, The Netherlands; Philips Research, Eindhoven, The Netherlands
pp. 300-305

Synthesizing Synchronous Elastic Flow Networks (Abstract)

Forrest Brewer , University of California, Santa Barbara. forrest@ece.ucsb.edu
Greg Hoover , University of California, Santa Barbara. ghoover@ece.ucsb.edu
pp. 306-311

Periodic Steady-State Analysis Augmented with Design Equality Constraints (Abstract)

Un-Ku Moon , Oregon State University, Corvallis, Oregon, USA
Pavan Kumar Hanumolu , Oregon State University, Corvallis, Oregon, USA
Igor Vytyaz , Oregon State University, Corvallis, Oregon, USA
Kartikeya Mayaram , Oregon State University, Corvallis, Oregon, USA
pp. 312-317

Analysis of Oscillator Injection Locking by Harmonic Balance Method (Abstract)

S.L. Ulyanov , IPPM, Russian Academy of Sciences, 3 Sovetskaya str., Moscow, Russia
M.M. Gourary , IPPM, Russian Academy of Sciences, 3 Sovetskaya str., Moscow, Russia
K.K. Gullapalli , Freescale Semiconductor Inc., 7700 W. Parmer Lane, Austin, Texas, USA
B.J. Mulvaney , Freescale Semiconductor Inc., 7700 W. Parmer Lane, Austin, Texas, USA, brian.mulvaney@freescale.com
M.M. Zharov , IPPM, Russian Academy of Sciences, 3 Sovetskaya str., Moscow, Russia
S.G. Rusakov , IPPM, Russian Academy of Sciences, 3 Sovetskaya str., Moscow, Russia, rusakov@ippm.ru
pp. 318-323

Model Checking of Analog Systems using an Analog Specification Language (Abstract)

Sebastian Steinhorst , Department of Computer Science, University of Frankfurt/Main, Germany. steinhorst@em.cs.uni-frankfurt.de
Lars Hedrich , Department of Computer Science, University of Frankfurt/Main, Germany. hedrich@em.cs.uni-frankfurt.de
pp. 324-329

Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components (Abstract)

Hugues Balp , Thales Communications S.A., Colombes, France. hugues.balp@fr.thalesgroup.com
Francois Verdier , ETIS Lab - UMR CNRS 8051, Cergy-Pontoise, France. verdier@ensea.fr
Michel Sarlotte , Thales Communications S.A., Colombes, France. michel.sarlotte@fr.thalesgroup.com
Gregory Gailliard , Thales Communications S.A., Colombes, France. gregory.gailliard@fr.thalesgroup.com
pp. 330-335

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications (Abstract)

M. Aguirre , Universidad de Sevilla, Departamento de Ingeniería Electrónica, Sevilla, Spain. aguirre@gtex10.us.es
L. Sterpone , Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy. luca.sterpone@polito.it
H. Guzman-Miranda , Universidad de Sevilla, Departamento de Ingeniería Electrónica, Sevilla, Spain. hipolito@gtex10.us.es
J. Tombs , Universidad de Sevilla, Departamento de Ingeniería Electrónica, Sevilla, Spain. jon@gtex10.us.es
pp. 336-341

Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring (Abstract)

Massimiliano Melani , Department of Information Engineering, University of Pisa, Via Caruso, 56122, Pisa, Italy
Luca Fanucci , Department of Information Engineering, University of Pisa, Via Caruso, 56122, Pisa, Italy
Francesco D'Ascoli , Department of Information Engineering, University of Pisa, Via Caruso, 56122, Pisa, Italy
Peter Lange , Fraunhofer Institute for Silicon Technology ISIT, Fraunhoferstrasse 1, D-25524, Itzehoe, Germany
Marco De Marinis , SensorDynamics AG, Via Giuntini 25, I-56123 Navacchio (Pisa), Italy
Lorenzo Bertini , SensorDynamics AG, Via Giuntini 25, I-56123 Navacchio (Pisa), Italy
pp. 342-347

Guiding Circuit Level Fault-Tolerance Design with Statistical Methods (Abstract)

Drew C. Ness , University of Minnesota, Department of Scientific Computation, EECS building, 200 Union St SE, Minneapolis, MN, 55455-0167. dness@ece.umn.edu
David J. Lilja , University of Minnesota, Department of Scientific Computation, EECS building, 200 Union St SE, Minneapolis, MN, 55455-0167; University of Minnesota, Department of Electrical and Co
pp. 348-353

A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements (Abstract)

Rajesh Garg , Department of EE, Texas A&M University, College Station TX 77843.
Charu Nagpal , Department of EE, Texas A&M University, College Station TX 77843.
Sunil P Khatri , Department of EE, Texas A&M University, College Station TX 77843.
pp. 354-359

Towards fault tolerant parallel prefix adders in nanoelectronic systems (Abstract)

Alex Orailoglu , UC San Diego, CSE Department. alex@cs.ucsd.edu
Wenjing Rao , UC San Diego, CSE Department. wrao@cs.ucsd.edu
pp. 360-365

A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking (Abstract)

Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907. kaushik@ecn.purdue.edu
Patrick Ndai , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907. pndai@ecn.purdue.edu
Swaroop Ghosh , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907. ghosh3@ecn.purdue.edu
pp. 366-371

Embedded Tutorial - Software for Wireless Networked Embedded Systems (PDF)

M Beigl , TU Braunschweig, Germany
J Beutel , ETH Zurich, Switzerland
A Dunkels , Swedish Institute of Computer Science, Kista, Sweden
J Beutel , ETH Zurich, Switzerland
K Langendoen , TU Delft, The Netherlands
pp. 372

Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction (Abstract)

Swarup Bhunia , Dept. of EECS, Case Western Reserve University, Cleveland, USA
Lawrence Leinweber , Dept. of EECS, Case Western Reserve University, Cleveland, USA. lawrence.leinweber@case.edu
pp. 373-378

A Scalable Algorithmic Framework for Row-Based Power-Gating (Abstract)

A. Sathanur , Politecnico di Torino
L. Benini , Università di Bologna
M. Poncino , Politecnico di Torino
A. Pullini , Politecnico di Torino
E. Macii , Politecnico di Torino
A. Macii , Politecnico di Torino
pp. 379-384

Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting (Abstract)

Ehsan Pakbaznia , University of Southern California. pakbazni@usc.edu
Massoud Pedram , University of Southern California. pedram@usc.edu
pp. 385-390

Physical Architectures of Automotive Systems (Abstract)

A. Ferrari , Parades, Roma, IT
A. Sangiovanni-Vincentelli , Univ. of California Berkeley, CA
T. Forest , GM Research, Warren, MI
M. Di Natale , Scuola S. Anna, Pisa, IT
M. Sabatini , Pirelli Tyre SpA, Milano, IT
G. Audisio , Pirelli Tyre SpA, Milano, IT
pp. 391-395

A Mutation Model for the SystemC TLM 2.0 Communication Interfaces (Abstract)

Nicola Bombieri , Dipartimento di Informatica, Università di Verona, Italy. nicola.bombieri@univr.it
Franco Fummi , Dipartimento di Informatica, Università di Verona, Italy. franco.fummi@univr.it
Graziano Pravadelli , Dipartimento di Informatica, Università di Verona, Italy. graziano.pravadelli@univr.it
pp. 396-401

Efficient Design Validation Based on Cultural Algorithms (Abstract)

Michael S. Hsiao , Dept. of Electrical&Computer Engineering, Virginia Tech, Blacksburg, VA. mhsiao@vt.edu
Weixin Wu , Dept. of Electrical&Computer Engineering, Virginia Tech, Blacksburg, VA. wuw@vt.edu
pp. 402-407

Algorithms for Maximum Satisfiability using Unsatisfiable Cores (Abstract)

Joao Marques-Silva , University of Southampton, Electronics&Computer Science, Southampton, UK. jpms@ecs.soton.ac.uk
Jordi Planes , University of Southampton, Electronics&Computer Science, Southampton, UK. jp3@ecs.soton.ac.uk
pp. 408-413

In-band Cross-Trigger Event Transmission for Transaction-Based Debug (Abstract)

Qiang Xu , Department of Computer Science&Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: qxu@cse.cuhk.edu.hk
Shan Tang , Department of Computer Science&Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: tangs@cse.cuhk.edu.hk
pp. 414-419

Efficient Representation and Analysis of Power Grids (Abstract)

Joel R. Phillips , Cadence Research Labs, Cadence Design Systems, Berkeley, California, U.S.A. jrp@cadence.com
L. Miguel Silveira , INESC ID / Cadence Research Labs, IST - TU Lisbon, Lisboa, Portugal. lms@inesc-id.pt
Joao M. S. Silva , INESC ID, IST - TU Lisbon, Lisboa, Portugal. jmss@algos.inesc-id.pt
pp. 420-425

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate (Abstract)

Navin Srivastava , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106
Roberto Suaya , Mentor Graphics, 38334 St. Ismier, Grenoble, France
Kaustav Banerjee , Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106
pp. 426-431

ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis (Abstract)

Duo Li , Dept. of Electrical Engineering, University of California, Riverside, CA 92521. dli@ee.ucr.edu
Sheldon X.-D. Tan , Dept. of Electrical Engineering, University of California, Riverside, CA 92521. stan@ee.ucr.edu
Bruce McGaughy , Cadence Design Systems Inc., San Jose, CA 95134
pp. 432-437

Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods (Abstract)

Alex Yakovlev , School of EECE, Newcastle University, UK
Basel Halak , School of EECE, Newcastle University, UK
pp. 438-443

Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures (Abstract)

Bruno Bougard , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: bougardb@imec.be
Francky Catthoor , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: catthoor@imec.be
Weiyu Xu , Department of EE, Caltech, CA, USA. Email: weiyu@caltech.edu
Liesbet Van Der Perre , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: vdperre@imec.be
Min Li , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: limin@imec.be
David Novo , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: novo@imec.be
pp. 444-449

Vectorization of Reed Solomon Decoding and Mapping on the EVP (Abstract)

Akash Kumar , Eindhoven University of Technology, Eindhoven, The Netherlands. a.kumar@tue.nl
Kees van Berkel , Eindhoven University of Technology, Eindhoven, The Netherlands; NXP Semiconductors, Eindhoven, The Netherlands
pp. 450-455

A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder (Abstract)

Norbert Wehn , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany. wehn@eit.uni-kl.de
Matthias May , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany. may@eit.uni-kl.de
Matthias Alles , Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany. alles@eit.uni-kl.de
pp. 456-461

Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction (Abstract)

Anshuman Chandra , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA
Felix Ng , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA
Rohit Kapur , Synopsys, Inc., 700 E. Middlefield Rd., Mountain View, CA
pp. 462-467

Scan Chain Organization for Embedded Diagnosis (Abstract)

Melanie Elm , Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, D-70569 Stuttgart, Germany. elm@iti.uni-stuttgart.de
Hans-Joachim Wunderlich , Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, D-70569 Stuttgart, Germany. wu@iti.uni-stuttgart.de
pp. 468-473

State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores (Abstract)

V. Tenentes , Computer Science Department, University of Ioannina, Greece. tenentes@uoi.gr
X. Kavousianos , Computer Science Department, University of Ioannina, Greece. kabousia@cs.uoi.gr
E. Kalligeros , Information&Communication Systems Engineering Dept., University of the Aegean, Greece. kalliger@aegean.gr
pp. 474-479

Automated Testability Enhancements for Logic Brick Libraries (Abstract)

R. D. Blanton , Center for Silicon System Implementation, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213. blanton@ece.cmu.edu
Jason G. Brown , Center for Silicon System Implementation, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213. jgbrown@ece.cmu.edu
Larry Pileggi , Center for Silicon System Implementation, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213. pileggi@ece.cmu.edu
Brian Taylor , Center for Silicon System Implementation, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213. briant@ece.cmu.edu
pp. 480-485

A Game-Theoretic Approach to Real-Time System Testing (Abstract)

Alexandre David , Center for Embedded Software Systems (CISS), Aalborg University, DK-9220 Aalborg, Denmark. adavid@cs.aau.dk
Kim G. Larsen , Center for Embedded Software Systems (CISS), Aalborg University, DK-9220 Aalborg, Denmark. kgl@cs.aau.dk
Brian Nielsen , Center for Embedded Software Systems (CISS), Aalborg University, DK-9220 Aalborg, Denmark. bnielsen@cs.aau.dk
Shuhao Li , Center for Embedded Software Systems (CISS), Aalborg University, DK-9220 Aalborg, Denmark. li@cs.aau.dk
pp. 486-491

Modeling Event Stream Hierarchies with Hierarchical Event Models (Abstract)

Jonas Rox , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, D-38106 Braunschweig / Germany. rox@ida.ing.tu-bs.de
Rolf Ernst , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, D-38106 Braunschweig / Germany. ernst@ida.ing.tu-bs.de
pp. 492-497

Semantics for Model-Based Validation of Continuous/Discrete Systems (Abstract)

G. Nicolescu , Ecole Polytechnique de Montreal, Montreal, Canada. gabriela.nicolescu@polymtl.ca
L. Gheorghe , Ecole Polytechnique de Montreal, Montreal, Canada. luiza.gheorghe@polymtl.ca
H. Boucheneb , Ecole Polytechnique de Montreal, Montreal, Canada
F. Bouchhima , Ecole Polytechnique de Montreal, Montreal, Canada
pp. 498-503

Using UML as Front-end for Heterogeneous Software Code Generation Strategies (Abstract)

Flavio Wagner , Institute of Informatics- Federal University of Rio Grande do Sul. flavio@inf.ufrgs.br
Ricardo Redin , Institute of Informatics- Federal University of Rio Grande do Sul. rmredin@inf.ufrgs.br
Luigi Carro , Institute of Informatics- Federal University of Rio Grande do Sul. carro@inf.ufrgs.br
Lisane B. Brisolara , Institute of Informatics- Federal University of Rio Grande do Sul. lisane@inf.ufrgs.br
Luis C. Lamb , Institute of Informatics- Federal University of Rio Grande do Sul. lamb@inf.ufrgs.br
Marcio F.S. Oliveira , Institute of Informatics- Federal University of Rio Grande do Sul. mfsoliveira@inf.ufrgs.br
pp. 504-509

Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm (PDF)

J Hartmann , STMicroelectronics, France
R Lauwereins , IMEC, Belgium
P Wintermayr , Elektronik.net, Germany
V Kiefer , Qimonda, Germany
S Turnoy , Synopsys, USA
R Aitken , ARM, USA
J Tracy Weed , Synopsys, USA
pp. 510

Software Components for Reliable Automotive Systems (Abstract)

M. Di Natale , Scuola Superiore Anna, Pisa, Italy
H. Heinecke , BMW Car IT GmbH, Munich, Germany
A. Metzner , OFFIS, Oldenburg, Germany
B. Josko , OFFIS, Oldenburg, Germany
W. Damm , OFFIS, Oldenburg, Germany
H. Kopetz , Technical University of Vienna, Wien, Austria
A. Sangiovanni-Vincentelli , Univ. of California Berkeley, Berkeley, CA, USA
pp. 549-554

Model-Based-Design Is Nice But... (PDF)

Herbert Hanselmann , dSPACE GmbH, Germany
pp. 555

A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems (Abstract)

Petru Eles , Department of Computer and Information Science, Linköpings universitet, Sweden. petel@ida.liu.se
Soheil Samii , Department of Computer and Information Science, Linköpings universitet, Sweden. sohsa@ida.liu.se
Sergiu Rafiliu , Department of Computer and Information Science, Linköpings universitet, Sweden. serra@ida.liu.se
Zebo Peng , Department of Computer and Information Science, Linköpings universitet, Sweden. zpe@ida.liu.se
pp. 556-561

Signal Probability Based Statistical Timing Analysis (Abstract)

Bao Liu , University of California, San Diego, Computer Science and Engineering Department, 9500 Gilman Dr., La Jolla, CA 92093-0114. Email: bliu@cs.ucsd.edu
pp. 562-567

A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect (Abstract)

Behnam Amelifard , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles CA 90089. amelifar@usc.edu
Hanif Fatemi , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles CA 90089. fatemi@usc.edu
Massoud Pedram , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles CA 90089. pedram@usc.edu
Safar Hatami , Department of Electrical Engineering-Systems, University of Southern California, Los Angeles CA 90089. shatami@usc.edu
pp. 568-573

Current source based standard cell model for accurate signal integrity and timing analysis (Abstract)

Sarma Vrudhula , Consortium for Embedded Systems, Arizona State University, Tempe, AZ 85281, USA
Amit Goel , Consortium for Embedded Systems, Arizona State University, Tempe, AZ 85281, USA
pp. 574-579

An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation (Abstract)

Jinjun Xiong , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598, USA
Wenjian Yu , Dept. Computer Science&Technology, Tsinghua University, Beijing 100084, China
Zeyi Wang , Dept. Computer Science&Technology, Tsinghua University, Beijing 100084, China
Wangyang Zhang , Dept. Computer Science&Technology, Tsinghua University, Beijing 100084, China
Zhiping Yu , Institute of Microelectronics, Tsinghua University, Beijing 100084, China
Rong Jiang , Cadence Design Systems Inc., San Jose, CA 95131, USA
pp. 580-585

SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction (Abstract)

L. Miguel Silveira , INESC ID / IST / Cadence Research Labs, TU Lisbon, Portugal. lms@inesc-id.pt
Jorge Fernandez Villena , INESC ID / IST, TU Lisbon, Portugal. jorge.fernandez@inesc-id.pt
pp. 586-591

Transistor-Specific Delay Modeling for SSTA (Abstract)

David Blaauw , blaauw@umich.edu
Andres Torres , andres_torres@mentor.com
Savithri Sundareswaran , Savithri.Sundareswaran@freescale.com
Brian Cline , btcline@umich.edu
Kaviraj Chopra , kaviraj@umich.edu
pp. 592-597

Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications (Abstract)

Min Li , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: limin@imec.be
David Novo , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: novo@imec.be
Francky Catthoor , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: catthoor@imec.be
Bruno Bougard , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: bougardb@imec.be
Liesbet Van Der Perre , Nomadic Embedded System Division, IMEC, Leuven, Belgium. Email: vdperre@imec.be
pp. 598-603

A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms (Abstract)

Timo Stripf , Universitaet Karlsruhe, Institut fuer Technik der Informationsverarbeitung. stripf@itiv.uni-karlsruhe.de
Ralf Koenig , Universitaet Karlsruhe, Institut fuer Technik der Informationsverarbeitung. koenig@itiv.uni-karlsruhe.de
Juergen Becker , Universitaet Karlsruhe, Institut fuer Technik der Informationsverarbeitung. becker@itiv.uni-karlsruhe.de
pp. 604-609

Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA (Abstract)

Pascal Gauget , Thales Optronique SA, rue Guynemer, 78283 Guyancourt, France. pascal.gauget@fr.thalesgroup.com
Philippe Bonnot , Thales Research&Technology, RD 128, 91767 Palaiseau, France. philippe.bonnot@thalesgroup.com
Gerard Gaillat , Thales Optronique SA, rue Guynemer, 78283 Guyancourt, France. gerard.gaillat@fr.thalesgroup.com
Gilbert Edelin , Thales Research&Technology, RD 128, 91767 Palaiseau, France. gilbert.edelin@thalesgroup.com
Fabrice Lemonnier , Thales Research&Technology, RD 128, 91767 Palaiseau, France. fabrice.lemonnier@thalesgroup.com
Olivier Ruch , Thales Optronique SA, rue Guynemer, 78283 Guyancourt, France. olivier.ruch@fr.thalesgroup.com
pp. 610-615

On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits (Abstract)

Alodeep Sanyal , University of Massachusetts at Amherst
Sandip Kundu , University of Massachusetts at Amherst
Aswin Sreedhar , University of Massachusetts at Amherst
pp. 616-621

Optimal Margin Computation for At-Speed Test (Abstract)

Peter A. Habitz , IBM Systems and Technology Group, Essex Junction, VT 05452. habitz@us.ibm.com
Chandu Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. chandu@us.ibm.com
Jinjun Xiong , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. jinjun@us.ibm.com
Vladimir Zolotov , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. zolotov@us.ibm.com
pp. 622-627

Resistive Bridging Fault Simulation of Industrial Circuits (Abstract)

Juergen Schloeffel , NXP Semiconductors GmbH, Design Technology Center, Georg-Heyken-Str. 1, D-21147 Hamburg, Germany. juergen.schloeffel@nxp.com
Bernd Becker , Albert-Ludwigs-University, Institute for Computer Science, Georges-Köhler-Allee 51, 79110 Freiburg im Breisgau, Germany. becker@informatik.uni-freiburg.de
Ilia Polian , Albert-Ludwigs-University, Institute for Computer Science, Georges-Köhler-Allee 51, 79110 Freiburg im Breisgau, Germany. polian@informatik.uni-freiburg.de
Piet Engelke , Albert-Ludwigs-University, Institute for Computer Science, Georges-Köhler-Allee 51, 79110 Freiburg im Breisgau, Germany. engelke@informatik.uni-freiburg.de
pp. 628-633

Physically-Aware N-Detect Test Pattern Selection (Abstract)

R. D. Blanton , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213. blanton@ece.cmu.edu
Naresh K. Bhatti , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213
Osei Poku , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213
Yen-Tzu Lin , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15213. yentzul@ece.cmu.edu
pp. 634-639

Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication (Abstract)

Gerard J. M. Smit , University of Twente, Enschede, The Netherlands
Maarten H. Wiggers , University of Twente, Enschede, The Netherlands. m.h.wiggers@utwente.nl
Marco J. G. Bekooij , NXP Semiconductors, Eindhoven, The Netherlands
pp. 640-645

Constraint Refinement for Online Verifiable Cross-Layer System Adaptation (Abstract)

Nikil Dutt , School of Information and Computer Sciences, University of California, Irvine, CA 92697, USA. dutt@ics.uci.edu
Nalini Venkatasubramanian , School of Information and Computer Sciences, University of California, Irvine, CA 92697, USA. nalini@ics.uci.edu
Minyoung Kim , School of Information and Computer Sciences, University of California, Irvine, CA 92697, USA. minyounk@ics.uci.edu
Mark-Oliver Stehr , Computer Science Laboratory, SRI International, Menlo Park, CA 94025, USA. stehr@csl.sri.com
Carolyn Talcott , Computer Science Laboratory, SRI International, Menlo Park, CA 94025, USA. clt@csl.sri.com
pp. 646-651

Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload (Abstract)

Prakash Mukre , Department of Electrical and Computer Engineering, Binghamton University, Binghamton, NY 13902. pmukre1@binghamton.edu
Qing Wu , Department of Electrical and Computer Engineering, Binghamton University, Binghamton, NY 13902. qwu@binghamton.edu
Parth Malani , Department of Electrical and Computer Engineering, Binghamton University, Binghamton, NY 13902. parth@binghamton.edu
Qinru Qiu , Department of Electrical and Computer Engineering, Binghamton University, Binghamton, NY 13902. qqiu@binghamton.edu
pp. 652-657

Embedded Tutorial - ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe (PDF)

L Gide , ENIAC Representative, Thales, France
K Glinos , ENIAC Representative, European Commission, Brussels
D Beenaert , ENIAC Representative, European Commission, Brussels
E Schutz , STMicroelectronics, Belgium
pp. 658

Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures (Abstract)

R Ernst , TU Braunschweig, Braunschweig Germany
R Wilhelm , Saarland University, Saarbrücken, Germany
E. Frank , VaST Systems, Munich, Germany
A. Sangiovanni-Vincentelli , Univ. of California Berkeley, Berkeley, CA, USA
M. Di Natale , Scuola Superiore S. Anna, Pisa, Italy
pp. 659-663

Random Stimulus Generation using Entropy and XOR Constraints (Abstract)

Igor L. Markov , EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. imarkov@umich.edu
Valeria Bertacco , EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. valeria@umich.edu
Stephen M. Plaza , EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. splaza@umich.edu
pp. 664-669

MCjammer: Adaptive Verification for Multi-core Designs (Abstract)

Valeria Bertacco , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, MI 48109. valeria@umich.edu
Ilya Wagner , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, MI 48109. iwagner@umich.edu
pp. 670-675

Efficient Implementation of Native Software Simulation for MPSoC (Abstract)

Xavier Guerin , System-Level Synthesis Group, TIMA Laboratory, 46, Av Félix Viallet, 38031 Grenoble, France
Patrice Gerin , System-Level Synthesis Group, TIMA Laboratory, 46, Av Félix Viallet, 38031 Grenoble, France
Frederic Petrot , System-Level Synthesis Group, TIMA Laboratory, 46, Av Félix Viallet, 38031 Grenoble, France
pp. 676-681

Simulation-Directed Invariant Mining for Software Verification (Abstract)

Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, USA. mhsiao@vt.edu
Xueqi Cheng , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, USA. xcheng@vt.edu
pp. 682-687

Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation (Abstract)

Massoud Momeni , Technische Universität Darmstadt, Department of Electrical Engineering and Information Technology, Institute of Microelectronic Systems, Karlstraße 15, D-64283 Darmstadt, Germany.
Manfred Glesner , Technische Universität Darmstadt, Department of Electrical Engineering and Information Technology, Institute of Microelectronic Systems, Karlstraße 15, D-64283 Darmstadt, Germany.
Petru Bogdan Bacinschi , Technische Universität Darmstadt, Department of Electrical Engineering and Information Technology, Institute of Microelectronic Systems, Karlstraße 15, D-64283 Darmstadt, Germany.
pp. 688-693

A Novel Technique for Improving Temperature Independency of Ring-ADC (Abstract)

Shun Li , ASCI&System State-Key Lab, Fudan University, Shanghai 201203, China
Feng Zhou , ASCI&System State-Key Lab, Fudan University, Shanghai 201203, China. fengzhou@fudan.edu.cn
Hua Chen , ASCI&System State-Key Lab, Fudan University, Shanghai 201203, China
pp. 694-697

An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs (Abstract)

P. B. Bacinschi , Inst. of Microelectronic Systems, Technische Univ. Darmstadt, Karlstr. 15, 64283 Darmstadt, Germany. pbb@mes.tu-darmstadt.de
T. Murgan , Inst. of Microelectronic Systems, Technische Univ. Darmstadt, Karlstr. 15, 64283 Darmstadt, Germany
M. Glesner , Inst. of Microelectronic Systems, Technische Univ. Darmstadt, Karlstr. 15, 64283 Darmstadt, Germany
K. Koch , Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany
pp. 698-703

Integrated approach to energy harvester mixed technology modelling and performance optimisation (Abstract)

Steve P. Beeby , School of Electronics and Computer Science, University of Southampton, UK. spb@ecs.soton.ac.uk
Leran Wang , School of Electronics and Computer Science, University of Southampton, UK. lw04r@ecs.soton.ac.uk
Bashir M. Al-Hashimi , School of Electronics and Computer Science, University of Southampton, UK. bmah@ecs.soton.ac.uk
Tom J. Kazmierski , School of Electronics and Computer Science, University of Southampton, UK. tjk@ecs.soton.ac.uk
Russel N. Torah , School of Electronics and Computer Science, University of Southampton, UK. rnt@ecs.soton.ac.uk
pp. 704-709

A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers (Abstract)

Michael Goffioul , IMEC/Nomadic Embedded Systems, Kapeldreef 75, B-3001 Leuven
Wolfgang Eberle , IMEC/Bioelectronic Systems, Kapeldreef 75, B-3001 Leuven
pp. 710-715

A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio (Abstract)

Sebastien Rabou , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Liesbet Van der Perre , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Steven Dupont , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
David Novo , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Bruno Bougard , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium. E-mail: bruno.bougard@imec.be
Bjorn De Sutter , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Osman Allam , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
pp. 716-721

Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios (Abstract)

D. Novo , IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium; KULeuven, 3000 Leuven, Belgium. novo@imec.be
L. Van der Perre , IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium. vdperre@imec.be
B. Bougard , IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium. bougardb@imec.be
F. Catthoor , IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium; KULeuven, 3000 Leuven, Belgium. catthoor@imec.be
A. Lambrechts , IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium; KULeuven, 3000 Leuven, Belgium. lambreca@imec.be
pp. 722-727

Test Strategies for Low Power Devices (Abstract)

M. Hirech , Synopsys Inc., Mountain View, CA94043, USA
C. P. Ravikumar , Texas Instruments India Pvt. Ltd., Bangalore, India - 560 093
X. Wen , Kyushu Institute of Technology, Iizuka 820-8502, Japan
pp. 728-733

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures (Abstract)

Michele Pittau , DMI-University of Cagliari, 32 Via Ospedale, Cagliari, Italy. pittau@unica.it
Giovanni De Micheli , LSI-EPFL, Lausanne, CH. giovanni.demicheli@epfl.ch
Marco Buttu , DMI-University of Cagliari, 32 Via Ospedale, Cagliari, Italy. buttu@unica.it
Andrea Acquaviva , DI-University of Verona, Strada le Grazie 15, Verona, Italy. andrea.acquaviva@univr.it
David Atienza , LSI-EPFL, Lausanne, CH. david.atienza@epfl.ch
Fabrizio Mulas , DMI-University of Cagliari, 32 Via Ospedale, Cagliari, Italy. mulas@unica.it
Salvatore Carta , DMI-University of Cagliari, 32 Via Ospedale, Cagliari, Italy. salvatore@unica.it
Luca Benini , DEIS - University of Bologna, V.le Risorgimento 2, Bologna, Italy. lbenini@deis.unibo.it
pp. 734-739

A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs (Abstract)

Frederic Arzel , Laboratoire d'informatique de Paris 6, Pierre et Marie Curie University (Paris 6), France
Olivier Temam , Alchemy Project, INRIA Saclay, France
Zheng Li , Alchemy Project, INRIA Saclay, France. E-mail: zheng.x.li@inria.fr
Nathalie Drach , Laboratoire d'informatique de Paris 6, Pierre et Marie Curie University (Paris 6), France
Pierre Palatin , Alchemy Project, INRIA Saclay, France. E-mail: olivier.temam@inria.fr
Olivier Certner , Alchemy Project, INRIA Saclay, France. E-mail: olivier.certner@inria.fr
pp. 740-745

Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis (Abstract)

Soheil Ghiasi , Electrical and Computer Engineering, University of California, Davis, CA 95616, USA. ghiasi@ucdavis.edu
Matin Hashemi , Electrical and Computer Engineering, University of California, Davis, CA 95616, USA. hashemi@ucdavis.edu
pp. 746-751

Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set (Abstract)

Stephanie Kreutz , University of Karlsruhe, CES - Chair for Embedded Systems, Karlsruhe, Germany
Muhammad Shafique , University of Karlsruhe, CES - Chair for Embedded Systems, Karlsruhe, Germany. shafique@informatik.uni-karlsruhe.de
Lars Bauer , University of Karlsruhe, CES - Chair for Embedded Systems, Karlsruhe, Germany. lars.bauer@informatik.uni-karlsruhe.de
Jorg Henkel , University of Karlsruhe, CES - Chair for Embedded Systems, Karlsruhe, Germany. henkel@informatik.uni-karlsruhe.de
pp. 752-757

Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency (Abstract)

Hai Lin , Dept. of Electrical&Computer Engineering, University of Connecticut, Storrs, CT 06269. E-mail: hal06002@engr.uconn.edu
Yunsi Fei , Dept. of Electrical&Computer Engineering, University of Connecticut, Storrs, CT 06269. E-mail: yfei@engr.uconn.edu
pp. 758-763

Instruction Set Extension Exploration in Multiple-Issue Architecture (Abstract)

Jyh-Jiun Shann , Dept. of Computer Science, National Chiao Tung University. jjshann@cs.nctu.edu.tw, shiva.cs94g@nctu.edu.tw
Chung-Ping Chung , Dept. of Computer Science, National Chiao Tung University. cpchung@cs.nctu.edu.tw, shiva.cs94g@nctu.edu.tw
Zhi-Yuan Chen , Dept. of Computer Science, National Chiao Tung University. shiva.cs94g@nctu.edu.tw
I-Wei Wu , Dept. of Computer Science, National Chiao Tung University. wuiw@cs.nctu.edu.tw, shiva.cs94g@nctu.edu.tw
pp. 764-769

Instruction Re-encoding Facilitating Dense Embedded Code (Abstract)

Jorg Henkel , University of Karlsruhe, CES - Chair for Embedded Systems, Karlsruhe, Germany. henkel@informatik.uni-karlsruhe.de
Talal Bonny , University of Karlsruhe, CES - Chair for Embedded Systems, Karlsruhe, Germany. bonny@informatik.uni-karlsruhe.de
pp. 770-775

Panel Session - The Future Car: Technology, Methods and Tools (PDF)

H Fennel , Continental Teves, Germany
A Sangiovanni Vincentelli , UC Berkeley, USA
T Weber , Daimler, Germany
H Heinecke , BMW, Germany
H Kopetz , TU Vienna, Austria
M Di Natale , Pisa, Italy
A Bouali , Esterel, France
Scuola S. Anna , Pisa, Italy
A Sangiovanni Vincentelli , UC Berkeley, USA
H Hanselmann , dSPACE GmbH, Germany
pp. 812

Improving Constant-Coefficient Multiplier Verification by Partial Product Identification (Abstract)

Chung-Yang Huang , Department of Electrical Engineering, National Taiwan University, Taiwan. ric@cc.ee.ntu.edu.tw
Kei-Yong Khoo , Cadence Design Systems, Inc., San José California, USA. khoo@cadence.com
Chao-Yue Lai , Department of Electrical Engineering, National Taiwan University, Taiwan. colby.lai@gmail.com
pp. 813-818

Improved Visibility in One-to-Many Trace Concretization (Abstract)

Kuntal Nanshi , Dept. of Electrical and Computer Engineering, University of Colorado at Boulder
Fabio Somenzi , Dept. of Electrical and Computer Engineering, University of Colorado at Boulder
pp. 819-824

Efficient Symbolic Simulation of Low Level Software (Abstract)

Eli Singerman , Intel Israel Design Center. E-mail: Eli.Singerman@intel.com
Tamarah Arons , Intel Israel Design Center. E-mail: Tamarah.Arons@intel.com
Elad Elster , Intel Israel Design Center. E-mail: Elad.Elster@intel.com
Jonathan Shalev , Intel Israel Design Center. E-mail: Jonathan.Shalev@intel.com
Shlomit Ozer , Intel Israel Design Center. E-mail: Shlomit.Ozer@intel.com
pp. 825-830

Completeness in SMT-based BMC for Software Programs (Abstract)

Aarti Gupta , NEC Labs America, Princeton, NJ 08540. agputa@nec-labs.com
Malay K. Ganai , NEC Labs America, Princeton, NJ 08540. malay@nec-labs.com
pp. 831-836

Novel Pin Assignment Algorithms for Components with Very High Pin Counts (Abstract)

Gisbert Thomke , IBM Research&Development, Boeblingen, Germany. thomke@de.ibm.com
Tilo Meister , Dresden University of Technology, Dresden, Germany. tilo@ieee.org
Jens Lienig , Dresden University of Technology, Dresden, Germany. jens@ieee.org
pp. 837-842

A Generic Standard Cell Design Methodology for Differential Circuit Styles (Abstract)

Frank K. Gurkaynak , Microelectronic Systems Laboratory (LSM) EPFL, CH-1015 Lausanne
Ozgur Inac , Microelectronic Systems Laboratory (LSM) EPFL, CH-1015 Lausanne
Erdem Guleyupoglu , Microelectronic Systems Laboratory (LSM) EPFL, CH-1015 Lausanne
Paolo Vietti , Microelectronic Systems Laboratory (LSM) EPFL, CH-1015 Lausanne
Stephane Badel , Microelectronic Systems Laboratory (LSM) EPFL, CH-1015 Lausanne. E-mail: stephane.badel@epfl.ch
Yusuf Leblebici , Microelectronic Systems Laboratory (LSM) EPFL, CH-1015 Lausanne
Anna Pena Martinez , Microelectronic Systems Laboratory (LSM) EPFL, CH-1015 Lausanne
pp. 843-848

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices (Abstract)

Ashutosh Chakraborty , Department of Electrical and Computer Engineering, The University of Texas at Austin. ashutosh@cerc.utexas.edu
David Z. Pan , Department of Electrical and Computer Engineering, The University of Texas at Austin. dpan@ece.utexas.edu
Sean X. Shi , Department of Electrical and Computer Engineering, The University of Texas at Austin. sean.shi@mail.utexas.edu
pp. 849-855

Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing (Abstract)

Sonia Singhal , Carnegie Mellon University, Pittsburgh, PA, USA. soniasin@ece.cmu.edu
Amith Singhee , Carnegie Mellon University, Pittsburgh, PA, USA. asinghee@ece.cmu.edu
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, PA, USA. rutenbar@ece.cmu.edu
pp. 856-861

A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications (Abstract)

Rocio del Rio , Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Edif. CICA-CNM, Avda. Reina Mercedes s/n, 41012 Sevilla, SPAIN. rocio@imse.cnm.es
Alonso Morgado , Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Edif. CICA-CNM, Avda. Reina Mercedes s/n, 41012 Sevilla, SPAIN. alonso@imse.cnm.es
Jose M. de la Rosa , Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Edif. CICA-CNM, Avda. Reina Mercedes s/n, 41012 Sevilla, SPAIN. jrosa@imse.cnm.es
pp. 862-867

Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement (Abstract)

Johann Hauer , Fraunhofer Institute for Integrated Circuits, 91058 Erlangen, Germany. johann.hauer@iis.fraunhofer.de
Werner Hinn , HSR University of Applied Sciences Rapperswil, 8640 Rapperswil, Switzerland
Robert Dorn , Fraunhofer Institute for Integrated Circuits, 91058 Erlangen, Germany
Teddy Loeliger , HSR University of Applied Sciences Rapperswil, 8640 Rapperswil, Switzerland. teddy.loeliger@hsr.ch
Matthias Volker , Fraunhofer Institute for Integrated Circuits, 91058 Erlangen, Germany
Stefan Modl , Fraunhofer Institute for Integrated Circuits, 91058 Erlangen, Germany
Markus Bingesser , austriamicrosystems AG, Rietstrasse 4, 8640 Rapperswil, Switzerland. markus.bingesser@austriamicrosystems.com
pp. 868-872

Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment (Abstract)

Francois Laulanet , AMI Semiconductor, Belgium
Olivier Charlier , AMI Semiconductor, Belgium
Mustafa Badaroglu , AMI Semiconductor, Belgium
Guy Decabooter , AMI Semiconductor, Belgium
pp. 873-878

A Programmable and Low-EMI Integrated Half-Bridge Driver in BCD Technology (Abstract)

M. Melani , Dept. of Information Engineering, University of Pisa, Pisa, Italy
M. De Marinis , SensorDynamics AG, Navacchio (Pisa), Italy
M. Forliti , SensorDynamics AG, Navacchio (Pisa), Italy
L. Fanucci , Dept. of Information Engineering, University of Pisa, Pisa, Italy
F. Vincis , SensorDynamics AG, Navacchio (Pisa), Italy
L. Bacciarelli , Dept. of Information Engineering, University of Pisa, Pisa, Italy
F. D'Ascoli , Dept. of Information Engineering, University of Pisa, Pisa, Italy
E. Pardi , SensorDynamics AG, Navacchio (Pisa), Italy
G. Ricotti , STMicroelectronics, Cornaredo (Milano), Italy
pp. 879-884

CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns (Abstract)

Yanjing Li , Stanford University
Subhasish Mitra , Stanford University
Samy Makar , CSwitch Corporation
pp. 885-890

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology (Abstract)

Yinhe Han , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences. yinhes@ict.ac.cn
Lei Zhang , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences. zlei@ict.ac.cn
Qiang Xu , Department of Computer Science&Engineering, The Chinese University of Hong Kong. qxu@cse.cuhk.edu.hk
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences. lxw@ict.ac.cn
pp. 891-896

A low-cost concurrent error detection technique for processor control logic (Abstract)

Abhijit Jas , Design and Technology Solutions, Intel Corporation. ajas@intel.com
Srinivas Patil , Design and Technology Solutions, Intel Corporation. spatil@intel.com
Ramtilak Vemu , Computer Engineering Research Center, University of Texas at Austin. rvemu@cerc.utexas.edu
Rajesh Galivanche , Design and Technology Solutions, Intel Corporation. rgalivanche@intel.com
Jacob A. Abraham , Computer Engineering Research Center, University of Texas at Austin. jaa@cerc.utexas.edu
pp. 897-902

Approximate logic circuits for low overhead, non-intrusive concurrent error detection (Abstract)

Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. kmram@rice.edu
Mihir R. Choudhury , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. mihir@rice.edu
pp. 903-908

Logical Reliability of Interacting Real-Time Tasks (Abstract)

Claudio Pinello , Cadence Research Labs. pinello@cadence.com
Daniel Iercan , "Politehnica" U. of Timisoara. daniel.iercan@aut.upt.ro
Christoph M. Kirsch , University of Salzburg. ck@cs.uni-salzburg.at
Krishnendu Chatterjee , UC Berkeley. c_krish@eecs.berkeley.edu
Arkadeb Ghosal , UC Berkeley. arkadeb@eecs.berkeley.edu
Thomas A. Henzinger , EPFL. tah@epfl.ch
Alberto Sangiovanni-Vincentelli , UC Berkeley. alberto@eecs.berkeley.edu
pp. 909-914

Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints (Abstract)

Viacheslav Izosimov , Dept. of Computer and Information Science, Linköping University. viaiz@ida.liu.se
Petru Eles , Dept. of Computer and Information Science, Linköping University. petel@ida.liu.se
Paul Pop , Dept. of Informatics and Mathematical Modelling, Technical University of Denmark. Paul.Pop@imm.dtu.dk
Zebo Peng , Dept. of Computer and Information Science, Linköping University. zebpe@ida.liu.se
pp. 915-920

Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems (Abstract)

Simin Nadjm-Tehrani , Department of Computer and Information Science, Linköping University, Linköping, Sweden. simin@ida.liu.se
Jonas Elmqvist , Department of Computer and Information Science, Linköping University, Linköping, Sweden. jonel@ida.liu.se
pp. 921-927

Compositional design of isochronous systems (Abstract)

Julien Ouy , INRIA, Unité de Recherche Rennes-Bretagne-Atlantique, IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
Jean-Pierre Talpin , INRIA, Unité de Recherche Rennes-Bretagne-Atlantique, IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
Loic Besnard , INRIA, Unité de Recherche Rennes-Bretagne-Atlantique, IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
Paul Le Guernic , CNRS, UMR 6074, IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
pp. 928-933

Quantitative Productivity Measurement in IC Design (Abstract)

Frank Badstubner , Infineon Technologies AG, DE, (PRODUKTIV+project coordination)
Andreas Vorg , edacentrum GmbH, DE (Project management)
pp. 934-935

Determining the Technical Complexity of Integrated Circuits (Abstract)

Erich Barke , Institute of Microelectronic Systems, EDA Group, Leibniz University Hannover, DE
Peter Leppelt , Institute of Microelectronic Systems, EDA Group, Leibniz University Hannover, DE
pp. 935

Qalitative and Quantitative Analysis of IC Designs (Abstract)

Frank Poppen , OFFIS, University of Oldenburg, Oldenburg, DE
Kevin Hausmann , OFFIS, University of Oldenburg, Oldenburg, DE
Axel Hahn , OFFIS, University of Oldenburg, Oldenburg, DE
Wolfgang Nebel , OFFIS, University of Oldenburg, Oldenburg, DE
Stefan Hausler , OFFIS, University of Oldenburg, Oldenburg, DE
pp. 935-936

Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits (Abstract)

Slava Bulach , GmbH, Wolfgang Rosenstiel, University Tuebingen, DE
Katharina Weinberger , GmbH, Wolfgang Rosenstiel, University Tuebingen, DE
Robert Bosch , GmbH, Wolfgang Rosenstiel, University Tuebingen, DE
pp. 937-938

Implications of Technology Trends on System Dependability (Abstract)

Jacob A. Abraham , The University of Texas at Austin, Austin, Texas, U.S.A. jaa@cerc.utexas.edu
pp. 940

Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges (Abstract)

Subhasish Mitra , Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA
pp. 941-946

Software Protection Mechanisms for Dependable Systems (Abstract)

Ute Wappler , Technische Universtät Dresden. ute.wappler@inf.tu-dresden.de
Martin Muller , Siemens AG, CT SE 2. martin.mueller@siemens.com
pp. 947-952

Subsystem Exchange in a Concurrent Design Process Environment (Abstract)

Paul Williams , Mentor Graphics, UK
Marino Strik , NXP Semiconductors, The Netherlands
Alain Gonier , Mentor Graphics, France
pp. 953-958

Cooperative Safety: a Combination of Multiple Technologies (Abstract)

Edoardo Merli , STMicroelectronics
Martin Duncan , STMicroelectronics
Piergiorgio Capozio , STMicroelectronics
Angelo Scuderi , STMicroelectronics
Raffaele Penazzi , STMicroelectronics
Max Siti , STMicroelectronics
pp. 959-961

System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture (Abstract)

Albrecht Mayer , Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany. albrecht.mayer@infineon.com
Frank Hellwig , Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany. frank.hellwig@infineon.com
pp. 962-966

Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style (Abstract)

Luca Benini , DEIS, University of Bologna, 40136 Bologna, Italy.
Bonesi Stefano , ENDIF, University of Ferrara, 44100 Ferrara, Italy.
Enrico Macii , DAUIN, Politecnico di Torino, 10129 Torino, Italy.
Davide Bertozzi , ENDIF, University of Ferrara, 44100 Ferrara, Italy.
pp. 967-972

Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints (Abstract)

Luca Benini , Università di Bologna
Andrea Calimera , Politecnico di Torino
Enrico Macii , Politecnico di Torino
pp. 973-978

A Single-supply True Voltage Level Shifter (Abstract)

Sunil P Khatri , Department of Electrical&Computer Engineering, Texas A&M University, College Station TX 77843. sunilkhatri@tamu.edu
Rajesh Garg , Department of Electrical&Computer Engineering, Texas A&M University, College Station TX 77843. rajeshgarg@tamu.edu
Gagandeep Mallarapu , Department of Electrical&Computer Engineering, Texas A&M University, College Station TX 77843. gagandeepm@tamu.edu
pp. 979-984

Clock Distribution Scheme using Coplanar Transmission Lines (Abstract)

Victor H. Cordero , Department of ECE, Texas A&M University
Sunil P Khatri , Department of ECE, Texas A&M University
pp. 985-990

Compositional, dynamic cache management for embedded chip multiprocessors (Abstract)

Marc J.M. Heijligers , NXP Semiconductors / Corporate I&T, HTC 37, Eindhoven, The Netherlands. marc.heijligers@nxp.com
Sorin D. Cotofana , Technical University of Delft, Mekelweg 4, Delft, The Netherlands. s.d.cotofana@ewi.tudelft.nl
Anca M. Molnos , NXP Semiconductors / Corporate I&T, HTC 37, Eindhoven, The Netherlands. anca.molnos@nxp.com
pp. 991-996

Comparison of memory write policies for NoC based Multicore Cache Coherent Systems (Abstract)

Pierre Guironnet de Massas , System-Level Synthesis Group, TIMA Laboratory, 46, Av Félix Viallet, 38031 Grenoble, France
Frederic Petrot , System-Level Synthesis Group, TIMA Laboratory, 46, Av Félix Viallet, 38031 Grenoble, France
pp. 997-1002

Serialized Asynchronous Links for NoC (Abstract)

C. D'Alessandro , Newcastle University
A. Yakovlev , Newcastle University
S. Ogg , University of Southampton. so04r@ecs.soton.ac.uk
L. Benini , University of Bologna
B. Al-Hashimi , University of Southampton. bmah@ecs.soton.ac.uk
E. Valli , University of Bologna
pp. 1003-1008

Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits (Abstract)

Nishant P. Patil , Stanford University, Stanford, CA
Jie Zhang , Stanford University, Stanford, CA
Subhasish Mitra , Stanford University, Stanford, CA
pp. 1009-1014

Quantified Synthesis of Reversible Logic (Abstract)

Hoang M. Le , Group for Computer Architecture (Prof. Dr. Rolf Drechsler), University of Bremen, 28359 Bremen, Germany. hle@informatik.uni-bremen.de
Daniel GroBe , Group for Computer Architecture (Prof. Dr. Rolf Drechsler), University of Bremen, 28359 Bremen, Germany. grosse@informatik.uni-bremen.de
Robert Wille , Group for Computer Architecture (Prof. Dr. Rolf Drechsler), University of Bremen, 28359 Bremen, Germany. rwille@informatik.uni-bremen.de
Gerhard W. Dueck , Faculty of Computer Science, University of New Brunswick, Fredericton, NB, Canada. gdueck@unb.ca
pp. 1015-1020

Adaptive Simulation for Single-Electron Devices (Abstract)

Robert Knobel , Physics Department, Queen's University, Kingston, ON K7L 3N6, Canada. knobel@physics.queensu.ca
Li Shang , ECE Department, University of Colorado at Boulder, Boulder, CO 80309, U.S.A. li.shang@colorado.edu
Nicholas Allec , ECE Department, Queen's University, Kingston, ON K7L 3N6, Canada. nicholas.allec@ece.queensu.ca
pp. 1021-1026

OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks (Abstract)

Julien Penders , IMEC-NL, Eindhoven, The Netherlands. E-mail: julien.penders@imec-nl.nl
Michele Paselli , IMEC-NL, Eindhoven, The Netherlands. E-mail: michele.paselli@imec-nl.nl
Francisco J. Rincon , DACYA/Universidad Complutense, Madrid, Spain. E-mail: francisco.rincon@fdi.ucm.es
Marcos Sanchez-Elez , DACYA/Universidad Complutense, Madrid, Spain. E-mail: marcos@fis.ucm.es
David Atienza , DACYA/Universidad Complutense, Madrid, Spain; LSI/EPFL, Lausanne, Switzerland. E-mail: datienza@dacya.ucm.es, david.atienza@epfl.ch
Joaquin Recas , DACYA/Universidad Complutense, Madrid, Spain. E-mail: jrecas@fis.ucm.es
Qin Zhao , IMEC-NL, Eindhoven, The Netherlands. E-mail: qin.zhao@imec-nl.nl
Giovanni De Micheli , LSI/EPFL, Lausanne, Switzerland. E-mail: giovanni.demicheli@epfl.ch
pp. 1027-1032

Improvements in Polynomial-Time Feasibility Testing for EDF (Abstract)

Alejandro Masrur , Institute for Real-Time Computer Systems, Technische Universität München, Germany. Alejandro.Masrur@rcs.ei.tum.de
Georg Farber , Institute for Real-Time Computer Systems, Technische Universität München, Germany. Georg.Faerber@rcs.ei.tum.de
Sebastian Drossler , Institute for Real-Time Computer Systems, Technische Universität München, Germany. Sebastian.Droessler@rcs.ei.tum.de
pp. 1033-1038

A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications (Abstract)

Gianluca Palermo , Politecnico di Milano - DEI, Via Ponzio 34/5, 20133 Milano, Italy
Matteo Monchiero , HP Labs, 1501 Page Mill Rd., Palo Alto 94304 CA, USA
Marco Branca , Politecnico di Milano - DEI, Via Ponzio 34/5, 20133 Milano, Italy
Fabrizio Ferrandi , Politecnico di Milano - DEI, Via Ponzio 34/5, 20133 Milano, Italy
Marco Ceriani , Politecnico di Milano - DEI, Via Ponzio 34/5, 20133 Milano, Italy
Donatella Sciuto , Politecnico di Milano - DEI, Via Ponzio 34/5, 20133 Milano, Italy
Antonino Tumeo , Politecnico di Milano - DEI, Via Ponzio 34/5, 20133 Milano, Italy
Lorenzo Camerini , Politecnico di Milano - DEI, Via Ponzio 34/5, 20133 Milano, Italy
pp. 1039-1044

An application-based EDF scheduler for OSEK/VDX (Abstract)

Frank Slomka , University of Ulm, 89069 Ulm, Germany. frank.slomka@uni-ulm.de
Gerhard Wirrer , SiemensVDO AG, 93055 Regensburg. gerhard.wirrer@siemens.com
Claas Diederichs , INCHRON GmbH, 14482 Potsdam, Germany. claas.diederichs@inchron.de
Ulrich Margull , 1 mal 1 Software GmbH, 90762 Fürth, Germany. margull@1mal1.com
pp. 1045-1050

Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme (Abstract)

Giorgio C. Buttazzo , Scuola Superiore S. Anna, Italy. giorgio.buttazzo@sssup.it
Gianluca Franchino , University of Pavia, Italy. gianluca.franchino@unipv.it
Tullio Facchinetti , University of Pavia, Italy. tullio.facchinetti@unipv.it
pp. 1051-1056

Simultaneous FU and Register Binding Based on Network Flow Method (Abstract)

Junjuan Xu , UCLA Computer Science Department, Los Angeles, CA 90095, USA. irene.xu@cs.ucla.edu
Jason Cong , UCLA Computer Science Department, Los Angeles, CA 90095, USA. cong@cs.ucla.edu
pp. 1057-1062

A Variation Aware High Level Synthesis Framework (Abstract)

Guangyu Sun , The Pennsylvania State University, University Park, PA, USA. gsun@cse.psu.edu
Yuan Xie , The Pennsylvania State University, University Park, PA, USA. yuanxie@cse.psu.edu
Feng Wang , The Pennsylvania State University, University Park, PA, USA. fenwang@cse.psu.edu
pp. 1063-1068

EPIC: Ending Piracy of Integrated Circuits (Abstract)

Jarrod A. Roy , The University of Michigan, Department of EECS, 2260 Hayward Ave., Ann Arbor, MI 48109-2121
Farinaz Koushanfar , Rice University, ECE and CS Departments, 6100 South Main, Houston, TX 77005
Igor L. Markov , The University of Michigan, Department of EECS, 2260 Hayward Ave., Ann Arbor, MI 48109-2121
pp. 1069-1074

Specification and Design Considerations for Reliable Embedded Systems (Abstract)

Sorin A. Huss , Dept. of Computer Science, TU Darmstadt, Darmstadt, Germany. huss@iss.tu-darmstadt.de
Adeel Israr , Dept. of Computer Science, TU Darmstadt, Darmstadt, Germany. israr@iss.tu-darmstadt.de
pp. 1111-1116

Synthesis of Fault-Tolerant Embedded Systems (Abstract)

Petru Eles , Dept. of Computer and Information Science, Linköping University, SE-581 83 Linköping, Sweden. petel@ida.liu.se
Paul Pop , Dept. of Informatics and Mathematical Modelling, Technical University of Denmark, DK-2800 Kongens Lyngby, Denmark. Paul.Pop@imm.dtu.dk
Viacheslav Izosimov , Dept. of Computer and Information Science, Linköping University, SE-581 83 Linköping, Sweden. viaiz@ida.liu.se
Zebo Peng , Dept. of Computer and Information Science, Linköping University, SE-581 83 Linköping, Sweden. zebpe@ida.liu.se
pp. 1117-1122

Video Processing Requirements on SoC Infrastructures (Abstract)

Tomas Henriksson , NXP Semiconductors Research, Eindhoven, The Netherlands
Pieter van der Wolf , NXP Semiconductors Research, Eindhoven, The Netherlands. pieter.van.der.wolf@nxp.com
pp. 1124-1125

Memory Technology for Extended Large-Scale Integration in Future Electronics Applications (Abstract)

Dinesh Pamunuwa , Centre for Microsystems Engineering, Department of Engineering, Lancaster University, Lancaster, UK. d.pamunuwa@lancaster.ac.uk
pp. 1126-1127

Memory-aware NoC Exploration and Design (Abstract)

Nikil Dutt , Center for Embedded Computer Systems, Donald Bren School of Information and Computer Sciences, University of California, Irvine, CA 92697-3435. dutt@uci.edu
pp. 1128-1129

Incremental Criticality and Yield Gradients (Abstract)

Vladimir Zolotov , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. zolotov@us.ibm.com
Jinjun Xiong , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. jinjun@us.ibm.com
Chandu Visweswariah , IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. chandu@us.ibm.com
pp. 1130-1135

Latch Modeling for Statistical Timing Analysis (Abstract)

David Z. Pan , Department of ECE, University of Texas, Austin TX 78712. dpan@ece.utexas.edu
Daifeng Wang , Department of ECE, University of Texas, Austin TX 78712. wang@ece.utexas.edu
Anand Ramalingam , Department of ECE, University of Texas, Austin TX 78712. anandram@ece.utexas.edu
Sean X. Shi , Department of ECE, University of Texas, Austin TX 78712. xshi@ece.utexas.edu
pp. 1136-1141

Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis (Abstract)

Alex Yakovlev , Microelectronics System Design Group, School of EECE, Newcastle University, UK. alex.yakovlev@ncl.ac.uk
Andrey Mokhov , Microelectronics System Design Group, School of EECE, Newcastle University, UK. andrey.mokhov@ncl.ac.uk
pp. 1142-1147

Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor (Abstract)

Srimat T. Chakradhar , NEC Laboratories America, 4 Independence Way, Princeton, NJ 08540
Anand Raghunathan , NEC Laboratories America, 4 Independence Way, Princeton, NJ 08540
Janar Thoguluva , NEC Laboratories America, 4 Independence Way, Princeton, NJ 08540; Alphion Corporation
pp. 1148-1153

Operating System Controlled Processor-Memory Bus Encryption (Abstract)

Alok Choudhary , Electrical Engineering and Computer Science Department, Northwestern University, 2145 Sheridan Road, Evanston, Illinois 60208
Xi Chen , Electrical Engineering and Computer Science Department, Northwestern University, 2145 Sheridan Road, Evanston, Illinois 60208
Robert P. Dick , Electrical Engineering and Computer Science Department, Northwestern University, 2145 Sheridan Road, Evanston, Illinois 60208
pp. 1154-1159

An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System (Abstract)

Sanchit Misra , Electrical Engineering and Computer Science Department, Northwestern University, Evanston IL, USA
Sumeet Joshi , Department of Electronics and Electrical Communications, Indian Institute of Technology, Kharagpur, India
Abhishek Das , Electrical Engineering and Computer Science Department, Northwestern University, Evanston IL, USA
Joseph Zambreno , Electrical and Computer Engineering Department, Iowa State University, Ames, IA, USA
Alok Choudhary , Electrical Engineering and Computer Science Department, Northwestern University, Evanston IL, USA
Gokhan Memik , Electrical Engineering and Computer Science Department, Northwestern University, Evanston IL, USA
pp. 1160-1165

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy (Abstract)

Sudhakar M. Reddy , Electrical&Computer Eng. Dept., University of Iowa, Iowa City, IA 52242, U.S.A.
Irith Pomeranz , School of Electrical&Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
pp. 1166-1171

Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation (Abstract)

Mike Kapralos , ECE Department, University of Connecticut. mikepk@engr.uconn.edu
Sumit Narayan , ECE Department, University of Connecticut. sumitn@engr.uconn.edu
Mohammad Tehranipoor , ECE Department, University of Connecticut. tehrani@engr.uconn.edu
Jeremy Lee , ECE Department, University of Connecticut. jslee@engr.uconn.edu
pp. 1172-1177

Multi-Vector Tests: A Path to Perfect Error-Rate Testing (Abstract)

Sandeep Gupta , Department of EE-Systems, University of Southern California, Los Angeles, CA 90089. sandeep@poisson.usc.edu
Shideh Shahidi , Department of EE-Systems, University of Southern California, Los Angeles, CA 90089. sshahidi@poisson.usc.edu
pp. 1178-1183

iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing (Abstract)

Qiang Xu , Dept. of Computer Science&Engineering, The Chinese University of Hong Kong. qxu@cse.cuhk.edu.hk
Xiaowei Li , Key Laboratory of Computer System and Architecture, ICT, CAS, Beijing, China. lxw@ict.ac.cn, gracelee@ict.ac.cn
Jia Li , Key Laboratory of Computer System and Architecture, ICT, CAS, Beijing, China; Graduate University of Chinese Academy of Sciences, Beijing, China. gracelee@ict.ac.cn
Yu Hu , Key Laboratory of Computer System and Architecture, ICT, CAS, Beijing, China. huyu@ict.ac.cn, gracelee@ict.ac.cn
pp. 1184-1189

Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors (Abstract)

Aviral Shrivastava , CML Research Group, Arizona State University, USA. Aviral.Shrivastava@asu.edu
Yunheung Paek , SO&R Research Group, Seoul National University, Korea. ypaek@snu.ac.kr
Sanghyun Park , SO&R Research Group, Seoul National University, Korea. shpark@optimizer.snu.ac.kr
pp. 1190-1195

Instruction Cache Energy Saving Through Compiler Way-Placement (Abstract)

Bruno De Bus , Member of HiPEAC, Department of Electronics and Information Systems (ELIS), University of Ghent, Belgium. bruno.debus@elis.ugent.be
Sandro Bartolini , Member of HiPEAC, Dipartimento di Ingegneria dell' Informazione, Università di Siena, Italy. bartolini@dii.unisi.it
Michael F.P. O'Boyle , Member of HiPEAC, School of Informatics, University of Edinburgh, UK. mob@inf.ed.ac.uk
Timothy M. Jones , Member of HiPEAC, School of Informatics, University of Edinburgh, UK. tjonesl@inf.ed.ac.uk
John Cavazos , Computer and Information Sciences, University of Delaware, USA. cavazos@cis.udel.edu
pp. 1196-1201

Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints (Abstract)

Zili Shao , Dept. of Computing, the Hong Kong Polytechnic U., Hong Kong; Email: cszlshao@comp.polyu.edu.hk
Chun Jason Xue , Department of Computer Science, City University of Hong Kong; Email: jasonxue@cityu.edu.hk
Meikang Qiu , U. of New Orleans; Email: qiumeikang@yahoo.com
Edwin H.-M. Sha , Dept. of Computer Science, the U. of Texas at Dallas, Richardson, Texas 75083, USA; Email: edsha@utdallas.edu
pp. 1202-1207

Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications (Abstract)

Antonio Carlos S. Beck , Universidade Federal do Rio Grande do Sul, Instituto de Informática - Porto Alegre/Brazil; Delft University of Technology, Computer Engineering - Delft/The Netherlands. caco@inf.uf
Luigi Carro , Universidade Federal do Rio Grande do Sul, Instituto de Informática - Porto Alegre/Brazil. carro@inf.ufrgs.br
Mateus B. Rutzig , Universidade Federal do Rio Grande do Sul, Instituto de Informática - Porto Alegre/Brazil. mbrutzig@inf.ufrgs.br
Georgi Gaydadjiev , Delft University of Technology, Computer Engineering - Delft/The Netherlands. g.n.gaydadjiev@ewi.tudelft.nl
pp. 1208-1213

Automatic Selection of Application-Specific Reconfigurable Processor Extensions (Abstract)

Krzysztof Kuchcinski , Dept. of Computer Science, Lund University, Sweden. krzysztof.kuchcinski@cs.lth.se
Christophe Wolinski , University of Rennes I / IRISA, France. wolinski@irisa.fr
pp. 1214-1219

An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications (Abstract)

Jason Schlessman , Department of Electrical Engineering, Princeton University, Princeton, USA, 08554. jschless@princeton.edu
Sebastian Puthenpurayil , Department of Electrical and Computer Engineering and Institute for Advanced Computer Studies, University of Maryland, College Park, USA, 20742. purayil@umd.edu
Sankalita Saha , Department of Electrical and Computer Engineering and Institute for Advanced Computer Studies, University of Maryland, College Park, USA, 20742. ssaha@umd.edu
Shuvra S. Bhattacharyya , Department of Electrical and Computer Engineering and Institute for Advanced Computer Studies, University of Maryland, College Park, USA, 20742. ssb@umd.edu
Wayne Wolf , Electrical and Computer Engineering Department, Georgia Institute of Technology, Atlanta, USA, 30332. wayne.wolf@ece.gatech.edu
pp. 1220-1225

Dependability for high-tech systems: an industry-as-laboratory approach (Abstract)

Ed Brinksma , Embedded Systems Institute, Eindhoven, University of Twente, Enschede, The Netherlands. ed.brinksma@esi.nl
Jozef Hooman , Embedded Systems Institute, Eindhoven, Radboud University Nijmegen, The Netherlands. jozef.hooman@esi.nl
pp. 1226-1231

User-Aware Dynamic Task Allocation in Networks-on-Chip (Abstract)

Radu Marculescu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA. radum@andrew.cmu.edu
Chen-Ling Chou , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA. chenlinc@andrew.cmu.edu
pp. 1232-1237

Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures (Abstract)

Jorg Henkel , University of Karlsruhe, CES - Chair for Embedded Systems, Karlsruhe, Germany. henkel@informatik.uni-karlsruhe.de
Mohammad Abdullah Al Faruque , University of Karlsruhe, CES - Chair for Embedded Systems, Karlsruhe, Germany. alfaruque@informatik.uni-karlsruhe.de
pp. 1238-1243

An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication (Abstract)

Byeong Min , CAE Team, System LSI Division, Semiconductor Business, Samsung Electronics
Soo-Kwan Eo , CAE Team, System LSI Division, Semiconductor Business, Samsung Electronics
Sungjoo Yoo , CAE Team, System LSI Division, Semiconductor Business, Samsung Electronics
Sung-Min Hong , CAE Team, System LSI Division, Semiconductor Business, Samsung Electronics
Kyu-Myung Choi , CAE Team, System LSI Division, Semiconductor Business, Samsung Electronics
Woo-Cheol Kwon , CAE Team, System LSI Division, Semiconductor Business, Samsung Electronics
pp. 1244-1249

Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design (Abstract)

Ajay K. Verma , Ecole Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, CH-1015 Lausanne, Switzerland. AjayKumar.Verma@epfl.ch
Philip Brisk , Ecole Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, CH-1015 Lausanne, Switzerland. Philip.Brisk@epfl.ch
Paolo Ienne , Ecole Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, CH-1015 Lausanne, Switzerland. Paolo.Ienn@epfl.ch
pp. 1250-1255

Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming (Abstract)

Philip Brisk , Ecole Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, CH-1015 Lausanne, Switzerland. e-mail: philip.brisk@epfl.ch
Paolo Ienne , Ecole Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, CH-1015 Lausanne, Switzerland. e-mail: paolo.ienne@epfl.ch
Hadi Parandeh-Afshar , School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran; Ecole Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, C
pp. 1256-1261

An adaptable FPGA-based System for Regular Expression Matching (Abstract)

Marco D. Santambrogio , Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy. marco.santambrogio@polimi.it
Ivano Bonesana , ALaRI, Faculty of Informatics, University of Lugano, Lugano, Switzerland. bonesani@alari.ch
Marco Paolieri , ALaRI, Faculty of Informatics, University of Lugano, Lugano, Switzerland. paolierm@alari.ch
pp. 1262-1267

Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems (Abstract)

Miroslav N. Velev , Aries Design Automation, LLC. miroslav.velev@aries-da.com
Ping Gao , Aries Design Automation, LLC
pp. 1268-1273

Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis (Abstract)

Denis Real , IETR - CELAR, 35170 Bruz, France. denis.real@dga.defense.gouv.fr
Mhamed Drissi , IETR, 35043 Rennes, France. Mhamed.Drissi@insa-rennes.fr
Frederic Valette , CELAR, 35170 Bruz, France. frederic.valette@dga.defense.gouv.fr
Jessy Clediere , LETTI, 38054 Grenoble Cedex 9, France. jessy.clediere@cea.fr
Cecile Canovas , LETTI, 38054 Grenoble Cedex 9, France. cecile.canovas@cea.fr
pp. 1274-1279

Power Balanced Gates Insensitive to Routing Capacitance Mismatch (Abstract)

Vyas Venkataraman , Boston University, Reliable Computing Laboratory, 8 Saint Mary's Street, Boston, MA 02215, USA. vyas@bu.edu, lark@bu.edu
Konrad J. Kulikowski , Boston University, Reliable Computing Laboratory, 8 Saint Mary's Street, Boston, MA 02215, USA. konkul@bu.edu, lark@bu.edu
Zhen Wang , Boston University, Reliable Computing Laboratory, 8 Saint Mary's Street, Boston, MA 02215, USA. lark@bu.edu
Alexander Taubin , Boston University, Reliable Computing Laboratory, 8 Saint Mary's Street, Boston, MA 02215, USA. taubin@bu.edu, lark@bu.edu
pp. 1280-1285

On Analysis and Synthesis of (n,k)-Non-Linear Feedback Shift Registers (Abstract)

Maxim Teslenko , Royal Institute of Technology (KTH), Electrum 229, 164 46 Kista, Sweden. maximt@imit.kth.se
Hannu Tenhunen , Royal Institute of Technology (KTH), Electrum 229, 164 46 Kista, Sweden. hannu@imit.kth.se
Elena Dubrova , Royal Institute of Technology (KTH), Electrum 229, 164 46 Kista, Sweden. elena@imit.kth.se
pp. 1286-1291

FPGA Design for Algebraic Tori-Based Public-Key Cryptography (Abstract)

Junfeng Fan , Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium. Junfeng.Fan@esat.kuleuven.be
Ingrid Verbauwhede , Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium. Ingrid.Verbauwhede@esat.kuleuven.be
Kazuo Sakiyama , Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium. Kazuo.Sakiyama@esat.kuleuven.be
Lejla Batina , Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium. Lejla.Batina@esat.kuleuven.be
pp. 1292-1297

Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation (Abstract)

Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada. Email: nicola@ece.mcmaster.ca
Ho Fai Ko , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada. Email: henryko@grads.ece.mcmaster.ca
pp. 1298-1303

Functional Self-Testing for Bus-Based Symmetric Multiprocessors (Abstract)

A. Apostolakis , Department of Informatics, University of Piraeus, Greece. andapo@unipi.gr
A. Paschalis , Department of Informatics&Telecom., University of Athens, Greece. paschali@di.uoa.gr
M. Psarakis , Department of Informatics, University of Piraeus, Greece. mpsarak@unipi.gr
D. Gizopoulos , Department of Informatics, University of Piraeus, Greece. dgizop@unipi.gr
pp. 1304-1309

Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality (Abstract)

H. Manhaeve , Q-Star Test, Lieven Bauwensstraat 20, B-8200 Brugge, Belgium. Phone: +32 50 319273, Fax: +32 50 312350, e-mail: info@qstar.be
J. Brenkus , Department of Microelectronics, Slovak University of Technology, Ilkovi¿ova 3, 812 19 Bratislava, Slovakia
S. Kerckenaere , Q-Star Test, Lieven Bauwensstraat 20, B-8200 Brugge, Belgium. Phone: +32 50 319273, Fax:+32 50 312350, e-mail: info@qstar.be
B. Straka , Q-Star Test, Lieven Bauwensstraat 20, B-8200 Brugge, Belgium. Phone: +32 50 319273, Fax: +32 50 312350, e-mail: info@qstar.be
pp. 1310-1315

Advanced Analog Filters for Telecommunications (Abstract)

A. Baschirotto , Department of Physics, University of Bicocca - Milano, Italy
S. D'Amico , Innovation Engineering Department, University of Salento - Lecce, Italy
M. De Matteis , Innovation Engineering Department, University of Salento - Lecce, Italy
pp. 1316-1321

Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies (Abstract)

G. Groeseneken , IMEC Leuven, Belgium; KU Leuven, ESAT-MICAS Department, Belgium
E. Maricau , Departement Elektrotechniek ESAT-MICAS, Katholieke Universiteit Leuven, Belgium
P. De Wit , Departement Elektrotechniek ESAT-MICAS, Katholieke Universiteit Leuven, Belgium
G. Gielen , Departement Elektrotechniek ESAT-MICAS, Katholieke Universiteit Leuven, Belgium. gielen@esat.kuleuven.be
B. Kaczer , IMEC Leuven, Belgium
J. Loeckx , Departement Elektrotechniek ESAT-MICAS, Katholieke Universiteit Leuven, Belgium
J. Martin-Martinez , IMEC Leuven, Belgium; Universitat Autonoma de Barcelona, Spain
R. Rodriguez , Universitat Autonoma de Barcelona, Spain
M. Nafria , Universitat Autonoma de Barcelona, Spain
pp. 1322-1327

Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces (Abstract)

Alexandre Schmid , Microelectronic Systems Laboratory (LSM), EPFL Lausanne, 1015 Switzerland
Yusuf Leblebici , Microelectronic Systems Laboratory (LSM), EPFL Lausanne, 1015 Switzerland
Frank K. Gurkaynak , Microelectronic Systems Laboratory (LSM), EPFL Lausanne, 1015 Switzerland
Carlotta Guiducci , DEIS University of Bologna, Italy
pp. 1328-1333

High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures (Abstract)

Xiaolin Chen , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
Harold Ishebabi , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
Gerd Ascheid , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
Heinrich Meyr , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
Rainer Leupers , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
Anupam Chattopadhyay , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany. anupam@iss.rwth-aachen.de
pp. 1334-1339

Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence (Abstract)

Amin Farmahini-Farahani , School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran. a.farmahini@ece.ut.ac.ir
Sied Mehdi Fakhraie , School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran. fakhraie@ut.ac.ir
Saeed Safari , School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran. saeed@ut.ac.ir
pp. 1340-1345

Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems (Abstract)

Yi Lu , Computer Engineering Laboratory, EEMCS, TU Delft, The Netherlands. Email: yilu@ce.et.tudelft.nl
Thomas Marconi , Computer Engineering Laboratory, EEMCS, TU Delft, The Netherlands. Email: thomas@ce.et.tudelft.nl
Georgi Gaydadjiev , Computer Engineering Laboratory, EEMCS, TU Delft, The Netherlands. Email: g.n.gaydadjiev@ewi.tudelft.nl
Koen Bertels , Computer Engineering Laboratory, EEMCS, TU Delft, The Netherlands. Email: k.l.m.bertels@tudelft.nl
pp. 1346-1351

Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor (Abstract)

M. Huebner , ITIV, University of Karlsruhe, Germany
A. Deledda , ARCES, University of Bologna, Italy
F. Campi , STMicroelectronics, Italy
T. DeMarco , STMicroelectronics, Italy
M. Coppola , STMicroelectronics, France
R. Locatelli , STMicroelectronics, France
C. Mucci , ARCES, University of Bologna, Italy
A. Vitkovski , ARCES, University of Bologna, Italy
M. Kuehnle , ITIV, University of Karlsruhe, Germany
P. Bonnot , THALES Research and Technology, France
G. Maruccia , STMicroelectronics, France
L. Pieralisi , STMicroelectronics, France
J. Becker , ITIV, University of Karlsruhe, Germany
P. Millet , THALES Research and Technology, France
A. Grasset , THALES Research and Technology, France
F. Ries , ITIV, University of Karlsruhe, Germany
pp. 1352-1357

Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems (PDF)

Stefan Poledna , TTTech, Austria
Neeraj Suri , TU Darmstadt, Germany
Subhasish Mitra , Stanford Univ, USA
Avi Mendelson , Intel, Israel
Jacob Abraham , Univ. of Texas at Austin, USA
Christof Fetzer , TU Dresden, Germany
pp. 1394-1395

Multicast Parallel Pipeline Router Architecture for Network-on-Chip (Abstract)

Faizal A. Samman , Technische Universität Darmstadt, Institute of Microelectronic Systems, Karlstr. 15. Darmstadt, Hessen D-64283; Dept. of Electrical Engineering, the University of Hasanuddin at Mak
Manfred Glesner , Technische Universität Darmstadt, Institute of Microelectronic Systems, Karlstr. 15. Darmstadt, Hessen D-64283. glesner@mes.tu-darmstadt.de
Thomas Hollstein , Technische Universität Darmstadt, Institute of Microelectronic Systems, Karlstr. 15. Darmstadt, Hessen D-64283. thomas.hollstein@mes.tu-darmstadt.de
pp. 1396-1401

Variation tolerant NoC design by means of self-calibrating links (Abstract)

Medardoni Simone , University of Ferrara, 44100 Ferrara, Italy
Marcello Lajolo , NEC Laboratories America, Inc, 08540 Princeton NJ, USA
Davide Bertozzi , University of Ferrara, 44100 Ferrara, Italy
pp. 1402-1407

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs (Abstract)

Pejman Lotfi-Kamran , School of Electrical and Computer Engineering, The University of Tehran. plotf@computer.org
Zainalabedin Navabi , School of Electrical and Computer Engineering, The University of Tehran. navabi@ece.neu.edu
Masoud Daneshtalab , School of Electrical and Computer Engineering, The University of Tehran; Islamic Azad University, Parand Branch. m.daneshtalab@ece.ut.ac.ir
Caro Lucas , School of Electrical and Computer Engineering, The University of Tehran. lucas@ipm.ir
pp. 1408-1413

Developing Mesochronous Synchronizers to Enable 3D NoCs (Abstract)

Federico Angiolini , DEIS, University of Bologna, Bologna, Italy. fangiolini@deis.unibo.it
Igor Loi , DEIS, University of Bologna, Bologna, Italy. iloi@deis.unibo.it
Luca Benini , DEIS, University of Bologna, Bologna, Italy. lbenini@deis.unibo.it
pp. 1414-1419

Memory Organization with Multi-Pattern Parallel Accesses (Abstract)

Arseni Vitkovski , ARCES - University of Bologna, Viale Pepoli 3/2, 40123 Bologna, Italy. avitkovski@arces.unibo.it
Georgi Kuzmanov , CE/EEMCS - Delft University of Technology, Mekelweg 4, 2628 CD Delft, the Netherlands. G.K.Kuzmanov@tudelft.nl
Georgi Gaydadjiev , CE/EEMCS - Delft University of Technology, Mekelweg 4, 2628 CD Delft, the Netherlands. G.N.Gaydadjiev@tudelft.nl
pp. 1420-1425

CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches (Abstract)

Marios Kleanthous , Department of Computer Science, University of Cyprus
Yiannakis Sazeides , Department of Computer Science, University of Cyprus
pp. 1426-1431

Magellan: A Search and Machine Learning-based Framework for Fast Multi-core Design Space Exploration and Optimization (Abstract)

Rakesh Kumar , Coordinated Science Laboratory, 1308 West Main St, Urbana, IL 61801
Sukhun Kang , Coordinated Science Laboratory, 1308 West Main St, Urbana, IL 61801
pp. 1432-1437

Process Variation Aware Issue Queue Design (Abstract)

Madhu Mutyam , Department of Computer Science and Engineering, Indian Institute of Technology-Madras, Chennai - 600036, India. madhu@cse.iitm.ac.in
Raghavendra K , Department of Computer Science and Engineering, Indian Institute of Technology-Madras, Chennai - 600036, India. raghavendra83@gmail.com
pp. 1438-1443

Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array (Abstract)

Ilario Mirimin , ARCES - University of Bologna
Axel Schneider , Alcatel-Lucent Deutschland AG
Joachim Knaeblein , Alcatel-Lucent Deutschland AG
Daniele Gazzola , ARCES - University of Bologna
Claudio Mucci , ARCES - University of Bologna
Luca Vanzolini , ARCES - University of Bologna
Fabio Campi , FTM, STMicroelectronics, Agrate Brianza
Luca Ciccarelli , FTM, STMicroelectronics, Agrate Brianza
Antonio Deledda , ARCES - University of Bologna
Sebastian Goller , Technische Universität Chemnitz
pp. 1444-1449

GMDS: Hardware implementation of novel real output queuing architecture (Abstract)

R. Esper-Chain , Institute for Applied Microelectronics (IUMA). DIEA. University of Las Palmas de Gran Canaria, Campus Universitario de Tafira, S/N. 35017. Las Palmas de Gran Canaria, Spain. esper@
F. Tobajas , Institute for Applied Microelectronics (IUMA). DIEA. University of Las Palmas de Gran Canaria, Campus Universitario de Tafira, S/N. 35017. Las Palmas de Gran Canaria, Spain. tobaja
R. Arteaga , Institute for Applied Microelectronics (IUMA). DIEA. University of Las Palmas de Gran Canaria, Campus Universitario de Tafira, S/N. 35017. Las Palmas de Gran Canaria, Spain. rartea
Roberto Sarmiento , Institute for Applied Microelectronics (IUMA). DIEA. University of Las Palmas de Gran Canaria, Campus Universitario de Tafira, S/N. 35017. Las Palmas de Gran Canaria, Spain. robert
V. de Armas , Institute for Applied Microelectronics (IUMA). DIEA. University of Las Palmas de Gran Canaria, Campus Universitario de Tafira, S/N. 35017. Las Palmas de Gran Canaria, Spain. armas@
pp. 1450-1455

Front End Device for Content Networking (Abstract)

Jeremy Buboltz , School of EECS, University of Central Florida, Orlando, FL 32816, USA. je963524@pegasus.cc.ucf.edu
Taskin Kocak , Dept. of Electrical and Electronic Engineering, University of Bristol, Bristol, BS8 1UB, UK. t.kocak@bristol.ac.uk
pp. 1456-1461

Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography (Abstract)

Mario Porrmann , Heinz Nixdorf Institute, Systems and Circuit Technology, University of Paderborn, Germany. porrmann@hni.upb.de
Madhura Purnaprajna , Heinz Nixdorf Institute, Systems and Circuit Technology, University of Paderborn, Germany. madhurap@hni.upb.de
Christoph Puttmann , Heinz Nixdorf Institute, Systems and Circuit Technology, University of Paderborn, Germany. puttmann@hni.upb.de
pp. 1462-1467

Digital bit stream jitter testing using jitter expansion (Abstract)

Abhijit Chatterjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332-0250. chat@ece.gatech.edu
Hyun Choi , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332-0250. hyun@ece.gatech.edu
pp. 1468-1473

A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution (Abstract)

Sudhakar M. Reddy , Electrical&Computer Eng. Dept., University of Iowa, Iowa City, IA 52242, U.S.A.
Irith Pomeranz , School of Electrical&Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
pp. 1474-1479

A Design-for-Diagnosis Technique for SRAM Write Drivers (Abstract)

V. Gouin , Infineon Technologies France, 2600, route des Crêtes - 06560 Sophia-Antipolis, France. Email: vicent.gouin@infineon.com
S. Pravossoudovitch , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Emai
A. Virazel , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Emai
P. Girard , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Emai
M. Bastian , Infineon Technologies France, 2600, route des Crêtes - 06560 Sophia-Antipolis, France. Email: magali.bastian@infineon.com
A. Ney , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, 161, rue Ada - 34392 Montpellier Cedex 5, France. Emai
pp. 1480-1485

Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications (Abstract)

D.C. Keezer , Georgia Institute of Technology, Atlanta, Georgia USA
P. Ducharme , IBM, Bromont, Canada
D. Minier , IBM, Bromont, Canada
pp. 1486-1491

Retargetable Code Optimization for Predicated Execution (Abstract)

M. Hohenauer , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany
F. Engel , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany
G. Ascheid , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany
H. Meyr , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany
R. Leupers , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany
Balpreet Singh , NXP Semiconductors, Eindhoven, The Netherlands
Gerrit Bette , Associated Compiler Experts bv, Amsterdam, The Netherlands
pp. 1492-1497

Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads (Abstract)

Nalini Vasudevan , Department of Computer Science, Columbia University, New York, USA. naliniv@cs.columbia.edu
Olivier Tardieu , INRIA, Sophia Antipolis, France. olivier.tardieu@inria.fr
Stephen A. Edwards , Department of Computer Science, Columbia University, New York, USA. sedwards@cs.columbia.edu
pp. 1498-1503

Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams (Abstract)

Roberto Lublinerman , Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA 16802. rluble@psu.edu
Stavros Tripakis , Cadence Research Laboratories, 2150 Shattuck Avenue, 10th Floor, Berkeley, CA 94704, USA. tripakis@cadence.com
pp. 1504-1509

ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis (Abstract)

Paulo Maciel , Centro de Informática (CIn), Universidade Federal de Pernambuco. prmm@cin.ufpe.br
Lucas Cordeiro , Departamento de Ciência da Computação, Universidade Federal do Amazonas. lcc@dcc.ufam.edu.br
Fabiano Cruz , Departamento de Ciência da Computação, Universidade Federal do Amazonas. fcruz@dcc.ufam.edu.br
Raimundo Barreto , Departamento de Ciência da Computação, Universidade Federal do Amazonas. rbarreto@dcc.ufam.edu.br
pp. 1510-1515

HOT TOPIC - 3D Integration or How to Scale in the 21st Century (PDF)

D Keitel-Schulz , Qimonda, Belgium
L Benini , University of Bologna, Italy
N Checka , MIT Lincoln Labs, USA
P Marchal , IMEC, Belgium
P Marchal , IMEC, Belgium
B Bougard , IMEC, Belgium
pp. 1516

Built-in Clock Skew System for On-line Debug and Repair (Abstract)

Zeljko Zilic , McGill University, Dept. of Electrical and Computer Engineering, Montreal, Canada
Atanu Chattopadhyay , McGill University, Dept. of Electrical and Computer Engineering, Montreal, Canada
pp. 248-251

Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects (Abstract)

Young H. Kwark , IBM T. J. Watson Research Center, Yorktown Heights, NY (USA)
Christian Schuster , Institut für Theoretische Elektrotechnik, Technische Universität Hamburg-Harburg (Germany)
Mark B. Ritter , IBM T. J. Watson Research Center, Yorktown Heights, NY (USA)
Xiaoxiong Gu , IBM T. J. Watson Research Center, Yorktown Heights, NY (USA)
Renato Rimolo-Donadio , Institut für Theoretische Elektrotechnik, Technische Universität Hamburg-Harburg (Germany)
pp. 252-255

On Automated Trigger Event Generation in Post-Silicon Validation (Abstract)

Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada. Email: nicola@ece.mcmaster.ca
Ho Fai Ko , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada. Email: henryko@grads.ece.mcmaster.ca
pp. 256-259

Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems (Abstract)

Ken W. Batcher , Kent State University, Cisco Systems. batcher@cisco.com
Robert A. Walker , Kent State University. walker@cs.kent.edu
pp. 260-263

Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking (Abstract)

Yang Qu , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FIN-90571 Oulu, Finland. Yang.Qu@vtt.fi
Jari Nurmi , Tampere University of Technology, Korkeakoulunkatu 1, FIN-33720 Tampere, Finland
Juha-Pekka Soininen , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FIN-90571 Oulu, Finland
pp. 264-267

Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration (Abstract)

Lin Zhong , Dept. of Electrical&Computer Engineering, Rice University, Houston, TX 77005
Mian Dong , Dept. of Electrical&Computer Engineering, Rice University, Houston, TX 77005
pp. 268-271

Merged Computation for Whirlpool Hashing (Abstract)

Ricardo Chaves , Instituto Superior Técnico/INESC-ID. Portugal; Computer Engineering Lab, TUDelft. The Netherlands.
Leonel Sousa , Instituto Superior Técnico/INESC-ID. Portugal.
Georgi Kuzmanov , Computer Engineering Lab, TUDelft. The Netherlands.
Stamatis Vassiliadis , Computer Engineering Lab, TUDelft. The Netherlands.
pp. 272-275

Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor (Abstract)

Trevor Meyerowitz , University of California at Berkeley, Berkeley, California, USA. tcm@eecs.berkeley.edu
Dominik Langen , Infineon Technologies, Munich, Germany. Dominik.Langen@infineon.com
Mirko Sauermann , Infineon Technologies, Munich, Germany. Mirko.Sauermann@infineon.com
Alberto Sangiovanni-Vincentelli , University of California at Berkeley, Berkeley, California, USA. alberto@eecs.berkeley.edu
pp. 276-279

PWM-Based Test Stimuli Generation for BIST of High Resolution ¿¿ ADCs (Abstract)

Leonardo Reyneri , Politecnico di Torino, Italy. reyneri@polito.it
Daniela De Venuto , Politecnico di Bari, Italy. d.devenuto@poliba.it
pp. 284-287

Fault Clustering in deep-submicron CMOS Processes (Abstract)

Jan Schat , NXP Semiconductors Germany
pp. 511-514

Energy Efficient and High Speed On-Chip Ternary Bus (Abstract)

Chunjie Duan , Mitsubishi Electric Research Labs, 201 Broadway, Cambridge, MA USA. Email: duan@merl.com
Sunil P. Khatri , Department of Electrical Engineering, Texas A&M University, College Station, TX 77843 USA. Email: sunilkhatri@tamu.edu
pp. 515-518

Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems (Abstract)

Francesco Redaelli , DEI, Politecnico di Milano, Piazza Leonardo da Vinci 32, 20133, Milano. francesco.redaelli@dresd.org
Marco D. Santambrogio , DEI, Politecnico di Milano, Piazza Leonardo da Vinci 32, 20133, Milano. santambr@elet.polimi.it
Donatella Sciuto , DEI, Politecnico di Milano, Piazza Leonardo da Vinci 32, 20133, Milano. sciuto@elet.polimi.it
pp. 519-522

Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches (Abstract)

Almitra Pradhan , Dept. of ECE, University of Cincinnati, Cincinnati, OH 45219. pradhaa@ececs.uc.edu
Ranga Vemuri , Dept. of ECE, University of Cincinnati, Cincinnati, OH 45219. ranga@ececs.uc.edu
pp. 523-526

Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression (Abstract)

Bao Liu , University of California San Diego, Computer Science and Engineering Department, 9500 Gilman Dr., La Jolla, CA 92093-0114. Email: bliu@cs.ucsd.edu
pp. 527-532

A methodology for improving software design lifecycle in embedded control systems (Abstract)

Yves Sorel , AOSTE Project-Team, INRIA Paris-Rocquencourt. email: Yves.Sorel@inria.fr
Remy Kocik , COSI Lab, ESIEE Paris, France. email: r.kocik@esiee.fr
Redha Hamouche , COSI Lab, ESIEE Paris, France. email: r.hamouche@esiee.fr
Mohamed El Mongi Ben Gaid , NeCS Project-Team, INRIA Grenoble-Rhône-Alpes, France. email: Mohamed.Bengaid@inria.fr
pp. 533-536

Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (Abstract)

Yi Zhu , UC San Diego, La Jolla, CA, U.S.A. y2zhu@ucsd.edu
Toshiyuki Shibuya , Fujitsu Laboratories LTD, Kawasaki, Japan. shibu@jp.fujitsu.com
Nuriyoki Ito , Fujitsu Limited, Kawasaki, Japan. ito.nuriyoki@jp.fujitsu.com
Ling Zhang , UC San Diego, La Jolla, CA, U.S.A. lizhang@ucsd.edu
Wanping Zhang , Qualcomm Inc. 5775 Morehouse Dr., San Diego, CA, U.S.A.; UC San Diego, La Jolla, CA, U.S.A. wanpingz@qualcomm.com, w7zhang@ucsd.edu
Rajeev Murgai , Fujitsu Laboratories of America, Inc., Sunnyvale, CA, U.S.A. murgai@fla.fujitsu.com
Zhi Zhu , Qualcomm Inc. 5775 Morehouse Dr., San Diego, CA, U.S.A. zzhu@qualcomm.com
Wenjian Yu , UC San Diego, La Jolla, CA, U.S.A.; Tsinghua University, Beijing 100084, China. w1yu@ucsd.edu, yu-wj@tsinghua.edu.cn
He Peng , UC San Diego, La Jolla, CA, U.S.A. hepeng@ucsd.edu
Rui Shi , UC San Diego, La Jolla, CA, U.S.A. rshi@ucsd.edu
Lew Chua-Eoan , Qualcomm Inc. 5775 Morehouse Dr., San Diego, CA, U.S.A. lewc@qualcomm.com
Chung-Kuan Cheng , UC San Diego, La Jolla, CA, U.S.A. ckcheng@ucsd.edu
pp. 537-540

A System Architecture for Reconfigurable Trusted Platforms (Abstract)

Alexander Klimm , Institut für Technik der Informationsverarbeitung, Universität Karlsruhe (TH). E-mail: klimm@itiv.uni-karlsruhe.de
Jurgen Becker , Institut für Technik der Informationsverarbeitung, Universität Karlsruhe (TH). E-mail: becker@itiv.uni-karlsruhe.de
Klaus Muller-Glaser , Institut für Technik der Informationsverarbeitung, Universität Karlsruhe (TH). E-mail: kmg@itiv.uni-karlsruhe.de
Oliver Sander , Institut für Technik der Informationsverarbeitung, Universität Karlsruhe (TH). E-mail: sander@itiv.uni-karlsruhe.de
Benjamin Glas , Institut für Technik der Informationsverarbeitung, Universität Karlsruhe (TH). E-mail: glas@itiv.uni-karlsruhe.de
pp. 541-544

Automatic Generation of Complex Properties for Hardware Designs (Abstract)

Steffen Rulke , Fraunhofer Institute for Integrated Circuits, Division Design Automation, 01069 Dresden, Germany. steffen.ruelke@eas.iis.fraunhofer.de
Frank Rogin , Fraunhofer Institute for Integrated Circuits, Division Design Automation, 01069 Dresden, Germany. frank.rogin@eas.iis.fraunhofer.de
Rolf Drechsler , University of Bremen, Institute of Computer Science, 28359 Bremen, Germany. drechsle@informatik.uni-bremen.de
Thomas Klotz , Fraunhofer Institute for Integrated Circuits, Division Design Automation, 01069 Dresden, Germany. thomas.klotz@eas.iis.fraunhofer.de
Gorschwin Fey , University of Bremen, Institute of Computer Science, 28359 Bremen, Germany. fey@informatik.uni-bremen.de
pp. 545-548

Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices (Abstract)

Martin Versen , Qimonda AG, Am Campeon 1-12, D-85579 Neubiberg, Germany
Achim Schramm , Qimonda AG, Am Campeon 1-12, D-85579 Neubiberg, Germany
Dorina Diaconescu , Infineon AG, Otto-Hahn-Ring 6, D-81739 München, Germany
Jan Schnepp , Qimonda AG, Am Campeon 1-12, D-85579 Neubiberg, Germany
pp. 776-779

A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs (Abstract)

Torsten Limberg , Vodafone Chair Mobile Communications Systems, TU Dresden, Germany. limberg@ifn.et.tu-dresden.de
Gerhard Fettweis , Vodafone Chair Mobile Communications Systems, TU Dresden, Germany. fettweis@ifn.et.tu-dresden.de
Bastian Ristau , Vodafone Chair Mobile Communications Systems, TU Dresden, Germany. ristau@ifn.et.tu-dresden.de
pp. 780-783

Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication (Abstract)

Thomas Kunemund , Infineon Technologies Austria AG. thomas.kuenemund@infineon.com
Thomas Leutgeb , Infineon Technologies Austria AG. thomas.leutgeb@infineon.com
Bernd Zimek , Infineon Technologies Austria AG. bernd.zimek@infineon.com
Josef Haid , Infineon Technologies Austria AG. josef.haid@infineon.com
pp. 784-787

Accuracy-Adaptive Simulation of Transaction Level Models (Abstract)

M. Radetzki , Institut für Technische Informatik, Universität Stuttgart, Stuttgart, Germany. radetzki@informatik.uni-stuttgart.de
R. Salimi Khaligh , Institut für Technische Informatik, Universität Stuttgart, Stuttgart, Germany. salimi@informatik.uni-stuttgart.de
pp. 788-791

Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor (Abstract)

Kun Huang , Institute of Computing Technology, Chinese Academy of Sciences. kunhuang@ict.ac.cn
Jun Wang , Institute of Computing Technology, Chinese Academy of Sciences. wangjun@ict.ac.cn
Ge Zhang , Institute of Computing Technology, Chinese Academy of Sciences. gzhang@ict.ac.cn
Yan Tang , The Ohio State University. tangya@cse.ohio-state.edu
Hongbo Zeng , Institute of Computing Technology, Chinese Academy of Sciences. hbzeng@ict.ac.cn
pp. 792-795

Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture (Abstract)

Fu-Wei Chen , Department of Computer Science and Engineering, Yuan Ze University, Chungli, Taiwan 320, R.O.C. s956030@mail.yzu.edu.tw
Yi-Yu Liu , Department of Computer Science and Engineering, Yuan Ze University, Chungli, Taiwan 320, R.O.C. yyliu@saturn.yzu.edu.tw, s956030@mail.yzu.edu.tw
pp. 796-799

Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology (Abstract)

Lars Hedrich , Institute of Computer Science, University of Frankfurt, Germany. hedrich@em.informatik.uni-frankfurt.de
Xiaoying Wang , Institute of Computer Science, University of Frankfurt, Germany. wang@em.informatik.uni-frankfurt.de
pp. 800-803

A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design (Abstract)

Gilles Jacquemod , LEAT, UMR UNSA-CNRS 6071, 06560 Valbonne, France
Jacky Talayssat , NXP Semiconductors, 06560 Valbonne, France
Javier del Prado Pavon , NXP Semiconductors, 06560 Valbonne, France
Eric Dekneuvel , LEAT, UMR UNSA-CNRS 6071, 06560 Valbonne, France
Alexandre Lewicki , NXP Semiconductors, 06560 Valbonne, France; LEAT, UMR UNSA-CNRS 6071, 06560 Valbonne, France
pp. 804-807

Re-Examining the Use of Network-on-Chip as Test Access Mechanism (Abstract)

Feng Yuan , Department of Computer Science&Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: fyuan@cse.cuhk.edu.hk
Qiang Xu , Department of Computer Science&Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: qxu@cse.cuhk.edu.hk
Lin Huang , Department of Computer Science&Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong. Email: lhuang@cse.cuhk.edu.hk
pp. 808-811

VLSI implementation of SISO arithmetic decoders for joint source channel coding (Abstract)

Simone Zezza , Politecnico di Torino, Italy. simone.zezza@polito.it
Guido Masera , Politecnico di Torino, Italy. guido.masera@polito.it
pp. 1075-1078

Error Detection/Correction in DNA Algorithmic Self-Assembly (Abstract)

Stephen Frechette , Riverside Research Institute, Lexington, MA 02421. sfrechette@rri-usa.org
Fabrizio Lombardi , Dept of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115. lombardi@ece.neu.edu
pp. 1079-1082

Temperature-Aware Voltage Selection for Energy Optimization (Abstract)

Z. Peng , Embedded Systems Laboratory (ESLAB), Department of Computer and Information Science, Linköping University, Sweden. zebpe@ida.liu.se
A. Andrei , Embedded Systems Laboratory (ESLAB), Department of Computer and Information Science, Linköping University, Sweden. alean@ida.liu.se
P. Eles , Embedded Systems Laboratory (ESLAB), Department of Computer and Information Science, Linköping University, Sweden. petel@ida.liu.se
M. Bao , Embedded Systems Laboratory (ESLAB), Department of Computer and Information Science, Linköping University, Sweden. g-minba@ida.liu.se
pp. 1083-1086

A Fast Approximation Algorithm for MIN-ONE SAT (Abstract)

Lei Fang , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, 24061. leifang@vt.edu
Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, 24061. mhsiao@vt.edu
pp. 1087-1090

Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis (Abstract)

Chung-Ping Chen , National Taiwan University, Electrical Engineering Department. cchen@cc.ee.ntu.edu.tw
Jun-Kuei Zeng , National Taiwan University, Electrical Engineering Department. yelsta89g@yahoo.com.tw
pp. 1091-1094

An efficient algorithm for free resources management on the FPGA (Abstract)

Thomas Marconi , Computer Engineering Lab., TU Delft, The Netherlands. thomas@ce.et.tudelft.nl
Koen Bertels , Computer Engineering Lab., TU Delft, The Netherlands. k.l.m.bertels@tudelft.nl
Yi Lu , Computer Engineering Lab., TU Delft, The Netherlands. yilu@ce.et.tudelft.nl
Georgi Gaydadjiev , Computer Engineering Lab., TU Delft, The Netherlands. georgi@ce.et.tudelft.nl
pp. 1095-1098

Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits (Abstract)

Masahiro Fujita , VLSI Design and Education Center (VDEC), University of Tokyo; CREST, Japan Science and Technology Agency
Hiroaki Yoshida , VLSI Design and Education Center (VDEC), University of Tokyo; CREST, Japan Science and Technology Agency
pp. 1099-1102

Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs (Abstract)

Richard Kacprowicz , Intel Corporation, Hillsboro, OR 97124. Email: richard.kacprowicz@intel.com
Sudarshan Bahukudumbi , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708. Email: spb@ee.duke.edu
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708. Email: krish@ee.duke.edu
pp. 1103-1106

CARbridge, Reduction of System Complexity by Standardisation of the System-Basis-Chips for Automotive Applications (Abstract)

Stefan Burges , BMW Group, E/E Architecture, Ergonomics and HMI, Hardware Components, Munich, Germany
Patrick Scheer , BMW Group, E/E Architecture, Ergonomics and HMI, Hardware Components, Munich, Germany
Ernst Schmidt , BMW Group, E/E Architecture, Ergonomics and HMI, Hardware Components, Munich, Germany
pp. 1107-1110

Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications (Abstract)

Mark Muir , The Universtiy of Edinburgh, Mayfield Road, Edinburgh, EH9 3JL, United Kingdom. Mark.Muir@ed.ac.uk
Iain Lindsay , The Universtiy of Edinburgh, Mayfield Road, Edinburgh, EH9 3JL, United Kingdom
Tughrul Arslan , The Universtiy of Edinburgh, Mayfield Road, Edinburgh, EH9 3JL, United Kingdom; Institute for System Level Integration, Alba Centre, Livingston, EH54 7EG, United Kingdom
pp. 1358-1361

Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme (Abstract)

Chris Papachristou , Case Western Reserve University, Cleveland, Ohio 44106, USA. cap2@case.edu
Swarup Bhunia , Case Western Reserve University, Cleveland, Ohio 44106, USA. skb21@case.edu
Rajat S. Chakraborty , Case Western Reserve University, Cleveland, Ohio 44106, USA. rsc22@case.edu
Francis Wolff , Case Western Reserve University, Cleveland, Ohio 44106, USA. fxw12@case.edu
pp. 1362-1365

Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects (Abstract)

Tomokazu Yoneda , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan. yoneda@is.naist.jp
Hideo Fujiwara , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan. fujiwara@is.naist.jp
pp. 1366-1369

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs (Abstract)

Jimson Mathew , University of Bristol, UK. jimson@cs.bris.ac.uk
Mohammad Reza Kakoee , University of Tehran, Iran. kakoee@cad.ece.ut.ac.ir
Mohammad Hosseinabady , University of Bristol, UK. mohammad@cs.bris.ac.uk
Dhiraj K. Pradhan , University of Bristol, UK. pradhan@cs.bris.ac.uk
pp. 1370-1373

Adaptive Filesystem Compression for Embedded Systems (Abstract)

Lan S. Bai , Northwestern University, Evanston, IL 60208. l-bai@northwestern.edu
Haris Lekatsas , Vorras Corporation, Princeton, NJ 08540. lekatsas@vorras.com
Robert P. Dick , Northwestern University, Evanston, IL 60208. dickrp@northwestern.edu
pp. 1374-1377

Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits (Abstract)

D. Michael Miller , Department of Computer Science, University of Victoria, Victoria, BC, Canada. mmiller@cs.uvic.ca
Mitchell A. Thornton , Department of Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA. mitch@engr.smu.edu
David Y. Feinstein , Department of Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA. dfeinste@engr.smu.edu
pp. 1378-1381

TinyTimber, Reactive Objects in C for Real-Time Embedded Systems (Abstract)

Simon Aittamaa , EISLAB, Lule
Johan Eriksson , EISLAB, Lule
Johan Nordlander , EISLAB, Lule
Per Lindgren , EISLAB, Lule
pp. 1382-1385

Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications (Abstract)

Flavio Rech Wagner , Universidade Federal do Rio Grande do Sul - UFRGS, Instituto de Informática, Porto Alegre, RS, Brazil. flavio@inf.ufrgs.br
Eduardo Wenzel Briao , Universidade Federal do Rio Grande do Sul - UFRGS, Instituto de Informática, Porto Alegre, RS, Brazil. ewbriao@inf.ufrgs.br
Daniel Barcelos , Universidade Federal do Rio Grande do Sul - UFRGS, Instituto de Informática, Porto Alegre, RS, Brazil. danielb@inf.ufrgs.br
pp. 1386-1389

Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications (Abstract)

Claudio Nani , IMEC, NES/Wireless, Leuven, Belgium; Department of Information Engineering, University of Pisa, Pisa, Italy. Claudio.Nani@imec.be
Luca Fanucci , Department of Information Engineering, University of Pisa, Pisa, Italy. l.fanucci@iet.unipi.it
Geert Van der Plas , IMEC, NES/Wireless, Leuven, Belgium. Geert.VanderPlas@imec.be
Sergio Saponara , Department of Information Engineering, University of Pisa, Pisa, Italy. s.saponara@iet.unipi.it
Pierluigi Nuzzo , IMEC, NES/Wireless, Leuven, Belgium. Pierluigi.Nuzzo@imec.be
pp. 1390-1393

Author Index (PDF)

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