The Community for Technology Leaders
2007 10th Design, Automation and Test in Europe Conference and Exhibition (2007)
Nice
April 16, 2007 to April 20, 2007
ISBN: 978-3-9810801-2-4
TABLE OF CONTENTS

[Front cover] (PDF)

pp. C1

Table of contents (PDF)

pp. 1-24

[Opinion] (PDF)

pp. 1-3

Awards (PDF)

pp. 1

Tutorial (PDF)

pp. 1-5

Challenges of Digital Consumer and Mobile SoC's: More Moore Possible? (PDF)

Tohru Furuyama , General Manager, Center for Semiconductor Research & Development (CSRD), Toshiba Corp., JP
pp. 1

ATLAS: A Chip-Multiprocessor with Transactional Memory Support (PDF)

Njuguna Njoroge , Computer Systems Laboratory, Stanford University, tcc_fpga_xtreme@lists.stanford.edu
Jared Casper , Computer Systems Laboratory, Stanford University
Sewook Wee , Computer Systems Laboratory, Stanford University
Yuriy Teslyar , Computer Systems Laboratory, Stanford University
Daxia Ge , Computer Systems Laboratory, Stanford University
Christos Kozyrakis , Computer Systems Laboratory, Stanford University
Kunle Olukotun , Computer Systems Laboratory, Stanford University
pp. 1-6

A dynamically adaptive DSP for heterogeneous reconfigurable platforms (PDF)

Fabio Campi , ST Microelectronics, Agrate Brianza, Italy
Antonio Deledda , ST Microelectronics, Agrate Brianza, Italy
Matteo Pizzotti , ST Microelectronics, Agrate Brianza, Italy
Luca Ciccarelli , ST Microelectronics, Agrate Brianza, Italy
Pierluigi Rolandi , ST Microelectronics, Agrate Brianza, Italy
Claudio Mucci , ARCES, University of Bologna
Andrea Lodi , ARCES, University of Bologna
Arseni Vitkovski , ARCES, University of Bologna
Luca Vanzolini , ARCES, University of Bologna
pp. 1-6

An 0.9 x 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface (PDF)

Phillip Stanley-Marbell , Dept. of ECE, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA
Diana Marculescu , Dept. of ECE, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, USA
pp. 1-6

An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio (PDF)

Zhuan Ye , Wireless Solutions Research Center 1301 E. Algonquin Rd. Schaumburg, IL 60196, USA +1-847-576-4846; Wireless Solutions Research Center 1301 E. Algonquin Rd. Schaumburg, IL 60196, USA +1-847-538-3847; Department of EECS Northwestern University, Evanston, IL 60208, USA +1-847-467-1168, Zhuan@labs.mot.com
John Grosspietsch , Wireless Solutions Research Center 1301 E. Algonquin Rd. Schaumburg, IL 60196, USA +1-847-576-4846; Wireless Solutions Research Center 1301 E. Algonquin Rd. Schaumburg, IL 60196, USA +1-847-538-3847, johng@labs.mot.com
Gokhan Memik , Wireless Solutions Research Center 1301 E. Algonquin Rd. Schaumburg, IL 60196, USA +1-847-576-4846; Department of EECS Northwestern University, Evanston, IL 60208, USA +1-847-467-1168, memik@ece. northwestern.edu
pp. 1-6

A Non-Intrusive Isolation Approach for Soft Cores (PDF)

Ozgur Sinanoglu , Math & Computer Science Department, Kuwait University, Safat, Kuwait 13060, ozgur@sci.kuniv.edu.kw
Tsvetomir Petrov , Qualcomm CDMA Technologies, Qualcomm, Inc., San Diego, CA, tpetrov@qualcomm. com
pp. 1-6

Unknown Blocking Scheme for Low Control Data Volume and High Observability (PDF)

Seongmoon Wang , NEC Labs. America, Princeton, NJ, swang@nec-labs.com
Wenlong Wei , NEC Labs. America, Princeton, NJ, wwei@nec-labs.com
Srimat T. Chakradhar , NEC Labs. America, Princeton, NJ, chak@nec-labs.com
pp. 1-6

Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling (Abstract)

Quming Zhou , Dept. of Electrical and Computer Engg., Rice University, Houston, TX, USA, quming@rice.edu
Kedarnath J. Balakrishnan , NEC Laboratories America, 4 Independence Way, Princeton, NJ, USA, bala@nec-labs.com
pp. 1-6

High-Level Test Synthesis for Delay Fault Testability (PDF)

Sying-Jyan Wang , Department of Computer Science, National Chung-Hsing University, Taichung 402, Taiwan, ROC
Tung-Hua Yeh , Department of Computer Science, National Chung-Hsing University, Taichung 402, Taiwan, ROC
pp. 1-6

Bus Access Optimisation for FlexRay-based Distributed Embedded Systems (PDF)

Traian Pop , Department of Computer and Information Science, Linköping University, Sweden, trapo@ida.liu.se
Paul Pop , Informatics and Mathematical Modelling, Technical University of Denmark, Denmark, paul.pop@imm.dtu.dk
Petru Eles , Department of Computer and Information Science, Linköping University, Sweden, petel@ida.liu.se
Zebo Peng , Department of Computer and Information Science, Linköping University, Sweden, zebpe@ida.liu.se
pp. 1-6

A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors (PDF)

Nadathur Satish , Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, CA, USA, nrsatish@eecs.berkeley.edu
Kaushik Ravindran , Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, CA, USA, kaushikr@eecs.berkeley.edu
Kurt Keutzer , Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, CA, USA, keutzer@eecs.berkeley.edu
pp. 1-6

Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow (PDF)

Chuan Lin , Magma Design Automation, Santa Clara, CA 95054, clin@magma-da.com
Aiguo Xie , Calypto Design Systems, Santa Clara, CA 95054, axie@calypto.com
Hai Zhou , EECS Department, Northwestern University, Evanston, IL 60208, haizhou@eecs.northwestern.edu
pp. 1-6

Simulation-based reusable posynomial models for MOS transistor parameters (PDF)

Varun Aggarwal , EvoDesignOpt Group, CSAIL, MIT, USA, varun-ag@mit.edu
Una-May O'Reilly , EvoDesignOpt Group, CSAIL, MIT, USA, unamay@csail.mit.edu
pp. 1-6

Trade-Off Design of Analog Circuits using Goal Attainment and "Wave Front" Sequential Quadratic Programming (PDF)

Daniel Mueller , Institute for Electronic Design Automation, TU Muenchen
Helmut Graeb , Institute for Electronic Design Automation, TU Muenchen
Ulf Schlichtmann , Institute for Electronic Design Automation, TU Muenchen
pp. 1-6

An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection (Abstract)

Tom Eeckelaert , Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Leuven, Tom.Eeckelaert@esat.kuleuven.ac.be
Raf Schoofs , Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Leuven
Georges Gielen , Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Leuven
Michiel Steyaert , Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Leuven
Willy Sansen , Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Leuven
pp. 1-6

A Coefficient Optimization and Architecture Selection Tool for ΣΔ Modulators in MATLAB (PDF)

Omer Yetik , Bo¿aziçi University, Dept. of Electrical and Electronic Eng., 34342 Bebek, ¿stanbul, Turkey, omer.yetik@boun.edu.tr
Orkun Saglamdemir , Bo¿aziçi University, Dept. of Electrical and Electronic Eng., 34342 Bebek, ¿stanbul, Turkey, orkun.saglamdemir@boun.edu.tr
Selcuk Talay , Bo¿aziçi University, Dept. of Electrical and Electronic Eng., 34342 Bebek, ¿stanbul, Turkey, talays@boun.edu.tr
Gunhan Dundar , Bo¿aziçi University, Dept. of Electrical and Electronic Eng., 34342 Bebek, ¿stanbul, Turkey, dundar@boun.edu.tr
pp. 1-6

Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems (PDF)

Wei Zheng , University of California at Berkeley, zhengwei@eecs.berkeley.edu
Marco di Natale , University of California at Berkeley; General Motors Research, dinatale@eecs.berkeley.edu
Claudio Pinello , General Motors Research; Cadence Berkeley Labs, pinello@cadence.com
Paolo Giusto , General Motors Research, paolo.giusto@gm.com
Alberto Sangiovanni Vincentelli , University of California at Berkeley, alberto@eecs.berkeley.edu
pp. 1-6

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures (PDF)

Chris Ostler , Department of CSE, Arizona State University, Tempe, AZ 85287, chrisost@asu.edu
Karam S. Chatha , Department of CSE, Arizona State University, Tempe, AZ 85287, kchatha@asu.edu
pp. 1-6

A Smooth Refinement Flow for Co-designing HW and SW Threads (PDF)

Paolo Destro , Dipartimento di Informatica - Università di Verona, Strada le Grazie 15, 37134 Verona, Italy, destro@sci.univr.it
Franco Fummi , Dipartimento di Informatica - Università di Verona, Strada le Grazie 15, 37134 Verona, Italy, fummi@sci.univr.it
Graziano Pravadelli , Dipartimento di Informatica - Università di Verona, Strada le Grazie 15, 37134 Verona, Italy, pravadelli@sci.univr.it
pp. 1-6

Speeding Up SystemC Simulation through Process Splitting (Abstract)

Youssef N. Naguib , Electronics and Communication Engineering, Cairo University, Giza, Egypt, ynaguib@ieee.org
Rafik S. Guindi , Electronics and Communication Engineering, Cairo University, Giza, Egypt, rguindi@ieee.org
pp. 1-6

An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip (PDF)

Akash Kumar , Eindhoven University of Technology, Eindhoven, The Netherlands, a.kumar@tue.nl
Andreas Hansson , Eindhoven University of Technology, Eindhoven, The Netherlands
Jos Huisken , Silicon Hive, Eindhoven, The Netherlands
Henk Corporaal , Eindhoven University of Technology, Eindhoven, The Netherlands
pp. 1-6

Hard Real-Time Reconfiguration Port Scheduling (PDF)

Florian Dittmann , Heinz Nixdorf Institute, University of Paderborn, Fuerstenallee 11, 33102 Paderborn, Germany, roichen@upb.de
Stefan Frank , Heinz Nixdorf Institute, University of Paderborn, Fuerstenallee 11, 33102 Paderborn, Germany, sfrank@upb.de
pp. 1-6

An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs (PDF)

Jin Cui , Department of Computer Science, Northeastern University, Shenyang, China
Qingxu Deng , Department of Computer Science, Northeastern University, Shenyang, China
Xiuqiang He , Department of Computer Science and Engineering, Hong Kong University of Science and Technology, Hong Kong, China
Zonghua Gu , Department of Computer Science and Engineering, Hong Kong University of Science and Technology, Hong Kong, China
pp. 1-6

Improving Utilization of Reconfigurable Resources Using Two Dimensional Compaction (PDF)

Ahmed A. el Farag , Computer Eng. Dept., Faculty of Eng., Cairo University, Giza, Egypt
Hatem M. El-Boghdadi , Computer Eng. Dept., Faculty of Eng., Cairo University, Giza, Egypt. helboghdadi@eng.cu.edu.eg
Samir I. Shaheen , Computer Eng. Dept., Faculty of Eng., Cairo University, Giza, Egypt
pp. 1-6

Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems (PDF)

Roman Lysecky , Department of Electrical and Computer Engineering, University of Arizona, rlysecky@ece.arizona.edu
pp. 1-6

Using Dynamic Voltage Scaling to Reduce the Configuration Energy of Run Time Reconfigurable Devices (PDF)

Yang Qu , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FIN-90571 Oulu, Finland, Yang.Qu@vtt.fi
Juha-Pekka Soininen , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FIN-90571 Oulu, Finland
Jari Nurmi , Tampere University of Technology, Korkeakoulunkatu 10, Tampere, Finland
pp. 1-6

A Shift Register based Clause Evaluator for Reconfigurable SAT Solver (PDF)

Mona Safar , Computer and Systems Engineering Department, Ain Shams University, Cairo, Egypt
Mohamed Shalan , Computer and Systems Engineering Department, Ain Shams University, Cairo, Egypt
M. Watheq El-Kharashi , Computer and Systems Engineering Department, Ain Shams University, Cairo, Egypt
Ashraf Salem , Mentor Graphics Egypt, Cairo, Egypt
pp. 1-6

Efficient High-Performance ASIC Implementation of JPEG-LS Encoder (PDF)

Markos Papadonikolakis , Alma Technologies, Pikermi Attica, Greece
Vasilleios Pantazis , Desics Department, IMEC, Leuven, Belgium
Athanasios P. Kakarountas , VLSI Design Lab., Electrical & Computer Engineering Department, University of Patras, Rio, Greece; Department of Informatics on Biomedicine, University of Central Greece, Lamia, Greece
pp. 1-6

Improve CAM Power Efficiency Using Decoupled Match Line Scheme (PDF)

Yen-Jen Chang , Dept. of Computer Science, National ChungHsing University, Taichung, Taiwan, ychang@cs.nchu.edu.tw
Yuan-Hong Liao , Dept. of Computer Science, National ChungHsing University, Taichung, Taiwan, s9356042@cs.nchu.edu.tw
Shanq-Jang Ruan , Dept. of Electronic Engineering, NTUST, Taipei, Taiwan, sjruan@mail.ntust.edu.tw
pp. 1-6

Cyclostationary Feature Detection on a tiled-SoC (Abstract)

Andre B.J. Kokkeler , University of Twente, P.O. Box 217, 7500, AE Enschede, The Netherlands. Phone: +31 53 4894291, Fax: +31 53 4894571, a.b.j.kokkeler@utwente.nl
Gerard J.M. Smit , University of Twente, P.O. Box 217, 7500, AE Enschede, The Netherlands
Thijs Krol , University of Twente, P.O. Box 217, 7500, AE Enschede, The Netherlands
Jan Kuper , University of Twente, P.O. Box 217, 7500, AE Enschede, The Netherlands
pp. 1-6

Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter (PDF)

C. Arbelo , Research Institute for Applied Microelectronics (IUMA), Department of Electronic Engineering and Control (DIEA), University of Las Palmas de Gran Canaria, E-35017, Spain
A. Kanstein , Freescale Inc., Toulouse, France
S. Lopez , Research Institute for Applied Microelectronics (IUMA), Department of Electronic Engineering and Control (DIEA), University of Las Palmas de Gran Canaria, E-35017, Spain
J. F. Lopez , Research Institute for Applied Microelectronics (IUMA), Department of Electronic Engineering and Control (DIEA), University of Las Palmas de Gran Canaria, E-35017, Spain
M. Berekovic , IMEC, Leuven, Belgium
R. Sarmiento , Research Institute for Applied Microelectronics (IUMA), Department of Electronic Engineering and Control (DIEA), University of Las Palmas de Gran Canaria, E-35017, Spain
J.-Y. Mignolet , IMEC, Leuven, Belgium
pp. 1-6

An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm (PDF)

Esra Sahin , Faculty of Engineering and Natural Sciences, Sabanci University, 34956, Istanbul, TURKEY
Ilker Hamzaoglu , Faculty of Engineering and Natural Sciences, Sabanci University, 34956, Istanbul, TURKEY, Email: hamzaoglu@sabanciuniv.edu
pp. 1-6

An FPGA Implementation of Decision Tree Classification (PDF)

Ramanathan Narayanan , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208, USA, ran310@eecs.northwestern.edu
Daniel Honbo , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208, USA, dkh301@eecs.northwestern.edu
Gokhan Memik , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208, USA, memik@eecs.northwestern.edu
Alok Choudhary , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208, USA, choudhar@eecs.northwestern.edu
Joseph Zambreno , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208, USA; Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA, zambreno@iastate.edu
pp. 1-6

Radix 4 SRT Division with Quotient Prediction and Operand Scaling (PDF)

Nishant R Srivastava , Illinois Institute of Technology, Chicago, Illinois 60616, USA
pp. 1-6

SoC Testing Using LFSR Reseeding, and Scan-Slice- Based TAM Optimization and Test Scheduling (PDF)

Zhanglei Wang , ECE Dept., Duke University, Durham, NC, E-mail: zw8@ee.duke.edu
Krishnendu Chakrabarty , ECE Dept., Duke University, Durham, NC, E-mail: krish@ee.duke.edu
Seongmoon Wang , NEC Laboratories America, Princeton, NJ, E-mail: swang@nec-labs.com
pp. 1-6

Optimized Integration of Test Compression and Sharing for SOC Testing (PDF)

Anders Larsson , Embedded Systems Laboratory, Linköpings Universitet, SE-582 83 Linköping, Sweden
Erik Larsson , Embedded Systems Laboratory, Linköpings Universitet, SE-582 83 Linköping, Sweden
Petru Eles , Embedded Systems Laboratory, Linköpings Universitet, SE-582 83 Linköping, Sweden
Zebo Peng , Embedded Systems Laboratory, Linköpings Universitet, SE-582 83 Linköping, Sweden
pp. 1-6

A Sophisticated Memory Test Engine for LCD Display Drivers (PDF)

Oliver Spang , University of Siegen, Computer Science, Siegen, Germany
Hans-Martin von Staudt , Dialog Semiconductor, Nabern, Germany
Michael G. Wahl , University of Siegen, Computer Science, Siegen, Germany
pp. 1-6

Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor (PDF)

Thuyen Le , IBM Deutschland Entwicklung GmbH, D-71032 Böblingen, Germany, thuyenle@de.ibm.com
Tilman Glokler , IBM Deutschland Entwicklung GmbH, D-71032 Böblingen, Germany, gloekler@de.ibm.com
Jason Baumgartner , IBM Systems & Technology Group, Austin, TX 78758, baumgarj@us.ibm.com
pp. 1-6

Low Cost Debug Architecture using Lossy Compression for Silicon Debug (PDF)

Ehab Anis , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada, Email: anise@mcmaster.ca
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada, Email: nicola@ece.mcmaster.ca
pp. 1-6

An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers (Abstract)

Tomokazu Yoneda , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan, yoneda@is.naist.jp
Masahiro Imanishi , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan
Hideo Fujiwara , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, 630-0192, Japan, fujiwara@is.naist.jp
pp. 1-6

Microprocessors in the Era of Terascale Integration (Abstract)

Shekhar Borkar , Intel Corporation, 2111 NE 25th Ave, Hillsboro, OR, 97124, Shekhar.Y.Borkar@intel.com
Norman P. Jouppi , Hewlett Packard, 1501 Page Mill Road, Palo Alto, CA 90304, norm.jouppi@hp.com
Per Stenstrom , Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Goteborg, Sweden, pers@ce.chalmers.se
pp. 1-6

CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions (Abstract)

M. Zhang , Institute of Microelectronic Systems, Leibniz University of Hannover, Germany, zhang@ims.uni-hannover.de
M. Olbrich , Institute of Microelectronic Systems, Leibniz University of Hannover, Germany, olbrich@ims.uni-hannover.de
D. Seider , Qimonda AG, David.Seider@qimonda.com
M. Frerichs , Qimonda AG, Martin.Frerichs@qimonda.com
H. Kinzelbach , Infineon Technologies AG, Harald.Kinzelbach@infineon.com
E. Barke , Institute of Microelectronic Systems, Leibniz University of Hannover, Germany, barke@ims.uni-hannover.de
pp. 1-6

A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs (Abstract)

Ghiath Al-Sammane , Concordia University, Montreal, Quebec, Canada, sammane@ece.concordia.ca
Mohamed H. Zaki , Concordia University, Montreal, Quebec, Canada, mzaki@ece.concordia.ca
Sofiene Tahar , Concordia University, Montreal, Quebec, Canada, tahar@ece.concordia.ca
pp. 1-6

Efficient Nonlinear Distortion Analysis of RF Circuits (PDF)

Dani Tannir , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada, H3A 2A7, dani.tannir@mail.mcgill.ca
Roni Khazaka , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada, H3A 2A7, roni.khazaka@mcgill.ca
pp. 1-6

Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis (Abstract)

Jonathan Borremans , IMEC, Leuven, Belgium; Vrije Universiteit Brussel, Brussels, Belgium
Ludwig de Locht , IMEC, Leuven, Belgium; Vrije Universiteit Brussel, Brussels, Belgium
Piet Wambacq , IMEC, Leuven, Belgium; Vrije Universiteit Brussel, Brussels, Belgium
Yves Rolain , Vrije Universiteit Brussel, Brussels, Belgium
pp. 1-6

Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations (PDF)

J. Lataire , Vrije Universiteit Brussel, Department ELEC, Pleinlaan 2, B1050 Brussels, Belgium, email: jlataire@vub.ac.be
G. Vandersteen , IMEC vzw, Kapeldreef 75, B3001 Leuven, Belgium; Vrije Universiteit Brussel, Department ELEC, Pleinlaan 2, B1050 Brussels, Belgium
R. Pintelon , Vrije Universiteit Brussel, Department ELEC, Pleinlaan 2, B1050 Brussels, Belgium
pp. 1-6

Performance Analysis of Complex Systems by Integration of Dataflow Graphs and Compositional Performance Analysis (PDF)

Simon Schliecker , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, Germany, schliecker@ida.ing.tu-bs.de
Steffen Stein , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, Germany, stein@ida.ing.tu-bs.de
Rolf Ernst , Institute of Computer and Communication Network Engineering, Technical University of Braunschweig, Germany, ernst@ida.ing.tu-bs.de
pp. 1-6

Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL (Abstract)

Hiren D. Patel , Virginia Polytechnic Institute and State University, Bradley Department of Electrical and Computer Engineering. E-mail: hiren@vt.edu
Sandeep K. Shukla , Virginia Polytechnic Institute and State University, Bradley Department of Electrical and Computer Engineering. E-mail: shukla@vt.edu
pp. 1-6

A Calculator for Pareto Points (PDF)

Marc Geilen , Eindhoven University of Technology, Department of Electrical Engineering, m.c.w.geilen@tue.nl
Twan Basten , Eindhoven University of Technology, Department of Electrical Engineering, a.a.basten@tue.nl
pp. 1-6

Modeling and Simulation to the Design of ΣΔ Fractional-N Frequency Synthesizer (PDF)

Shuilong Huang , Department of Electronics Engineering, Tsinghua University, Beijing 100084, China
Huainan Ma , RFIC Corporation, Beijing 100084, China
Zhihua Wang , Department of Electronics Engineering, Tsinghua University, Beijing 100084, China
pp. 1-6

System Level Power Optimization of Sigma-Delta Modulator (PDF)

Fei Gong , Institute of VLSI Design, Zhejiang University, Hangzhou, 310027, P.R. China, gongfei@vlsi.zju.edu.cn
Xiaobo Wu , Institute of VLSI Design, Zhejiang University, Hangzhou, 310027, P.R. China
pp. 1-4

Executable system-level specification models containing UML-based behavioral patterns (PDF)

Leandro Soares Indrusiak , Institute of Microelectronic Systems - Technische Universität Darmstadt, E-mail: indrusiak@mes.tu-darmstadt.de
Andreas Thuy , Institute of Microelectronic Systems - Technische Universität Darmstadt, E-mail: a.thuy@gmx.net
Manfred Glesner , Institute of Microelectronic Systems - Technische Universität Darmstadt, E-mail: glesner@mes.tu-darmstadt.de
pp. 1-6

Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures (PDF)

Soumya Eachempati , Dept. of Computer Science and Engineering, Pennsylvania State University, USA, eachempa@cse.psu.edu
Arthur Nieuwoudt , Dept. of Electrical and Computer Engineering, Rice University, USA, abnieu@rice.edu
Aman Gayasen , Synopsys Inc., USA, gayasen@synopsys.com
N. Vijaykrishnan , Dept. of Computer Science and Engineering, Pennsylvania State University, USA, vijay@cse.psu.edu
Yehia Massoud , Dept. of Electrical and Computer Engineering, Rice University, USA, massoud@rice.edu
pp. 1-6

Two-Level Microprocessor-Accelerator Partitioning (Abstract)

Scott Sirowy , Department of Computer Science and Engineering -University of California, Riverside, ssirowy@cs.ucr.edu
Yonghui Wu , Department of Computer Science and Engineering -University of California, Riverside, yonghui@cs.ucr.edu
Stefano Lonardi , Department of Computer Science and Engineering -University of California, Riverside, stelo@cs.ucr.edu
Frank Vahid , Department of Computer Science and Engineering -University of California, Riverside; Center for Embedded Computer Systems, University of California, Irvine, vahid@cs.ucr.edu
pp. 1-6

Design Space Exploration of Partially Re-configurable Embedded Processors (Abstract)

A. Chattopadhyay , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany, anupam@iss.rwth-aachen.de
W. Ahmed , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
K. Karuri , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
D. Kammler , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
R. Leupers , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
G. Ascheid , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
H. Meyr , Integrated Signal Processing Systems, RWTH Aachen University 52056 Aachen, Germany
pp. 1-6

Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor (PDF)

Hamid Noori , Kyushu University, Fukuoka, Japan, noori@c.csce.kysuhu-u.ac.jp
Farhad Mehdipour , Amirkabir University of Technology, Tehran, Iran, mehdipur@ce.aut.ac.ir
Kazuaki Murakami , Kyushu University, Fukuoka, Japan, murakami@i.kyushu-u.ac.jp
Koji Inoue , Kyushu University, Fukuoka, Japan, inoue@i.kyushu-u.ac.jp
Maziar Goudarzi , Kyushu University, Fukuoka, Japan, goudarzi@slrc.kyushu-u.ac.jp
pp. 1-6

Low Complexity LDPC Code Decoders for Next Generation Standards (PDF)

T. Brack , Microelectronic System Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany
M. Alles , Microelectronic System Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany
T. Lehnigk-Emden , Microelectronic System Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany
F. Kienle , Microelectronic System Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany
N. Wehn , Microelectronic System Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany
N. E. L'Insalata , Department of Information Engineering, University of Pisa, via G. Caruso, 56122, Pisa, Italy
F. Rossi , Department of Information Engineering, University of Pisa, via G. Caruso, 56122, Pisa, Italy
M. Rovini , Department of Information Engineering, University of Pisa, via G. Caruso, 56122, Pisa, Italy
L. Fanucci , Department of Information Engineering, University of Pisa, via G. Caruso, 56122, Pisa, Italy
pp. 1-6

Non-fractional parallelism in LDPC Decoder implementations (PDF)

John Dielissen , NXP Semiconductors, High Tech Campus 31, 5656 AE Eindhoven, The Netherlands, E-mail: john.dielissen@nxp.com
Andries Hekstra , NXP Semiconductors, High Tech Campus 31, 5656 AE Eindhoven, The Netherlands
pp. 1-6

Minimum-Energy LDPC Decoder for Real-Time Mobile Application (PDF)

Weihuang Wang , Department of Electrical and Computer Engineering, Texas A&M University, TX 77840, Email: whwang@ece.tamu.edu
Gwan Choi , Department of Electrical and Computer Engineering, Texas A&M University, TX 77840, Email: gchoi@ece.tamu.edu
pp. 1-6

Pipelined Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture (PDF)

Zahid Khan , School of Engineering and Electronics, The University of Edinburgh, Mayfield Road, Edinburgh, EH9 3JL, z.khan@ed.ac.uk
Tughrul Arslan , School of Engineering and Electronics, The University of Edinburgh, Mayfield Road, Edinburgh, EH9 3JL
pp. 1-6

Implementation of AES/Rijndael on a dynamically reconfigurable architecture (PDF)

Claudio Mucci , ARCES - University of Bologna, Viale Pepoli 3/2, Bologna, Italy
Luca Vanzolini , ARCES - University of Bologna, Viale Pepoli 3/2, Bologna, Italy
Andrea Lodi , ARCES - University of Bologna, Viale Pepoli 3/2, Bologna, Italy
Antonio Deledda , ARCES - University of Bologna, Viale Pepoli 3/2, Bologna, Italy
Roberto Guerrieri , ARCES - University of Bologna, Viale Pepoli 3/2, Bologna, Italy
Fabio Campi , FTM, STMicroelectronics, Viale Olivetti 2, Agrate Brianza (MI)
Mario Toma , FTM, STMicroelectronics, Viale Olivetti 2, Agrate Brianza (MI)
pp. 1-6

Using the Inter- and Intra-Switch Regularity in NoC Switch Testing (PDF)

Mohammad Hosseinabady , Nanoelectronics-Center of Excellence, University of Tehran 14399 Tehran, Iran, mohammad@cad.ece.ut.ac.ir
Atefe Dalirsani , Nanoelectronics-Center of Excellence, University of Tehran 14399 Tehran, Iran, atefeh@cad.ece.ut.ac.ir
Zainalabedin Navabi , Nanoelectronics-Center of Excellence, University of Tehran 14399 Tehran, Iran, navabi@ece.neu.edu
pp. 1-6

Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips (PDF)

Kim Petersen , Dept. of Electronic Computer and Software Systems, Royal Institute of Technology (KTH), KTH/ICT/ECS, Electrum 229, SE-164 40 Kista, Sweden, +46 (0) 70 859 41 84, +46 (0) 8 790 41 27, kim.petersen@hdc.se
Johnny Oberg , Dept. of Electronic Computer and Software Systems, Royal Institute of Technology (KTH), KTH/ICT/ECS, Electrum 229, SE-164 40 Kista, Sweden, +46 (0) 70 859 41 84, +46 (0) 8 790 41 27, johnny@imit.kth.se
pp. 1-6

Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks (PDF)

Oussama Laouamri , DeFacTo Technologies, 167 rue de Mayoussard, 38 430 Moirans, FRANCE
Chouki Aktouf , DeFacTo Technologies, 167 rue de Mayoussard, 38 430 Moirans, FRANCE
pp. 1-6

Fast Memory Footprint Estimation based on Maximal Dependency Vector Calculation (PDF)

Q. Hu , Norwegian University of Science and Technology, Trondheim, Norway, qubo.hu@iet.ntnu.no
A. Vandecappelle , IMEC vzw, Leuven, Belgium, vdcappel@imec.be
P. G. Kjeldsberg , Norwegian University of Science and Technology, Trondheim, Norway, pgk@iet.ntnu.no
F. Catthoor , IMEC vzw, Leuven, Belgium; professor at Katholieke Universiteit Leuven, Belgium, catthoor@imec.be
M. Palkovic , IMEC vzw, Leuven, Belgium, palkovic@imec.be
pp. 1-6

Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations (Abstract)

Hongwei Zhu , Dept. of Computer Science, University of Illinois at Chicago, hzhu7@uic.edu
Ilie I. Luican , Dept. of Computer Science, University of Illinois at Chicago, iluica2@uic.edu
Florin Balasa , Dept. of Computer Science, University of Illinois at Chicago, fbalasa@uic.edu
pp. 1-6

The Impact of Loop Unrolling on Controller Delay in High Level Synthesis (PDF)

Srikanth Kurra , Dept. of Comp. Sc. & Engg., Indian Institute of Technology, New Delhi 110016, srikanth@cse.iitd.ac.in
Neeraj Kumar Singh , Intel Tech. India Pvt. Ltd., 136 Airport Road, Bangalore 560017, neeraj.k.singh@intel.com
Preeti Ranjan Panda , Dept. of Comp. Sc. & Engg., Indian Institute of Technology, New Delhi 110016, panda@cse.iitd.ac.in
pp. 1-6

Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip (PDF)

Scott Sirowy , Department of Computer Science and Engineering ¿ University of California, Riverside, ssirowy@cs.ucr.edu
Yonghui Wu , Department of Computer Science and Engineering ¿ University of California, Riverside, yonghui@cs.ucr.edu
Stefano Lonardi , Department of Computer Science and Engineering ¿ University of California, Riverside, stelo@cs.ucr.edu
Frank Vahid , Department of Computer Science and Engineering ¿ University of California, Riverside; Center for Embedded Computer Systems, University of California, Irvine, Vahid@cs.ucr.edu
pp. 1-6

System-Level Process Variation Driven Throughput Analysis for Single and Multiple Voltage-Frequency Island Designs (PDF)

Siddharth Garg , Dept. of Electrical and Computer Engineering, Carnegie Mellon University, sgarg1@andrew.cmu.edu
Diana Marculescu , Dept. of Electrical and Computer Engineering, Carnegie Mellon University, dianam@ece.cmu.edu
pp. 1-6

Reliability-Aware System Synthesis (PDF)

Michael Glass , University of Erlangen-Nuremberg, Germany, glass@cs.fau.de
Martin Lukasiewycz , University of Erlangen-Nuremberg, Germany, martin.lukasiewycz@cs.fau.de
Thilo Streichert , University of Erlangen-Nuremberg, Germany, streichert@cs.fau.de
Christian Haubelt , University of Erlangen-Nuremberg, Germany, haubelt@cs.fau.de
Jurgen Teich , University of Erlangen-Nuremberg, Germany, teich@cs.fau.de
pp. 1-6

Flexibility-oriented Design Methodology for Reconfigurable ΔΣ Modulators (PDF)

Pengbo Sun , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, Stony Brook, NY, 11794-2350, psun@ece.sunysb.edu
Ying Wei , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, Stony Brook, NY, 11794-2350, ywei@ece.sunysb.edu
Alex Doboli , Department of Electrical and Computer Engineering, State University of New York at Stony Brook, Stony Brook, NY, 11794-2350, adoboli@ece.sunysb.edu
pp. 1-6

Experimental Validation of a Tuning Algorithm for High-Speed Filters (PDF)

G. Matarrese , Dipartimento di Elettrotecnica ed Elettronica, Politecnico di Bari, Italy
C. Marzocca , Dipartimento di Elettrotecnica ed Elettronica, Politecnico di Bari, Italy
F. Corsi , Dipartimento di Elettrotecnica ed Elettronica, Politecnico di Bari, Italy
S. D'Amico , Dipartimento di Ingegneria dell'Innovazione, Università di Lecce, Italy
A. Baschirotto , Dipartimento di Ingegneria dell'Innovazione, Università di Lecce, Italy
pp. 1-6

Design of High-Resolution MOSFET-Only Pipelined ADCs with Digital Calibration (Abstract)

Hamed Aminzadeh , Integrated Systems Lab., EE Dept., Ferdowsi University of Mashhad, Mashhad, Iran
Mohammad Danaie , Integrated Systems Lab., EE Dept., Ferdowsi University of Mashhad, Mashhad, Iran
Reza Lotfi , Integrated Systems Lab., EE Dept., Ferdowsi University of Mashhad, Mashhad, Iran
pp. 1-6

A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems (PDF)

Jafar Savoj , Rambus Inc., Los Altos, CA
Ali-Azam Abbasfar , Rambus Inc., Los Altos, CA
Amir Amirkhany , Stanford University
Bruno W. Garlepp , Rambus Inc., Los Altos, CA
Mark A. Horowitz , Stanford University
pp. 1-6

Automatic Synthesis of Compressor Trees: Reevaluating Large Counters (PDF)

Ajay K. Verma , Ecole Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, CH-1015 Lausanne, Switzerland, AjayKumar.Verma@epfl.ch
Paolo Ienne , Ecole Polytechnique Fédérale de Lausanne (EPFL), School of Computer and Communication Sciences, CH-1015 Lausanne, Switzerland, Paolo.Ienne@epfl.ch
pp. 1-6

Area Optimization of Multi-Cycle Operators in High-Level Synthesis (PDF)

M. C. Molina , Dpto. Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, cmolinap@fdi.ucm.es
R. Ruiz-Sautua , Dpto. Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, rsautua@fdi.ucm.es
J. M. Mendias , Dpto. Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, mendias@dacya.ucm.es
R. Hermida , Dpto. Arquitectura de Computadores y Automática, Universidad Complutense de Madrid, rhermida@dacya.ucm.es
pp. 1-6

Data-Flow Transformations using Taylor Expansion Diagrams (PDF)

M. Ciesielski , University of Massachusetts, Department of Electrical & Computer Engineering, Amherst, MA 01003, USA, ciesiel@ecs.umass.edu
S. Askar , University of Massachusetts, Department of Electrical & Computer Engineering, Amherst, MA 01003, USA, saskar@ecs.umass.edu
D. Gomez-Prado , University of Massachusetts, Department of Electrical & Computer Engineering, Amherst, MA 01003, USA, dgomezpr@ecs.umass.edu
J. Guillot , Laboratoire LESTER, Université de Bretagne Sud, 56321 Lorient, France, jguillot@univ-ubs.fr
E. Boutillon , Laboratoire LESTER, Université de Bretagne Sud, 56321 Lorient, France, emmanuel.boutillon@univ-ubs.fr
pp. 1-6

Automatic Application Specific Floating-point Unit Generation (PDF)

Yee Jern Chong , School of Computer Science & Engineering, University of New South Wales, Sydney, Australia, yeejernc@cse.unsw.edu.au
Sri Parameswaran , School of Computer Science & Engineering, University of New South Wales, Sydney, Australia, sridevan@cse.unsw.edu.au
pp. 1-6

Time-Constrained Clustering for DSE of Clustered VLIW-ASP (PDF)

Mario Scholzel , Department of Computer Science at Brandenburg University of Technology at Cottbus, Germany
pp. 1-6

Timing Simulation of Interconnected AUTOSAR Software-Components (PDF)

Matthias Krause , FZI Forschungszentrum Informatik, Haid-und-Neu-Strasse 10-14, 76131, Karlsruhe, Germany, mkrause@fzi.de
Oliver Bringmann , FZI Forschungszentrum Informatik, Haid-und-Neu-Strasse 10-14, 76131, Karlsruhe, Germany, bringmann@fzi.de
Andre Hergenhan , Carmeq GmbH, Carnotstrasse 4, 10587, Berlin, Germany, andre.hergenhan@carmeq.com
Gokhan Tabanoglu , Carmeq GmbH, Carnotstrasse 4, 10587, Berlin, Germany, goekhan.tabanoglu@carmeq.com
Wolfgang Rosentiel , Universität Tübingen, Sand 13, 72076, Tübingen, Germany, rosenstiel@fzi.de
pp. 1-6

FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications (PDF)

Sergio Saponara , Dept. Information Engineering, University of Pisa, Via Caruso 16, 56122, Pisa, Italy
Esa Petri , Consorzio Pisa Ricerche ¿ Divisione Applicazioni Microelettroniche (CPR-TEAM), C.so Italia 116, 56125, Pisa, Italy
Marco Tonarelli , Consorzio Pisa Ricerche ¿ Divisione Applicazioni Microelettroniche (CPR-TEAM), C.so Italia 116, 56125, Pisa, Italy
Iacopo del Corona , Dept. Information Engineering, University of Pisa, Via Caruso 16, 56122, Pisa, Italy
Luca Fanucci , Dept. Information Engineering, University of Pisa, Via Caruso 16, 56122, Pisa, Italy
pp. 1-6

Low-g Accelerometer Fast Prototyping for Automotive Applications (Abstract)

F. D'Ascoli , Dept. of Information Engineering, University of Pisa, Via Caruso, I-56122 Pisa, Italy
F. Iozzi , Dept. of Information Engineering, University of Pisa, Via Caruso, I-56122 Pisa, Italy
C. Marino , Dept. of Information Engineering, University of Pisa, Via Caruso, I-56122 Pisa, Italy
M. Melani , Dept. of Information Engineering, University of Pisa, Via Caruso, I-56122 Pisa, Italy
M. Tonarelli , Dept. of Information Engineering, University of Pisa, Via Caruso, I-56122 Pisa, Italy
L. Fanucci , Dept. of Information Engineering, University of Pisa, Via Caruso, I-56122 Pisa, Italy, Tel: +39 050 2217.668. Fax: +39 050 2217.522, e-mail: 1.fanucci@iet.unipi.it
A. Giambastiani , SensorDynamics AG, Via Giuntini 25, I-56123 Navacchio (Pisa), Italy
A. Rocchi , SensorDynamics AG, Via Giuntini 25, I-56123 Navacchio (Pisa), Italy
M. de Marinis , SensorDynamics AG, Via Giuntini 25, I-56123 Navacchio (Pisa), Italy
pp. 1-6

Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508 (PDF)

Riccardo Mariani , YOGITECH SpA Pisa, Italy, http://www.yogitech.com
Gabriele Boschi , YOGITECH SpA Pisa, Italy, http://www.yogitech.com
Federico Colucci , YOGITECH SpA Pisa, Italy, http://www.yogitech.com
pp. 1-6

Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System (PDF)

Christopher Claus , Technische Universität München, Lehrstuhl für integrierte Systeme, Theresienstrasse 90, 80333 München, Germany, Christopher.Claus@tum.de
Johannes Zeppenfeld , Technische Universität München, Lehrstuhl für integrierte Systeme, Theresienstrasse 90, 80333 München, Germany
Florian Muller , Technische Universität München, Lehrstuhl für integrierte Systeme, Theresienstrasse 90, 80333 München, Germany
Walter Stechele , Technische Universität München, Lehrstuhl für integrierte Systeme, Theresienstrasse 90, 80333 München, Germany
pp. 1-6

Towards a Methodology for the Quantitative Evaluation of Automotive Architectures (PDF)

Patrick Popp , General Motors Research and Development, 30500 Mound Road, Warren, MI 48090-9055
Marco di Natale , General Motors Research and Development, 30500 Mound Road, Warren, MI 48090-9055
Paolo Giusto , General Motors Research and Development, 350 Marine Parkway, RedWood Shores, CA 94065
Sri Kanajan , General Motors Research and Development, 30500 Mound Road, Warren, MI 48090-9055
Claudio Pinello , General Motors Research and Development, 350 Marine Parkway, RedWood Shores, CA 94065; Cadence Berkeley Labs
pp. 1-6

Dynamic Learning Based Scan Chain Diagnosis (PDF)

Yu Huang , Mentor Graphics Corporation, 300 Nickerson Road, Marlborough, MA 01752, USA
pp. 1-6

Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations (PDF)

Ozgur Sinanoglu , Math & Computer Science Department, Kuwait University, Safat, Kuwait 13060, ozgur@sci. kuniv.edu. kw
Philip Schremmer , Qualcomm CDMA Technologies, Qualcomm, Inc., San Diego, CA, philips@qualcomm. com
pp. 1-6

On Test Generation by Input Cube Avoidance (PDF)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U. S. A.
Sudhakar M. Reddy , Electrical & Computer Eng. Dept., University of Iowa, Iowa City, IA 52242, U. S. A.
pp. 1-6

Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution (PDF)

A. Ney , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpellier ¿ LIRMM, Université de Montpellier II / CNRS, 161, rue Ada ¿ 34392 Montpellier Cedex 5, France, Email: Ney@lirmm.fr URL:http://www.lirmm.fr/~w3mic
P. Girard , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpellier ¿ LIRMM, Université de Montpellier II / CNRS, 161, rue Ada ¿ 34392 Montpellier Cedex 5, France, Email: Girard@lirmm.fr URL:http://www.lirmm.fr/~w3mic
C. Landrault , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpellier ¿ LIRMM, Université de Montpellier II / CNRS, 161, rue Ada ¿ 34392 Montpellier Cedex 5, France, Email: Landrault@lirmm.fr URL:http://www.lirmm.fr/~w3mic
S. Pravossoudovitch , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpellier ¿ LIRMM, Université de Montpellier II / CNRS, 161, rue Ada ¿ 34392 Montpellier Cedex 5, France, Email: Pravossoudovitch@lirmm.fr URL:http://www.lirmm.fr/~w3mic
A. Virazel , Laboratoire d¿Informatique, de Robotique et de Microélectronique de Montpellier ¿ LIRMM, Université de Montpellier II / CNRS, 161, rue Ada ¿ 34392 Montpellier Cedex 5, France, Email: Virazel@lirmm.fr URL:http://www.lirmm.fr/~w3mic
M. Bastian , Infineon Technologies France, 2600, route des Crêtes ¿ 06560 Sophia-Antipolis, France, Email:magali.bastian@infineon.com URL:http://www.infineon.com
pp. 1-6

On Power-profiling and Pattern Generation for Power-safe Scan Tests (Abstract)

V.R. Devanathan , ASIC, Texas Instruments India Pvt. Ltd., Bangalore, India - 560 093, vrd@ti.com
C.P. Ravikumar , ASIC, Texas Instruments India Pvt. Ltd., Bangalore, India - 560 093, ravikumar@ti.com
V. Kamakoti , Department of Computer Science and Engg., Indian Institute of Technology, Madras, India -600 036, kama@cs.iitm.ernet.in
pp. 1-6

Automatic Test Pattern Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults (PDF)

Kunal P. Ganeshpure , University of Massachusetts Amherst, kganeshp@ecs.umass.edu
Sandip Kundu , University of Massachusetts Amherst, kundu@ecs.umass.edu
pp. 1-6

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation (PDF)

Yu Wang , Circuits and Systems Division, E.E. Dept., Tsinghua University, Beijing, 100084 China, wangyuu99@mails.tsinghua.edu.cn
Hong Luo , Circuits and Systems Division, E.E. Dept., Tsinghua University, Beijing, 100084 China, luohong99@mails.tsinghua.edu.cn
Ku He , Circuits and Systems Division, E.E. Dept., Tsinghua University, Beijing, 100084 China, heku00@mails.tsinghua.edu.cn
Rong Luo , Circuits and Systems Division, E.E. Dept., Tsinghua University, Beijing, 100084 China, luorong@tsinghua.edu.cn
Huazhong Yang , Circuits and Systems Division, E.E. Dept., Tsinghua University, Beijing, 100084 China, yanghz@tsinghua.edu.cn
Yuan Xie , CSE Department, Pennsylvania State University, University Park, PA, USA, yuanxie@cse.psu.edu
pp. 1-6

A Cross-Referencing-Based Droplet Manipulation Method for High-Throughput and Pin-Constrained Digital Microfluidic Arrays (Abstract)

Tao Xu , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA, tx@ee.duke.edu
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA, krish@ee.duke.edu
pp. 1-6

Reversible Circuit Technology Mapping from Non-reversible Specifications (PDF)

Zeljko Zilic , McGill University, zeljko.zilic@mcgill.ca
Katarzyna Radecka , McGill University; Concordia University
Ali Kazamiphur , McGill University; Concordia University
pp. 1-6

Distributed Power-Management Techniques for Wireless Network Video Systems (PDF)

Nicholas H. Zamora , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213-3890, USA, e-mail: nhz@ece.cmu.edu
Jung-Chun Kao , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213-3890, USA, e-mail: jungchuk@ece.cmu.edu
Radu Marculescu , Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213-3890, USA, e-mail: radum@ece.cmu.edu
pp. 1-6

Improving the Fault Tolerance of Nanometric PLA Designs (PDF)

Federico Angiolini , DEIS, University of Bologna, 40136 Bologna, Italy
M. Haykel Ben Jamaa , LSI, EPFL, 1015 Lausanne, Switzerland
David Atienza , LSI, EPFL, 1015 Lausanne, Switzerland; DACYA, Complutense University, 28040 Madrid, Spain
Luca Benini , DEIS, University of Bologna, 40136 Bologna, Italy
Giovanni de Micheli , LSI, EPFL, 1015 Lausanne, Switzerland
pp. 1-6

Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits (PDF)

K. Nepal , Brown University, Division of Engineering, Providence, RI 02912
R. I. Bahar , Brown University, Division of Engineering, Providence, RI 02912
J. Mundy , Brown University, Division of Engineering, Providence, RI 02912
W. R. Patterson , Brown University, Division of Engineering, Providence, RI 02912
A. Zaslavsky , Brown University, Division of Engineering, Providence, RI 02912
pp. 1-6

An Efficient Code Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods (PDF)

Seok-Won Seong , Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL 32611, USA. sseong@cise.ufl.edu
Prabhat Mishra , Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL 32611, USA. prabhat@cise.ufl.edu
pp. 1-6

Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints (PDF)

Kubilay Atasu , Department of Computing, Imperial College London; Department of Computer Engineering, Bogazici University, Istanbul, atasu@doc.ic.ac.uk
Robert G. Dimond , Department of Computing, Imperial College London, rgd@doc.ic.ac.uk
Oskar Mencer , Department of Computing, Imperial College London, oskar@doc.ic.ac.uk
Wayne Luk , Department of Computing, Imperial College London, wl@doc.ic.ac.uk
Can Ozturan , Department of Computer Engineering, Bogazici University, Istanbul, ozturaca@boun.edu.tr
Gunhan Dundar , Department of Electrical and Electronics Engineering, Bogazici University, Istanbul, dundar@boun.edu.tr
pp. 1-6

Resource Prediction for Media Stream Decoding (PDF)

Juan Hamers , ELIS Department, Ghent University, Belgium, Email: jmhamers@elis.UGent.be
Lieven Eeckhout , ELIS Department, Ghent University, Belgium, Email: leeckhou@elis.UGent.be
pp. 1-6

Register Pointer Architecture for Efficient Embedded Processors (PDF)

JongSoo Park , Computer Systems Laboratory, Stanford University, jongsoo@stanford.edu
Sung-Boem Park , Computer Systems Laboratory, Stanford University, sbpark84@stanford.edu
James D. Balfour , Computer Systems Laboratory, Stanford University, jbalfour@stanford.edu
David Black-Schaffer , Computer Systems Laboratory, Stanford University, davidbbs@stanford.edu
Christos Kozyrakis , Computer Systems Laboratory, Stanford University, kozyraki@stanford.edu
William J. Dally , Computer Systems Laboratory, Stanford University, dally@stanford.edu
pp. 1-6

Feasibility of Combined Area and Performance Optimization for Superscalar Processors Using Random Search (PDF)

S. van Haastregt , LIACS, Leiden University, svhaast@liacs.nl
P. M. W. Knijnenburg , Informatics Institute, University of Amsterdam, peterk@science.uva.nl
pp. 1-6

A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy (Abstract)

A. Milidonis , VLSI Design Lab., Electrical & Computer Engineering Department, University of Patras, Rio, Greece, e-mail: milidon@ee.upatras.gr
N. Alachiotis , VLSI Design Lab., Electrical & Computer Engineering Department, University of Patras, Rio, Greece
V. Porpodas , VLSI Design Lab., Electrical & Computer Engineering Department, University of Patras, Rio, Greece
H. Michail , VLSI Design Lab., Electrical & Computer Engineering Department, University of Patras, Rio, Greece
A. P. Kakarountas , VLSI Design Lab., Electrical & Computer Engineering Department, University of Patras, Rio, Greece
C. E. Goutis , VLSI Design Lab., Electrical & Computer Engineering Department, University of Patras, Rio, Greece
pp. 1-6

An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification (PDF)

Nikhil Jayakumar , Department of Electrical & Computer Engineering, Texas A&M University, College Station TX 77843. nikhil_AT_ece_DOT_tamu_DOT_edu
Sunil P Khatri , Department of Electrical & Computer Engineering, Texas A&M University, College Station TX 77843. sunilkhatri_AT_tamu_DOT_edu
pp. 1-6

Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network (PDF)

Meeta S. Gupta , Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA, meeta@eecs.harvard.edu
Jarod L. Oatley , Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA, jloatley@eecs.harvard.edu
Russ Joseph , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, rjoseph@ece.northwestern.edu
Gu-Yeon Wei , Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA, guyeon@eecs.harvard.edu
David M. Brooks , Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA, dbrooks@eecs.harvard.edu
pp. 1-6

Process Variation Tolerant Low Power DCT Architecture (PDF)

Nilanjan Banerjee , Purdue University, West Lafayette, IN-47907, USA., Email: nbanerje@purdue.edu
Georgios Karakonstantis , Purdue University, West Lafayette, IN-47907, USA., Email: gkarakon@purdue.edu
Kaushik Roy , Purdue University, West Lafayette, IN-47907, USA., Email: kaushik@purdue.edu
pp. 1-6

Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction (PDF)

Yan Lin , Electrical Engineering Department, University of California, Los Angeles, ylin@ee.ucla.edu, http://eda.ee.ucla.edu
Lei He , Electrical Engineering Department, University of California, Los Angeles, lhe@ee.ucla.edu, http://eda.ee.ucla.edu
pp. 1-6

Hardware Scheduling Support in SMP Architectures (PDF)

Andre C. Nacul , Center for Embedded Systems, University of California, Irvine, nacul@uci.edu
Francesco Regazzoni , ALaRI, University of Lugano, Lugano, Switzerland, regazzoni@alari.ch
Marcello Lajolo , NEC Laboratories America, Princeton, NJ, lajolo@nec-labs.com
pp. 1-6

A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method (PDF)

Tobias Bjerregaard , Teklatech, Diplomvej, building 377, 2800 Lyngby, Denmark, tob@teklatech.com
Mikkel Bystrup Stensgaard , TU of Denmark (DTU), IMM, Richard Petersens Plads, 2800 Lyngby, Denmark, mikkel.stensgaard@imm.dtu.dk
Jens Sparso , TU of Denmark (DTU), IMM, Richard Petersens Plads, 2800 Lyngby, Denmark, jsp@imm.dtu.dk
pp. 1-6

Butterfly and Benes-Based on-Chip Communication Networks for Multiprocessor Turbo Decoding (PDF)

Hazem Moussa , Electronics Department, ENST Bretagne, Technopôle Brest Iroise, 29238 Brest, France, hazem.moussa@enst-bretagne.fr
Olivier Muller , Electronics Department, ENST Bretagne, Technopôle Brest Iroise, 29238 Brest, France, olivier.muller@enst-bretagne.fr
Amer Baghdadi , Electronics Department, ENST Bretagne, Technopôle Brest Iroise, 29238 Brest, France, amer.baghdadi@enst-bretagne.fr
Michel Jezequel , Electronics Department, ENST Bretagne, Technopôle Brest Iroise, 29238 Brest, France, michel.jezequel@enst-bretagne.fr
pp. 1-6

Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms (PDF)

Simone Medardoni , ENDIF, University of Ferrara, 44100 Ferrara, Italy
Martino Ruggiero , DEIS, University of Bologna, 40136 Bologna, Italy
Davide Bertozzi , ENDIF, University of Ferrara, 44100 Ferrara, Italy
Luca Benini , DEIS, University of Bologna, 40136 Bologna, Italy
Giovanni Strano , STMicroelectronics, On-Chip Communication System, Catania, Italy
Carlo Pistritto , STMicroelectronics, On-Chip Communication System, Catania, Italy
pp. 1-6

Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs (PDF)

Jukka Suhonen , Tampere University of Technology / Institute of Computer and Digital Systems, P.O.Box 553, FIN-33101 Tampere, Finland, jukka.suhonen@tut.fi
Mikko Kohvakka , Tampere University of Technology / Institute of Computer and Digital Systems, P.O.Box 553, FIN-33101 Tampere, Finland, mikko.kohvakka@tut.fi
Mauri Kuorilehto , Tampere University of Technology / Institute of Computer and Digital Systems, P.O.Box 553, FIN-33101 Tampere, Finland, mauri.kuorilehto@tut.fi
Marko Hannikainen , Tampere University of Technology / Institute of Computer and Digital Systems, P.O.Box 553, FIN-33101 Tampere, Finland, marko.hannikainen@tut.fi
Timo D. Hamalainen , Tampere University of Technology / Institute of Computer and Digital Systems, P.O.Box 553, FIN-33101 Tampere, Finland, timo.d.hamalainen@tut.fi
pp. 1-6

Design methods for Security and Trust (Abstract)

Ingrid Verbauwhede , ESAT/COSIC, Katholieke Universiteit Leuven
Patrick Schaumont , Electrical and Computer Engineering Department, Virginia Tech
pp. 1-6

New safety critical radio altimeter for Airbus and related design flow (Abstract)

D. Hairion , THALES Communications, 160 bd de Valmy, 92704 Colombes, France, david.hairion@fr.thalesgroup.com
S. Emeriau , THALES Communications, 160 bd de Valmy, 92704 Colombes, France, simon.emeriau@fr.thalesgroup.com
E. Combot , THALES Communications, 160 bd de Valmy, 92704 Colombes, France
M. Sarlotte , THALES Communications, 160 bd de Valmy, 92704 Colombes, France
pp. 1-5

Introducing New Verification Methods into a Company's Design Flow: An Industrial User's Point of View (Abstract)

Robert Lissel , Robert Bosch GmbH, Automotive Electronics, Tuebinger Strasse 123, 72762 Reutlingen, Germany, robert.lissel@de.bosch.com
Joachim Gerlach , Robert Bosch GmbH, Automotive Electronics, Tuebinger Strasse 123, 72762 Reutlingen, Germany, joachim.gerlach@de.bosch.com
pp. 1-6

Testable Design for Advanced Serial-Link Transceivers (PDF)

Mitchell Lin , Department of Electrical and Computer Engineering, University of California, Santa Barbara, leitz@ece.ucsb.edu
Kwang-Ting Cheng , Department of Electrical and Computer Engineering, University of California, Santa Barbara
pp. 1-6

Method for Reducing Jitter in Multi-Gigahertz ATE (Abstract)

D.C. Keezer , Georgia Institute of Technology, Atlanta, Georgia USA
D. Minier , IBM, Bromont, Canada
P. Ducharme , IBM, Bromont, Canada
pp. 1-6

Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests (PDF)

Jens Anders , Philips Research Laboratories, 5656 AE Eindhoven, The Netherlands; University of Hannover, Institute of Electromagnetic Theory, 30167, Hannover, Germany, e-mail: jand@tet.uni-hannover.de
Shaji Krishnan , Philips Research Laboratories, 5656 AE Eindhoven, The Netherlands, e-mail: shaji.krishnan@philips.com
Guido Gronthoud , Philips Research Laboratories, 5656 AE Eindhoven, The Netherlands, e-mail: guido.gronthoud@philips.com
pp. 1-6

An ADC-BiST Scheme Using Sequential Code Analysis (Abstract)

Erdem S. Erdogan , Duke University Department of Electrical & Computer Engineering Durham, NC USA, ese@ee.duke.edu
Sule Ozev , Duke University Department of Electrical & Computer Engineering Durham, NC USA, sule@ee.duke.edu
pp. 1-6

Boosting SER Test for RF Transceivers by Simple DSP Technique (Abstract)

Jerzy Dabrowski , Department of Electrical Engineering, Linkping University, SE-581 83 Linkping, SWEDEN
Rashad Ramzan , Department of Electrical Engineering, Linkping University, SE-581 83 Linkping, SWEDEN
pp. 1-6

Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System Characterization of the Multi-Gigahertz Interfaces on the Cell Processor (Abstract)

P. Yeung , Rambus, Inc, http://www.rambus.com
A. Torres , Rambus, Inc, http://www.rambus.com
P. Batra , Rambus, Inc, http://www.rambus.com
pp. 1-6

Evaluation of test measures for LNA production testing using a multinormal statistical model (PDF)

J. Tongbong , TIMA Laboratory, 46 Avenue Félix Viallet, 38031 Grenoble, France
S. Mir , TIMA Laboratory, 46 Avenue Félix Viallet, 38031 Grenoble, France
J. L. Carbonero , ST Microelectronics, 850 Rue Jean Monnet, 38926 Crolles, France
pp. 1-6

Heterogeneous Systems on Chip and Systems in Package (PDF)

I. O'Connor , Ecole Centrale de Lyon, France
B. Courtois , TIMA Laboratory, France
K. Chakrabarty , Duke University, USA
N. Delorme , CEA-LETI, France
M. Hampton , Certess Inc., USA
J. Hartung , Cadence Europe, Germany
pp. 1-6

Engineering Trust with Semantic Guardians (PDF)

Ilya Wagner , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, MI 48109, iwagner@umich.edu
Valeria Bertacco , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, MI 48109, valeria@umich.edu
pp. 1-6

CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators (PDF)

Dohyung Kim , Department of Computer Science and Engineering, University of California, San Diego, USA, dhkim@ucsd.edu
Soonhoi Ha , School of Computer Science and Engineering, Seoul Nation University, Korea, sha@iris.snu.ac.kr
Rajesh Gupta , Department of Computer Science and Engineering, University of California, San Diego, USA, rgupta@ucsd.edu
pp. 1-6

A One-Shot Configurable-Cache Tuner for Improved Energy and Performance (Abstract)

Ann Gordon-Ross , Department of Computer Science and Engineering-University of California, Riverside, http://www.cs.ucr.edu/~, ann@cs.ucr.edu
Pablo Viana , Universidade Federal de Alagoas-Arapiraca-AL, Brazil
Frank Vahid , Department of Computer Science and Engineering-University of California, Riverside, http://www.cs.ucr.edu/~; center for Embedded Computer Systems-University of California, Irvine, vahid@cs.ucr.edu
Walid Najjar , Department of Computer Science and Engineering-University of California, Riverside, http://www.cs.ucr.edu/~, najjar@cs.ucr.edu
Edna Barros , Centro de Informtica-Federal University of Pernambuco, Recife-PE, Brazil
pp. 1-6

Design Fault Directed Test Generation for Microprocessor Validation (PDF)

Deepak A. Mathaikutty , FERMAT Lab, Virginia Tech, Blacksburg, VA 24061, mathaikutty@vt. edu
Sandeep K. Shukla , FERMAT Lab, Virginia Tech, Blacksburg, VA 24061, shukla@vt. edu
Sreekumar V. Kodakara , The University of Minnesota, Minneapolis, MN 55455, sreek@ece.umn.edu
David Lilja , The University of Minnesota, Minneapolis, MN 55455, lilja@ece.umn.edu
Ajit Dingankar , Validation Tools, Intel Corporation, Folsom, CA 95630, ajit.dingankar@intel.com
pp. 1-6

Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance (PDF)

Wolfgang Ecker , Infineon Technologies AG, IFAG COM BTSMT SD, 81726 Munich, Germany, Wolfgang.Ecker@infineon.com
Volkan Esen , Infineon Technologies AG, TU Darmstadt-MES/BTU Cottbus, Volkan.Esen@infineon.com
Lars Schonberg , Infineon Technologies AG, TU Darmstadt-MES/BTU Cottbus, Lars.Schönberg@infineon.com
Thomas Steininger , Infineon Technologies AG, TU Darmstadt-MES/BTU Cottbus, Thomas.Steininger@infineon.com
Michael Velten , Infineon Technologies AG, TU Darmstadt-MES/BTU Cottbus, Michael.Velten@infineon.com
Michael Hull , Infineon Technologies AG, University of Southampton, mh102@ecs.soton.ac.uk
pp. 1-6

Adaptive Power Management in Energy Harvesting Systems (PDF)

Clemens Moser , Swiss Federal Institute of Technology Zurich, moser@tik.ee.ethz.ch
Lothar Thiele , Swiss Federal Institute of Technology Zurich, thiele@tik.ee.ethz.ch
Davide Brunelli , University of Bologna, dbrunelli@deis.unibo.it
Luca Benini , University of Bologna, lbenini@deis.unibo.it
pp. 1-6

Stochastic Modeling and Optimization for Robust Power Management in a Partially Observable System (PDF)

Qinru Qiu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, New York 13902, USA, qqiu@binghamton.edu
Ying Tan , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, New York 13902, USA, ytan3@binghamton.edu
Qing Wu , Department of Electrical and Computer Engineering, Binghamton University, State University of New York, Binghamton, New York 13902, USA, qwu@binghamton.edu
pp. 1-6

Efficient and Scalable Compiler-Directed Energy Optimization for Realtime Applications (PDF)

Po-Kuan Huang , Electrical and Computer Engineering, University of California, Davis, pohuang@ece.ucdavis.edu
Soheil Ghiasi , Electrical and Computer Engineering, University of California, Davis, soheil@ece.ucdavis.edu
pp. 1-6

Peripheral-Conscious Scheduling on Energy Minimization for Weakly Hard Real-time Systems (PDF)

Linwei Niu , Department of Computer Science and Engineering, University of South Carolina, Columbia, SC 29208, niul@cse.sc.edu
Gang Quan , Department of Computer Science and Engineering, University of South Carolina, Columbia, SC 29208, gquan@cse.sc.edu
pp. 1-6

Task Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoC (PDF)

Ryo Watanabe , Research Center of Advanced Science and Technology (RCAST), The University of Tokyo, 4-6-1 Komaba, Meguro-City, Tokyo, Japan, Watanabe@hal.rcast.u-tokyo.ac.jp
Masaaki Kondo , Research Center of Advanced Science and Technology (RCAST), The University of Tokyo, 4-6-1 Komaba, Meguro-City, Tokyo, Japan, Kondo@hal.rcast.u-tokyo.ac.jp
Masashi Imai , Komaba Open Laboratory (KOL), The University of Tokyo, 4-6-1 Komaba, Meguro-City, Tokyo, Japan, Miyabi@hal.rcast.u-tokyo.ac.jp
Hiroshi Nakamura , Research Center of Advanced Science and Technology (RCAST), The University of Tokyo, 4-6-1 Komaba, Meguro-City, Tokyo, Japan, Nakamura@hal.rcast.u-tokyo.ac.jp
Takashi Nanya , Research Center of Advanced Science and Technology (RCAST), The University of Tokyo, 4-6-1 Komaba, Meguro-City, Tokyo, Japan, Nanya@hal.rcast.u-tokyo.ac.jp
pp. 1-6

Instruction Trace Compression for Rapid Instruction Cache Simulation (PDF)

Andhi Janapsatya , Computer Science and Engineering, The University of New South Wales, Sydney, NSW 2052, Australia, andhij@cse.unsw.edu.au
Aleksandar Ignjatovic , School of CSE and NICTA, University of New South Wales, Sydney, NSW 2052, Australia, ignjat@cse.unsw.edu.au
Sri Parameswaran , School of CSE and NICTA, University of New South Wales, Sydney, NSW 2052, Australia, sridevan@cse.unsw.edu.au
Joerg Henkel , Dept. of Computer Science, Karlsruhe University, Zirkel 2, D-76131 Karlsruhe, Germany, henkel@informatik.uni-karIsruhe.de
pp. 1-6

Efficient Code Density Through Look-up Table Compression (PDF)

Talal Bonny , University of Karlsruhe, Department of Computer Science, Karlsruhe, Germany, bonny@informatik.uni-karlsruhe.de
Joerg Henkel , University of Karlsruhe, Department of Computer Science, Karlsruhe, Germany, henkel@informatik.uni-karlsruhe.de
pp. 1-6

Microarchitectural Support for Program Code Integrity Monitoring in Application-specific Instruction Set Processors (PDF)

Yunsi Fei , Dept. of Electrical & Computer Engineering, University of Connecticut, Storrs, CT 06269, E-mail: yfei@engr.uconn.edu
Z. Jerry Shi , Dept. of Computer Science & Engineering, University of Connecticut, Storrs, CT 06269 E-mail: zshi@engr.uconn.edu
pp. 1-6

Soft-core Processor Customization using the Design of Experiments Paradigm (PDF)

David Sheldon , Department of Computer Science and Engineering, University of California, Riverside, dsheldon@cs.ucr.edu
Frank Vahid , Department of Computer Science and Engineering, University of California, Riverside; Center for Embedded Computer Systems at UC Irvine, vahid@cs.ucr.edu
Stefano Lonardi , Department of Computer Science and Engineering, University of California, Riverside, stelo@cs.ucr.edu
pp. 1-6

DATE 2007 "Best Industrial Designs" Session: From Algorithm to First 3.5G Call in Record Time - A Novel System Design Approach Based on Virtual Prototyping and its Consequences for Interdisciplinary System Design Teams (PDF)

M. Brandenburg , Infineon Technologies AG, Munich, Germany
A. Schollhorn , Infineon Technologies AG, Munich, Germany
S. Heinen , Infineon Technologies AG, Munich, Germany
J. Eckmuller , Infineon Technologies AG, Munich, Germany
T. Eckart , Infineon Technologies AG, Munich, Germany
pp. 1-3

Portable Multimedia SoC Design: a Global Challenge (Abstract)

Maurizio Paganini , Application Processor Division, STMicroelectronics, Grenoble, France, Tel : +33-4-7658-5616 Fax : +33-4-7658-5870, e-mail : maurizio.paganini@st.com
Georg Kimmich , Application Processor Division, STMicroelectronics, Grenoble, France
Stephane Ducrey , Application Processor Division, STMicroelectronics, Grenoble, France
Guilhem Caubit , Application Processor Division, STMicroelectronics, Grenoble, France
Vincent Coeffe , Application Processor Division, STMicroelectronics, Grenoble, France
pp. 1-4

Circuit-Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs (PDF)

Hamidreza Hashempour , Independent Researcher, Tehran, IRAN, hhashemp@ece.neu.edu
Fabrizio Lombardi , ECE Dept., Northeastern University, Boston, MA 02115, USA, lombardi@ece.neu.edu
pp. 1-6

Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling (PDF)

B. Jang , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, bjang@ece.neu.edu
Y-B. Kim , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, ybk@ece.neu.edu
F. Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, lombardi@ece.neu.edu
pp. 1-6

Design and DfT of a High-Speed Area-Efficient Embedded Asynchronous FIFO (PDF)

Paul Wielage , NXP Semiconductors, Research - Digital Design & Test, High Tech Campus 48, M/S-02, 5656AE Eindhoven, The Netherlands; NXP Semiconductors' IC Laboratory in Eindhoven, The Netherlands. paul.wielage@nxp.com
Erik Jan Marinissen , NXP Semiconductors, Research - Digital Design & Test, High Tech Campus 48, M/S-02, 5656AE Eindhoven, The Netherlands, erik.jan.marinissen@nxp.com
Michel Altheimer , NXP Semiconductors, Digital Library Technology, 505, Route des Lucioles, Sophia Antipolis, 06560 Valbonne, France; NXP Semiconductors in Crolles, France, e-mail:michel.altheimer@nxpcrolles.st.com
Clemens Wouters , NXP Semiconductors, Digital Library Technology, High Tech Campus 46, M/S-11, 5656AE Eindhoven, The Netherlands, elemens.wouters@nxp.com
pp. 1-6

Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO (PDF)

Tobias Dubois , Linköpings Universitet Dept. of Computer Science Embedded Systems Laboratory, SE-581 83 Linköping, Sweden, tobdu865@student.liu.se
Mohamed Azimane , NXP Semiconductors Research, High Tech Campus 48, M/S-02, 5656AE Eindhoven The Netherlands mohamed.azimane@nxp.com
Erik Larsson , Linköpings Universitet Dept. of Computer Science Embedded Systems Laboratory, SE-581 83 Linköping, Sweden, erila@ida.liu.se
Erik Jan Marinissen , NXP Semiconductors Research, High Tech Campus 48, M/S-02, 5656AE Eindhoven The Netherlands erik.jan.marinissen@nxp.com
Paul Wielage , NXP Semiconductors Research, High Tech Campus 48, M/S-02, 5656AE Eindhoven The Netherlands; NXP Semiconductors' IC Laboratory in Eindhoven, The Netherlands. paul.wielage@nxp.com
Clemens Wouters , NXP Semiconductors Digital Library Technology, High Tech Campus 46, M/S-11, 5656AE Eindhoven, The Netherlands, clemens.wouters@nxp.com
pp. 1-6

Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs (PDF)

Wenjing Rao , UC San Diego, CSE Department, wrao@cs.ucsd.edu
Alex Orailoglu , UC San Diego, CSE Department, alex@cs.ucsd.edu
Ramesh Karri , Polytechnic University, ECE Department, rkarri@poly.edu
pp. 1-5

A Multi-Core Debug Platform for NoC-Based Systems (PDF)

Shan Tang , Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong; Broadband Communication Network Lab, Beijing University of Posts & Telecommunications, Beijing, China, Email: tangs@cse.cuhk.edu.hk
Qiang Xu , Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong Email: qxu@cse.cuhk.edu.hk
pp. 1-6

Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support (Abstract)

L. Moss , Department of Computer Engineering, cole Polytechnique de Montral, moss@grm.polymtl.ca
M. de Nanclas , Department of Computer Engineering, cole Polytechnique de Montral, denancla@grm.polymtl.ca
L. Filion , Department of Computer Engineering, cole Polytechnique de Montral, filion@grm.polymtl.ca
S. Fontaine , Department of Computer Engineering, cole Polytechnique de Montral, fontaine@grm.polymtl.ca
G. Bois , Department of Computer Engineering, cole Polytechnique de Montral, bois@grm.polymtl.ca
M. Aboulhamid , Department of Computer Science and Operational Research, Universit de Montral, aboulham@iro.umontreal.ca
pp. 1-6

Incremental ABV for Functional Validation of TL-to-RTL Design Refinement (PDF)

Nicola Bombieri , Dipartimento di Informatica - Università di Verona, bombieri@sci.univr.it
Franco Fummi , Dipartimento di Informatica - Università di Verona, fummi@sci.univr.it
Graziano Pravadelli , Dipartimento di Informatica - Università di Verona, pravadelli@sci.univr.it
pp. 1-6

Efficient Testbench Code Synthesis for a Hardware Emulator System (Abstract)

I. Mavroidis , Microprocessor and Hardware Lab (MHL), Technical University of Crete (TUC), Kounoupidiana, Crete, GG73100, Greece, jacob@mhl.tuc.gr
I. Papaefstathiou , Microprocessor and Hardware Lab (MHL), Technical University of Crete (TUC), Kounoupidiana, Crete, GG73100, Greece, ygp@mhl.tuc.gr
pp. 1-6

Implementation of a Transaction Level Assertion Framework in SystemC (PDF)

Wolfgang Ecker , Infineon Technologies AG, IFAG COM BTS MT SD, 81726 Munich, Germany, Wolfgang.Ecker@infineon.com
Volkan Esen , Infineon Technologies AG, TU Darmstadt - MES, Volkan.Esen@infineon.com
Thomas Steininger , Infineon Technologies AG, TU Darmstadt - MES, Thomas.Steininger@infineon.com
Michael Velten , Infineon Technologies AG, TU Darmstadt - MES, Michael.Velten@infineon.com
Michael Hull , Infineon Technologies AG, University of Southampton, mh102@ecs.soton.ac.uk
pp. 1-6

Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions (PDF)

Shireesh Verma , Department of Computer Science, University of California Irvine, Irvine, CA 92697, USA, shireesh@ics.uci.edu
Ian G. Harris , Department of Computer Science, University of California Irvine, Irvine, CA 92697, USA, harris@ics.uci.edu
Kiran Ramineni , Department of Computer Science, University of California Irvine, Irvine, CA 92697, USA, kiran@ics.uci.edu
pp. 1-6

Compositional Specification of Behavioral Semantics (Abstract)

Kai Chen , Motorola Labs, Schaumburg, IL, 60646, USA, Kai.Chen@motorola.com
Janos Sztipanovits , ISIS, Vanderbilt University, Nashville, TN, 37203, USA, Sztipaj@isis.vanderbilt.edu
Sandeep Neema , ISIS, Vanderbilt University, Nashville, TN, 37203, USA, Sandeep@isis.vanderbilt.edu
pp. 1-6

Performance Analysis of Multimedia Applications using Correlated Streams (PDF)

Kai Huang , ETH Zürich, Switzerland, huang@tik.ee.ethz.ch
Lothar Thiele , ETH Zürich, Switzerland, thiele@tik.ee.ethz.ch
Todor Stefanov , University Leiden, Netherlands, stefanov@liacs.nl
Ed Deprettere , University Leiden, Netherlands, edd@liacs.nl
pp. 1-6

Simulation Platform for UHF RFID (PDF)

Vojtech Derbek , Institute of Technical Informatics, Graz University of Technology, Austria, derbek@iti.tugraz.at
Christian Steger , Institute of Technical Informatics, Graz University of Technology, Austria, steger@iti.tugraz.at
Reinhold Weiss , Institute of Technical Informatics, Graz University of Technology, Austria, rweiss@iti.tugraz.at
Daniel Wischounig , CISC Semiconductor Design+Consulting GmBH, Austria, d.wischounig@cisc.at
Josef Preishuber-Pfluegl , CISC Semiconductor Design+Consulting GmBH, Austria, j.preishuber-pfluegl@cisc.at
Markus Pistauer , CISC Semiconductor Design+Consulting GmBH, Austria, m.pistauer@cisc.at
pp. 1-6

Tool-support for the analysis of hybrid systems and models (Abstract)

Andreas Bauer , Institut fr Informatik, Technische Universitt Mnchen, baueran@informatik.tu-muenchen.de
Markus Pister , Institut fr Informatik, Technische Universitt Mnchen, pister@informatik.tu-muenchen.de
Michael Tautschnig , Institut fr Informatik, Technische Universitt Mnchen, tautschn@informatik.tu-muenchen.de
pp. 1-6

Automatic Model Generation for Black Box Real-Time Systems (Abstract)

Thomas Huining Feng , EECS, UC Berkeley, tfeng@eecs.berkeley.edu
Lynn Wang , EECS, UC Berkeley, ting0918@eecs.berkeley.edu
Wei Zheng , EECS, UC Berkeley, zhengwei@eecs.berkeley.edu
Sri Kanajan , General Motors, sri.kanajan@gm.com
Sanjit A. Seshia , EECS, UC Berkeley, sseshia@eecs.berkeley.edu
pp. 1-6

Routing Table Minimization for Irregular Mesh NoCs (Abstract)

Evgeny Bolotin , Electrical Engineering Department, Technion-Israel Institute of Technology,Haifa 32000, Israel
Israel Cidon , Electrical Engineering Department, Technion-Israel Institute of Technology,Haifa 32000, Israel
Ran Ginosar , Electrical Engineering Department, Technion-Israel Institute of Technology,Haifa 32000, Israel
Avinoam Kolodny , Electrical Engineering Department, Technion-Israel Institute of Technology,Haifa 32000, Israel
pp. 1-6

Congestion-Controlled Best-Effort Communication for Networks-on-Chip (PDF)

J.W. van den Brand , NXP Research, jan.willem.v.d.brand@nxp.com
C. Ciordas , Eindhoven University of Technology
K. Goossens , NXP Research
T. Basten , Eindhoven University of Technology
pp. 1-6

Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip (PDF)

Andreas Hansson , Eindhoven University of Technology, Eindhoven, The Netherlands, m.a.hansson@tue.nl
Martijn Coenen , Research, NXP Semiconductors, Eindhoven, The Netherlands, martijn.coenen@nxp.com
Kees Goossens , Research, NXP Semiconductors, Eindhoven, The Netherlands, kees.goossens@nxp.com
pp. 1-6

Testing in the Year 2020 (PDF)

Rajesh Galivanche , Intel Corp., Santa Clara, USA, E-mail: rajesh.galivanche@intel.com
Rohit Kapur , Synopsys, Mountain View, USA, E-mail: rohit.kapur@synopsys.com
Antonio Rubio , Technical University of Catalunya, Barcelona, Spain, E-mail: antonio.rubio@upc.edu
pp. 1-6

Transaction Level Modelling of SCA Compliant Software Defined Radio Waveforms and Platforms PIM/PSM (PDF)

Gregory Gailliard , Thales Communications S.A., Colombes, France, Grégory.Gailliard@fr.thalesgroup.com
Eric Nicollet , Thales Communications S.A., Colombes, France, Eric.Nicollet@fr.thalesgroup.com
Michel Sarlotte , Thales Communications S.A., Colombes, France, Michel.Sarlotte@fr.thalesgroup.com
Francois Verdier , ETIS Lab ¿ UMR CNRS 8051, Cergy-Pontoise, France, verdier@ensea.fr
pp. 1-6

Event Driven Data Processing Architecture (Abstract)

Ingemar Soderquist , Saab AB, Saab Avitronics, SE-581 88 Linkping, Sweden, Email: ingemar.soderquist@saabgroup.com; Electronic Devices, Linkping University, SE-581 83 Linkping, Sweden. Email: ingemar.soderquist@isy.liu.se
pp. 1-5

Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments (PDF)

B. Fiethe , IDA TU Braunschweig, Hans-Sommer-Str. 66, D-38106 Braunschweig, Germany
H. Michalik , IDA TU Braunschweig, Hans-Sommer-Str. 66, D-38106 Braunschweig, Germany
C. Dierker , IDA TU Braunschweig, Hans-Sommer-Str. 66, D-38106 Braunschweig, Germany
B. Osterloh , IDA TU Braunschweig, Hans-Sommer-Str. 66, D-38106 Braunschweig, Germany
G. Zhou , IDA TU Braunschweig, Hans-Sommer-Str. 66, D-38106 Braunschweig, Germany
pp. 1-6

Enabling certification for dynamic partial reconfiguration using a minimal flow (Abstract)

B. Rousseau , Universit catholique de Louvain. Laboratoire de micro lectronique. Place du Levant, 3. 1348 Louvain-la-Neuve, rousseau@dice.ucl.ac.be
Ph. Manet , Universit catholique de Louvain. Laboratoire de micro lectronique. Place du Levant, 3. 1348 Louvain-la-Neuve, manet@dice.ucl.ac.be
D. Galerin , Universit catholique de Louvain. Laboratoire de micro lectronique. Place du Levant, 3. 1348 Louvain-la-Neuve, denis.galerin@student.uclouvain.be
D. Merkenbreack , Universit catholique de Louvain. Laboratoire de micro lectronique. Place du Levant, 3. 1348 Louvain-la-Neuve, diego.merkenbreack@student.uclouvain.be
J.-D. Legat , Universit catholique de Louvain. Laboratoire de micro lectronique. Place du Levant, 3. 1348 Louvain-la-Neuve, legat@dice.ucl.ac.be
F. Dedeken , Thales Communications Belgium. Rue des Frres Taymans. 1480 Tubize, fabienne.dedeken@be.thalesgroup.com
Y. Gabriel , Thales Communications Belgium. Rue des Frres Taymans. 1480 Tubize, yves.gabriel@be.thalesgroup.com
pp. 1-6

Identification of Process/Design Issues during 0.18μm Technology Qualification for Space Application (PDF)

Julie Ferrigno , CNES, Electronic Analysis Dept., 18, Avenue Edouard Belin, 31401 Toulouse Cedex 9, France, Phone: +(33) 5 61 28 21 49 Fax: +(33) 5 61 27 47 32, Email: julie.ferrigno@boursier.cnes.fr
Philippe Perdu , CNES, Electronic Analysis Dept., 18, Avenue Edouard Belin, 31401 Toulouse Cedex 9, France
Kevin Sanchez , CNES, Electronic Analysis Dept., 18, Avenue Edouard Belin, 31401 Toulouse Cedex 9, France
Dean Lewis , IXL, Université de Bordeaux 1, 33405 Talence, France
pp. 1-5

RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics (PDF)

Yves Gabriel , THALES COMMUNICATIONS, Rue des Frères Taymans 28, B-1480 Tubize, Belgium, yves.gabriel@be.thalesgroup.com
Philippe Manet , Université catholique de Louvain, Place du Levant 3, B-1348 Louvain-la- Neuve, Belgium, manet@dice.ucl.ac.be
Leonardo Tosi , CESVIT MICROELETTRONICA, Via A. Cecchi 30, 59100 Prato, Italy, tosi@cesvitmicroelettronica.it
Marco di Ciano , Tecnopolis CSATA, Str P. Casamassima km 3, 70010 Valenzano Bari, Italy, m.diciano@tno.it
Olivier Mulertt , MBDA, Rue Grange Dame Rose 20 - 22, 78140 Velizy-Villacoublay, France, olivier.mulertt@mbda-systems.com
Daniel Maufroid , THALES COMMUNICATIONS, Boulevard de Valmy 160, 92704 Colombes, France, daniel.maufroid@fr.thalesgroup.com
Jean-Didier Legat , Université catholique de Louvain, Place du Levant 3, B-1348 Louvain-la- Neuve, Belgium, legat@dice.ucl.ac.be
Denis Aulagnier , THALES AIRBORNE SYSTEMS, Av. de la 1ere DFL 10, 29283 Brest, France, denis.aulagnier@fr.thalesgroup.com
Christian Gamrat , CEA LIST, CEN Saclay, 91191 Gif Sur Yvette, France, christian.gamrat@cea.fr
Raffaele Liberati , ELETTRONICA, Via Tiburtina Valeria km 13,700, 00131 Rome, Italy, raffaele.liberati@elt.it
Vincenzo la Barba , THALES ITALIA, Via E. Mattei 20, 66013 Chieti Scalo, Italy, vincenzo.labarba@it.thalesgroup.com
pp. 1-6

WAVSTAN: Waveform based Variational Static Timing Analysis (PDF)

Saurabh K Tiwary , Cadence Berkeley Labs, Berkeley, CA, USA, stiwary@cadence.com
Joel R Phillips , Cadence Berkeley Labs, Berkeley, CA, USA, jrp@cadence.com
pp. 1-6

Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times (Abstract)

Shweta Srivastava , Department of Electrical and Computer Engineering, University of Minnesota, Email: shwetas@umn.edu
Jaijeet Roychowdhury , Department of Electrical and Computer Engineering, University of Minnesota, Email: jr@umn.edu
pp. 1-6

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops (PDF)

B. Lasbouygues , STMicroelectronics, Design Department 850, rue Monnet 38926, Crolles, France
R. Wilson , STMicroelectronics, Design Department 850, rue J. Monnet, 38926, Crolles, France
N. Azemard , University of Montpellier, II, 161 rue Ada, 34392, Montpellier, France
P. Maurine , University of Montpellier, II, 161 rue Ada, 34392, Montpellier, France
pp. 1-6

Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models (PDF)

D. Tadesse , Brown University, Division of Engineering, Providence, RI 02912
D. Sheffield , Brown University, Division of Engineering, Providence, RI 02912
E. Lenge , Rensselaer Polytechnic Institute, Troy, NY 12180
R.I. Bahar , Brown University, Division of Engineering, Providence, RI 02912
J. Grodstein , Intel Corporation, Hudson, MA 01749
pp. 1-6

CARAT: a Toolkit for Design and Performance Analysis of Component-Based Embedded Systems (PDF)

Egor Bondarev , Eindhoven University of Technology, 5600 MB, Eindhoven, The Netherlands, e.bondarev@tue.nl
Michel Chaudron , Eindhoven University of Technology, 5600 MB, Eindhoven, The Netherlands
Peter H. N. de With , LogicaCMG / Eindhoven Univ. of Tech., 5605 JB, Eindhoven, The Netherlands, p.h.n.de.with@tue.nl
pp. 1-6

Modeling and Simulation Alternatives for the Design of Networked Embedded Systems (PDF)

E. Alessio , Telecom Italia Lab, Via G. Reiss Romoli 274, I-10148, Torino, Italy, elisal.alessio@telecomitalia.it
F. Fummi , Dipartimento di Informatica, Università di Verona, strada le Grazie 15, I-37134, Verona, Italy, fummi@sci.univr.it
D. Quaglia , Dipartimento di Informatica, Università di Verona, strada le Grazie 15, I-37134, Verona, Italy, quaglia@sci.univr.it
M. Turolla , Telecom Italia Lab, Via G. Reiss Romoli 274, I-10148, Torino, Italy, maura.turolla@telecomitalia.it
pp. 1-6

Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns (PDF)

Stylianos Mamagkakis , IMEC vzw., 3001 Heverlee, Belgium, mamagka@imec.be
Dimitrios Soudris , VLSI Center-Democritus Uni., 67100 Xanthi, Greece, dsoudris@ee.duth.gr
Francky Catthoor , IMEC vzw., 3001 Heverlee, Belgium; ESAT/K.U.Leuven, catthoor@imec.be
pp. 1-6

Leightweight Middleware for Seamless HW-SW Interoperability, with Application to Wireless Sensor Networks (PDF)

F.J. Villanueva , Department of Information Technologies and Systems, School of Computer Science, 13071, Ciudad Real, Spain. felixjesus.villanueva@uclm.es
D. Villa , Department of Information Technologies and Systems, School of Computer Science, 13071, Ciudad Real, Spain
F. Moya , Department of Information Technologies and Systems, School of Computer Science, 13071, Ciudad Real, Spain
J. Barba , Department of Information Technologies and Systems, School of Computer Science, 13071, Ciudad Real, Spain
F. Rincon , Department of Information Technologies and Systems, School of Computer Science, 13071, Ciudad Real, Spain
J. C. Lope , Department of Information Technologies and Systems, School of Computer Science, 13071, Ciudad Real, Spain
pp. 1-6

A Middleware-centric Design Flow for Networked Embedded Systems (PDF)

F. Fummi , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy, fummi@sci.univr.it
G. Perbellini , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy, perbellini@sci.univr.it
R. Pietrangeli , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy, pietrangeli@sci.univr.it
D. Quaglia , University of Verona - Department of Computer Science - Strada le Grazie, 37134, Verona, Italy, quaglia@sci.univr.it
pp. 1-6

Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources (PDF)

Ani Nahapetian , Computer Science Department, University of California, Los Angeles (UCLA), Los Angeles, California, USA
Paolo Lombardo , Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), Università Bologna, Bologna, Italy
Andrea Acquaviva , Information Science and Technology Institute (ISTI), Università di Urbino, Urbino, Italy
Luca Benini , Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), Università Bologna, Bologna, Italy
Majid Sarrafzadeh , Information Science and Technology Institute (ISTI), Università di Urbino, Urbino, Italy
pp. 1-6

Dynamic Power Management under Uncertain Information (PDF)

Hwisung Jung , Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089, hwijung@usc.edu
Massoud Pedram , Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089, pedram@usc.edu
pp. 1-6

Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors (PDF)

Praveen Raghavan , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium; KULeuven, Belgium, ragha@imec.be
Andy Lambrechts , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium; KULeuven, Belgium, lambreca@imec.be
Murali Jayapala , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium, jayapala@imec.be
Francky Catthoor , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium; KULeuven, Belgium
Diederik Verkest , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium; KULeuven, Belgium; VUB, Belgium
Henk Corporaal , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium; TU Eindhoven, Netherlands
pp. 1-6

Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory (PDF)

Mihir Choudhury , Rice University, mihir@rice.edu
Kyle Ringgenberg , Rice University, kringg@rice.edu
Scott Rixner , Rice University, rixner@rice.edu
Kartik Mohanram , Rice University, kmram@rice.edu
pp. 1-6

PowerQuest: Trace Driven Data Mining for Power Optimization (PDF)

Pietro Babighian , Intel Corp., Leixlip ¿ Ireland
Gila Kamhi , Intel Corp., Haifa ¿ Israel
Moshe Vardi , Rice University, Houston - Texas
pp. 1-6

System Level Assessment of an Optical NoC in an MPSoC Platform (PDF)

M. Briere , ?cole Polytechnique de Montréal, Montréal ¿ Canada
B. Girodias , ?cole Polytechnique de Montréal, Montréal ¿ Canada
Y. Bouchebaba , ?cole Polytechnique de Montréal, Montréal ¿ Canada
G. Nicolescu , ?cole Polytechnique de Montréal, Montréal ¿ Canada
F. Mieyeville , ?cole Centrale de Lyon, ?cully ¿ France
F. Gaffiot , ?cole Centrale de Lyon, ?cully ¿ France
I. O'Connor , ?cole Centrale de Lyon, ?cully ¿ France
pp. 1-6

Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture (PDF)

A. Sheibanyrad , The University of Pierre et Marie Curie, Paris, France
I. Miro Panades , STMicroelectronics, Grenoble, France
A. Greiner , The University of Pierre et Marie Curie, Paris, France
pp. 1-6

Analytical Router Modeling for Networks-on-Chip Performance Analysis (PDF)

Umit Y. Ogras , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA, uogras@ece.cmu.edu
Radu Marculescu , Department of Electrical and Computer Engineering, Carnegie Mellon University, USA, radum@ece.cmu.edu
pp. 1-6

Hard- and Software Modularity of the NOVA MPSoC Platform (PDF)

Christian Sauer , Infineon Technologies, Communications Solutions, Munich, Germany, Christian.Sauer@infineon.com
Matthias Gries , Infineon Technologies, Communications Solutions, Munich, Germany, Matthias.Gries@infineon.com
Sebastian Dirk , Infineon Technologies, Communications Solutions, Munich, Germany
pp. 1-6

Tutorial: The Methodological and Technological Dimensions of Technology Transfer for Embedded Systems in Aeronautics and Space (PDF)

Thierry Pardessus , VP R&T Systems and Integration Tests, Airbus SAS, France
Heinrich Daembkes , VP Systems and Software Engineering, EADS Defense Electronics, Germany
Richard Arning , head of Sensor Systems & Integration, EADS Corporate Research Center, Germany
pp. 1-2

Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints (PDF)

Johann Grossschadl , Graz University of Technology, Institute for Applied Information Processing and Communications, Inffeldgasse 16a, A-8010 Graz, Austria, jgrosz@iaik.tugraz.at
Stefan Tillich , Graz University of Technology, Institute for Applied Information Processing and Communications, Inffeldgasse 16a, A-8010 Graz, Austria, stillich@iaik.tugraz.at
Christian Rechberger , Graz University of Technology, Institute for Applied Information Processing and Communications, Inffeldgasse 16a, A-8010 Graz, Austria, chrech@iaik.tugraz.at
Michael Hofmann , Graz University of Technology, Institute for Applied Information Processing and Communications, Inffeldgasse 16a, A-8010 Graz, Austria, mhofmann@sbox.tugraz.at
Marcel Medwed , Graz University of Technology, Institute for Applied Information Processing and Communications, Inffeldgasse 16a, A-8010 Graz, Austria, koermy@sbox.tugraz.at
pp. 1-6

An Area Optimized Reconfigurable Encryptor for AES-Rijndael (Abstract)

Monjur Alam , Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, monjur@cse.iitkgp.ernet.in
Sonai Ray , Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, sonai@cse.iitkgp.ernet.in
Debdeep Mukhopadhayay , Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur; Indian Institute of Technology, Madras, debdeep@cse.iitm.ernet.in
Santosh Ghosh , Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, santosh@cse.iitkgp.ernet.in
Dipanwita RoyChowdhury , Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, drc@cse.iitkgp.ernet.in
Indranil Sengupta , Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, isg@cse.iitkgp.ernet.in
pp. 1-6

Performance Aware Secure Code Partitioning (PDF)

S. H. K. Narayanan , The Pennsylvania State University, snarayan@cse.psu.edu
M. Kandemir , The Pennsylvania State University, kandemir@cse.psu.edu
R. Brooks , Clemson University, rrb@acm.org
pp. 1-6

Energy and Execution Time Analysis of a Software-based Trusted Platform Module (PDF)

Najwa Aaraj , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, naaraj@princeton.edu
Anand Raghunathan , NEC Laboratories America, Princeton, NJ 08540, anand@nec-labs.com
Srivaths Ravi , Texas Instruments R&D Center, Bangalore, India, srivaths.ravi@ti.com
Niraj K. Jha , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, jha@princeton.edu
pp. 1-6

Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches (PDF)

Luong D. Hung , Graduate School of Information Science and Technology, The University of Tokyo, Hongo 7-3-1, Bunkyo, Tokyo 113-8656, Japan, hung@mtl.t.u-tokyo.ac.jp
Hidetsugu Irie , Graduate School of Information Science and Technology, The University of Tokyo, Hongo 7-3-1, Bunkyo, Tokyo 113-8656, Japan, ern@mtl.t.u-tokyo.ac.jp
Masahiro Goshima , Graduate School of Information Science and Technology, The University of Tokyo, Hongo 7-3-1, Bunkyo, Tokyo 113-8656, Japan, goshima@mtl.t.u-tokyo.ac.jp
Shuichi Sakai , Graduate School of Information Science and Technology, The University of Tokyo, Hongo 7-3-1, Bunkyo, Tokyo 113-8656, Japan, sakai@mtl.t.u-tokyo.ac.jp
pp. 1-6

Transient Fault Prediction Based on Anomalies in Processor Events (PDF)

Satish Narayanasamy , University of California, San Diego
Ayse K. Coskun , University of California, San Diego
Brad Calder , University of California, San Diego; Microsoft
pp. 1-6

Low-Cost Protection for SER Upsets and Silicon Defects (PDF)

Mojtaba Mehrara , Advanced Computer Architecture Lab University of Michigan, Ann Arbor, MI 48109, mehara@umich.edu
Mona Attariyan , Advanced Computer Architecture Lab University of Michigan, Ann Arbor, MI 48109, monattar@umich.edu
Smitha Shyam , Advanced Computer Architecture Lab University of Michigan, Ann Arbor, MI 48109, smithash@umich.edu
Kypros Constantinides , Advanced Computer Architecture Lab University of Michigan, Ann Arbor, MI 48109, kypros@umich.edu
Valeria Bertacco , Advanced Computer Architecture Lab University of Michigan, Ann Arbor, MI 48109, valeria@umich.edu
Todd Austin , Advanced Computer Architecture Lab University of Michigan, Ann Arbor, MI 48109, austin@umich.edu
pp. 1-6

Working with Process Variation Aware Caches (PDF)

Madhu Mutyam , International Institute of Information Technology, Hyderabad, Gachibowli, Hyderabad -500032, India, mutyam@iiit.ac.in
Vijaykrishnan Narayanan , Pennsylvania State University, University Park, PA 16802, USA, vijay@cse.psu.edu
pp. 1-6

An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processor (PDF)

E. Sanchez , Politecnico di Torino Dipartimento di Automatica e Informatica, Torino, Italy, edgar.sanchez@polito.it
M. Schillaci , Politecnico di Torino Dipartimento di Automatica e Informatica, Torino, Italy, massimiliano.schillaci@polito.it
G. Squillero , Politecnico di Torino Dipartimento di Automatica e Informatica, Torino, Italy, giovanni.squillero@polito.it
M. Sonza Reorda , Politecnico di Torino Dipartimento di Automatica e Informatica, Torino, Italy, matteo.sonzareorda@polito.it
pp. 1-6

Functional and Timing Validation of Partially Bypassed Processor Pipelines (PDF)

Qiang Zhu , Fujitsu Laboratories LTD., Japan, 1-1, Kamikodanaka 4-Chome, Nakahara-ku, Kawasaki 211-8588 shiyu@labs.fujitsu.com
Aviral Shrivastava , Department of Computer Science and Engineering, ASU, Tempe, AZ 85281 Aviral.Shrivastava@asu.edu
Nikil Dutt , School of Information and Computer Science, UC Irvine, CA 92617 dutt@ics.uci.edu
pp. 1-6

A Compositional Approach to the Combination of Combinational and Sequential Equivalence Checking of Circuits Without Known Reset States (PDF)

In-Ho Moon , Advanced Technology Group, Synopsys Inc.
Per Bjesse , Advanced Technology Group, Synopsys Inc.
Carl Pixley , Advanced Technology Group, Synopsys Inc.
pp. 1-6

Estimating Functional Coverage in Bounded Model Checking (PDF)

Daniel Grosse , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany, grosse@informatik.uni-bremen.de
Ulrich Kuhne , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany, ulrichk@informatik.uni-bremen.de
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany, drechsle@informatik.uni-bremen.de
pp. 1-6

Abstraction and Refinement Techniques in Automated Design Debugging (PDF)

Sean Safarpour , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada, sean@eecg.toronto.edu
Andreas Veneris , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada, veneris@eecg.toronto.edu
pp. 1-6

Automatic Hardware Synthesis from Specifications: A Case Study (PDF)

Roderick Bloem , Graz University of Technology
Stefan Galler , Graz University of Technology
Barbara Jobstmann , Graz University of Technology
Nir Piterman , EPFL Lausanne
Amir Pnueli , Weizmann Institute
Martin Weiglhofer , Graz University of Technology
pp. 1-6

pFFT in FastMaxwell: A Fast Impedance Extraction Solver for 3D Conductor Structures over Substrate (PDF)

Tarek Moselhy , Research Laboratory in Electronics, Massachusetts Institute of Technology, 77 Massachusetts Ave, Cambridge, MA, 02139, Email: tmoselhy@mit.edu
Xin Hu , Ropes and Gray LLP Boston, MA, Email: xinhu@alum.mit.edu
Luca Daniel , Research Laboratory in Electronics, Massachusetts Institute of Technology, 77 Massachusetts Ave, Cambridge, MA, 02139, Email: luca@mit.edu
pp. 1-6

Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction (PDF)

Xin Hu , Ropes and Gray LLP Boston, MA, Email: xinhu@alum.mit.edu
Tarek Moselhy , Research Laboratory in Electronics, Massachusetts Institute of Technology, 77 Massachusetts Ave, Cambridge, MA, 02139
Jacob White , Research Laboratory in Electronics, Massachusetts Institute of Technology, 77 Massachusetts Ave, Cambridge, MA, 02139
Luca Daniel , Research Laboratory in Electronics, Massachusetts Institute of Technology, 77 Massachusetts Ave, Cambridge, MA, 02139
pp. 1-6

Thermally Robust Clocking Schemes for 3D Integrated Circuits (PDF)

Mosin Mondal , Rice University, Houston, TX. mosin@rice.edu
Andrew J. Ricketts , Pennsylvania State University, University Park, PA. ricketts@cse.psu.edu
Sami Kirolos , Rice University, Houston, TX. kirolos@rice.edu
Tamer Ragheb , Rice University, Houston, TX. ragheb@rice.edu
Greg Link , York College of Pennsylvania, York, PA. glink@ycp.edu
N. Vijaykrishnan , Pennsylvania State University, University Park, PA. vijay@cse.psu.edu
Yehia Massoud , Rice University, Houston, TX. massoud@rice.edu
pp. 1-6

Double-Via-Driven Standard Cell Library Design (PDF)

Tsai-Ying Lin , Computer Science and Engineering Department, Yuan Ze University, Chung-Li, Taiwan, csrlin@cs.yzu.edu.tw
Tsung-Han Lin , Computer Science and Engineering Department, Yuan Ze University, Chung-Li, Taiwan
Hui-Hsiang Tung , Computer Science and Engineering Department, Yuan Ze University, Chung-Li, Taiwan
Rung-Bin Lin , Computer Science and Engineering Department, Yuan Ze University, Chung-Li, Taiwan
pp. 1-6

Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining (PDF)

Jingye Xu , ECE, University of Illinois at Chicago, Chicago, IL60607, jxu6@uic.edu
Abinash Roy , ECE, University of Illinois at Chicago, Chicago, IL60607, aroy5@uic.edu
Masud H. Chowdhury , ECE, University of Illinois at Chicago, Chicago, IL60607, masud@ece.uic.edu
pp. 1-6

A Future of Customizable Processors: Are We There Yet? (PDF)

Laura Pozzi , Faculty of Informatics, University of Lugano, CH-6900 Lugano, Switzerland
Pierre G. Paulin , Advanced System Technology, STMicroelectronics Inc., Canada
pp. 1-2

Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement (PDF)

Peter Spindler , Institute for Electronic Design Automation, Technische Universitaet Muenchen, Munich, Germany
Frank M. Johannes , Institute for Electronic Design Automation, Technische Universitaet Muenchen, Munich, Germany
pp. 1-6

Yield-aware Placement Optimization (PDF)

P. Azzoni , PDF Solutions (IT)
M. Bertoletti , University of Verona (IT)
N. Dragone , University of Verona (IT)
F. Fummi , PDF Solutions (IT)
C. Guardiani , University of Verona (IT)
W. Vendraminetto , PDF Solutions (IT)
pp. 1-6

Microarchitecture Floorplanning for Sub-threshold Leakage Reduction (PDF)

Hushrav D. Mogal , University of Minnesota, Twin Cities, Minneapolis, MN 55414, mhush@umn.edu
Kia Bazargan , University of Minnesota, Twin Cities, Minneapolis, MN 55414, kia@umn.edu
pp. 1-6

Compact Hardware Design of Whirlpool Hashing Core (PDF)

Timo Alho , Nokia Technology Platforms, Tampere, Finland, timo.a.alho@nokia.com
Panu Hamalainen , Nokia Technology Platforms, Tampere, Finland, panu.hamalainen@nokia.com
Marko Hannikainen , Tampere University of Technology, Institute of Digital and Computer Systems, Tampere, Finland, marko.hannikainen@tut.fi
Timo D. Hamalainen , Tampere University of Technology, Institute of Digital and Computer Systems, Tampere, Finland, timo.d.hamalainen@tut.fi
pp. 1-6

An Efficient Polynomial Multiplier in GF(2m) and its Application to ECC Designs (Abstract)

Steffen Peter , IHP GmbH, Frankfurt(Oder), Germany, peter@ihp-microelectronics. com
Peter LangendOorfer , IHP GmbH, Frankfurt(Oder), Germany, langendoerfer@ihp-microelectronics. com
pp. 1-6

Flexible Hardware Reduction for Elliptic Curve Cryptography in GF(2m) (PDF)

Steffen Peter , IHP GmbH, Frankfurt(Oder), Germany, peter@ihp-microelectronics. com
Peter Langendorfer , IHP GmbH, Frankfurt(Oder), Germany, langendoerfer@ihp-microelectronics. com
Krzysztof Piotrowski , IHP GmbH, Frankfurt(Oder), Germany, piotrowski@ihp-microelectronics. com
pp. 1-6

Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware (PDF)

Kuan Jen Lin , Department of Electronic Engineering, Fu Jen Catholic University, Taiwan, kjlin@mail.fju.edu.tw
Shan Chien Fang , Department of Electronic Engineering, Fu Jen Catholic University, Taiwan
Shih Hsien Yang , Department of Electronic Engineering, Fu Jen Catholic University, Taiwan
Cheng Chia Lo , Department of Electronic Engineering, Fu Jen Catholic University, Taiwan
pp. 1-6

Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical Delay Testing of Nanometer ICs (PDF)

J.L. Rossello , Electronic Technology Group, Balearic Islands Univ., Cra. de Valldemossa, Km 7.5, E-07122, Palma de Mallorca, Spain
C. de Benito , Electronic Technology Group, Balearic Islands Univ., Cra. de Valldemossa, Km 7.5, E-07122, Palma de Mallorca, Spain
S.A. Bota , Electronic Technology Group, Balearic Islands Univ., Cra. de Valldemossa, Km 7.5, E-07122, Palma de Mallorca, Spain
J. Segura , Electronic Technology Group, Balearic Islands Univ., Cra. de Valldemossa, Km 7.5, E-07122, Palma de Mallorca, Spain
pp. 1-6

Sensitivity Analysis for Fault-analysis and Tolerance in RF Front-end Circuitry (Abstract)

Tejasvi Das , Dept. of Electrical Engineering, Rochester Institute of Technology, Rochester NY 14623, Email: tad4807@rit.edu
P.R. Mukund , Dept. of Electrical Engineering, Rochester Institute of Technology, Rochester NY 14623
pp. 1-6

A Two-Tone Test Method for Continuous-Time Adaptive Equalizers (PDF)

Dongwoo Hong , University of California, Santa Barbara, CA, USA
Shadi Saberi , Carnegie Mellon University, Pittsburgh, PA, USA
Kwang-Ting Cheng , University of California, Santa Barbara, CA, USA
C. Patrick Yue , University of California, Santa Barbara, CA, USA
pp. 1-6

Worst-Case Design and Margin for Embedded SRAM (PDF)

Robert Aitken , ARM, Sunnyvale CA, USA, rob.aitken@arm.com
Sachin Idgunji , ARM, Sunnyvale CA, USA, sachin.idgunji@arm.com
pp. 1-6

Pulse propagation for the detection of small delay defects (PDF)

M. Favalli , DI - Univ. of Ferrara
C. Metra , DEIS - Univ. of Bologna
pp. 1-6

BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits (PDF)

Amir Zjajo , Philips Research Laboratories, HighTech Campus 5, 5656 AE Eindhoven, The Netherlands, e-mail: amir.zjajo@philips.com
Manuel J. Barragan Asian , Instituto de Microelectronica de Seville, Centro Nacional de Microelectroinca, University of Seville, 41012 Seville, Spain
Jose Pineda de Gyvez , Philips Research Laboratories, HighTech Campus 5, 5656 AE Eindhoven, The Netherlands; Eindhoven University of Technology, Den Dolech 2, 5612 AZ Eindhoven, The Netherlands
pp. 1-6

A New Hybrid Solution to Boost SAT Solver Performance (PDF)

Lei Fang , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, leifang@vt.edu
Michael S. Hsiao , Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, mhsiao@vt.edu
pp. 1-6

QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure (PDF)

Chi-An Wu , Department of Electrical Engineering, National Taiwan University, Taiwan
Ting-Hao Lin , Department of Electrical Engineering, National Taiwan University, Taiwan
Chih-Chun Lee , Department of Electrical Engineering, National Taiwan University, Taiwan
Chung-Yang Huang , Department of Electrical Engineering, National Taiwan University, Taiwan
pp. 1-6

Boosting the Role of Inductive Invariants in Model Checking (PDF)

Gianpiero Cabodi , Politecnico di Torino, Dip. di Automatica e Informatica, Turin, ITALY
Sergio Nocco , Politecnico di Torino, Dip. di Automatica e Informatica, Turin, ITALY
Stefano Quer , Politecnico di Torino, Dip. di Automatica e Informatica, Turin, ITALY
pp. 1-6

Polynomial-Time Subgraph Enumeration for Automated Instruction Set Extension (PDF)

Paolo Bonzini , Faculty of Informatics, University of Lugano (USI), Switzerland, Email: paolo.bonzini@lu.unisi.ch
Laura Pozzi , Faculty of Informatics, University of Lugano (USI), Switzerland, Email: laura.pozzi@unisi.ch
pp. 1-6

Interrupt and Low-level Programming Support for Expanding the Application Domain of Statically-Scheduled Horizontal-Microcoded Architectures in Embedded Systems (PDF)

Mehrdad Reshadi , Center for Embedded Computer Systems (CECS), University of California Irvine, CA 92697, USA. reshadi@cecs.uci.edu
Daniel Gajski , Center for Embedded Computer Systems (CECS), University of California Irvine, CA 92697, USA. gajski@cecs.uci.edu
pp. 1-6

DRIM : A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for Embedded Systems (PDF)

Zhiguo Ge , Department of Computer Science, National University of Singapore, gezhiguo@comp.nus.edu.sg
Weng-Fai Wong , Department of Computer Science, National University of Singapore, wongwf@comp.nus.edu.sg
Hock-Beng Lim , ST Engineering, limhb@steng.com.sg
pp. 1-6

SoftSIMD - Exploiting Subword Parallelism Using Source Code Transformations (PDF)

Stefan Kraemer , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany, kraemer@iss.rwth-aachen.de
Rainer Leupers , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany, leupers@iss.rwth-aachen.de
Gerd Ascheid , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany
Heinrich Meyr , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany
pp. 1-6

A Process Splitting Transformation For Kahn Process Networks (PDF)

Sjoerd Meijer , Leiden Institute of Advanced Computer Science (LIACS), Niels Bohrweg 1, 2333 CA Leiden, The Netherlands, smeijer@liacs.nl
Bart Kienhuis , Leiden Institute of Advanced Computer Science (LIACS), Niels Bohrweg 1, 2333 CA Leiden, The Netherlands, kienhuis@liacs.nl
Alex Turjan , NXP Semiconductors, High Tech Campus 46, 5656 AE Eindhoven, The Netherlands, alex.turjan@nxp.com
Erwin de Kock , NXP Semiconductors, High Tech Campus 46, 5656 AE Eindhoven, The Netherlands, erwin.de.kock@nxp.com
pp. 1-6

Computing Synchronizer Failure Probabilities (PDF)

Suwen Yang , Department of Computer Science, University of British Columbia, swyang@cs.ubc.ca
Mark Greenstreet , Department of Computer Science, University of British Columbia, mrg@cs.ubc.ca
pp. 1-6

Layout-Aware Gate Duplication and Buffer Insertion (PDF)

D. Baneres , Universitat Politècnica de Catalunya, Barcelona, Spain
J. Cortadella , Universitat Politècnica de Catalunya, Barcelona, Spain
M. Kishinevsky , Strategic CAD Lab, Intel Corp., Hillsboro, OR USA
pp. 1-6

Self Heating-Aware Optimal Wire Sizing under Elmore Delay Model (PDF)

Min Ni , Electrical Engineering and Computer Science, Northwestern University Evanston, IL, mni166@ece.northwestern.edu
Seda Ogrenci Memik , Electrical Engineering and Computer Science, Northwestern University Evanston, IL, seda@ece.northwestern.edu
pp. 1-6

Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application (Abstract)

Amith Singhee , Dept. of ECE, Carnegie Mellon University, Pittsburgh, Pennsylvania, 15213 USA, asinghee@ece.cmu.edu
Rob A. Rutenbar , Dept. of ECE, Carnegie Mellon University, Pittsburgh, Pennsylvania, 15213 USA, rutenbar@ece.cmu.edu
pp. 1-6

Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design (PDF)

Yi Feng , Dept. of Computer Science, Peking University Beijing, P.R.China, fengyi@mprc.pku.edu.cn
Zheng Zhou , Dept. of Computer Science, Peking University Beijing, P.R.China, zhouzheng@mprc.pku.edu.cn
Dong Tong , Dept. of Computer Science, Peking University Beijing, P.R.China, tongdong@mprc.pku.edu.cn
Xu Cheng , Dept. of Computer Science, Peking University Beijing, P.R.China, chengxu@mprc.pku.edu.cn
pp. 1-6

Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model (Abstract)

Min Chen , Arizona State Univ., Phoenix, AZ
Wei Zhao , Arizona State Univ., Phoenix, AZ
pp. 1-6

Statistical simulation of high-frequency bipolar circuits (PDF)

W. Schneider , Atmel Germany, Theresienstr. 2, 74025 Heilbronn, Germany
M. Schroter , Chair for Electron Devices and Integrated Circuits, Dresden University of Technology, 01062 Dresden, Germany; ECE Dept., University of California San Diego, La Jolla, CA, USA
W. Kraus , Atmel Germany, Theresienstr. 2, 74025 Heilbronn, Germany
H. Wittkopf , Chair for Electron Devices and Integrated Circuits, Dresden University of Technology, 01062 Dresden, Germany
pp. 1-6

Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband Digital Signal Processing System (PDF)

M. Schamann , Lehrstuhl für Integrierte Systeme, Ruhr-Universitäat Bochum, D-44780 Bochum, Germany, marcus.schaemann@is.rub.de
S. Hessel , Lehrstuhl für Integrierte Systeme, Ruhr-Universitäat Bochum, D-44780 Bochum, Germany
U. Langmann , Lehrstuhl für Integrierte Systeme, Ruhr-Universitäat Bochum, D-44780 Bochum, Germany
M. Bucker , Nokia Research Center, Meesmannstr. 103, D-44807 Bochum, Germany, martin.bucker@nokia.com
pp. 1-6

Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures (Abstract)

Cyprian Grassmann , Infineon Technologies AG COM PS CE
Mathias Richter , Siemens CT PP 2
Mirko Sauermann , Infineon Technologies AG COM PS CE
pp. 1-6

Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow (PDF)

K. van Renterghem , Department of Information Technology, Ghent University / IMEC, Sint Pietersnieuwstraat 41, 9000 GENT, Belgium, Koen.VanRenterghem@intec.ugent.be
P. Demuytere , Department of Information Technology, Ghent University / IMEC, Sint Pietersnieuwstraat 41, 9000 GENT, Belgium
D. Verhulst , Department of Information Technology, Ghent University / IMEC, Sint Pietersnieuwstraat 41, 9000 GENT, Belgium
J. Vandewege , Department of Information Technology, Ghent University / IMEC, Sint Pietersnieuwstraat 41, 9000 GENT, Belgium
Xing-Zhi Qiu , Department of Information Technology, Ghent University / IMEC, Sint Pietersnieuwstraat 41, 9000 GENT, Belgium
pp. 1-6

An effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal UWB System-on-Chip (PDF)

Marco Crepaldi , VLSI Laboratory, Dipartimento di Elettronica, Politecnico di Torino, Italy, Email: marco.crepaldi@polito.it
Mario R. Casu , VLSI Laboratory, Dipartimento di Elettronica, Politecnico di Torino, Italy
Mariagrazia Graziano , VLSI Laboratory, Dipartimento di Elettronica, Politecnico di Torino, Italy
Maurizio Zamboni , VLSI Laboratory, Dipartimento di Elettronica, Politecnico di Torino, Italy
pp. 1-6

Behavioral Modeling of Delay-Locked Loops and its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems (PDF)

E. Barajas , Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain
R. Cosculluela , Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain
D. Coutinho , Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain
D. Mateo , Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain
J. L. Gonzalez , Electronic Engineering Department, Universitat Politècnica de Catalunya, Barcelona, Spain
I. Cairo , Barcelona R&D Laboratory, EPSON EUROPE Electronics GmbH, Sant Cugat, Spain
S. Banda , Barcelona R&D Laboratory, EPSON EUROPE Electronics GmbH, Sant Cugat, Spain
M. Ikeda , Communications Device R&D Department, SEIKO EPSON Corporation, Hirooka, Shiojiri-shi, Japan
pp. 1-6

Soft Error Rate Analysis for Sequential Circuits (PDF)

Natasa Miskov-Zivanov , Department of Electrical and Computer Engineering, Carnegie Mellon University, nmiskov@ece.cmu.edu
Diana Marculescu , Department of Electrical and Computer Engineering, Carnegie Mellon University, dianam@ece.cmu.edu
pp. 1-6

Verification-Guided Soft Error Resilience (PDF)

Sanjit A. Seshia , UC Berkeley, sseshia@eecs.berkeley.edu
Wenchao Li , UC Berkeley, wenchao@berkeley.edu
Subhasish Mitra , Stanford University, subh@stanford.edu
pp. 1-6

A Low-SER Efficient Core Processor Architecture for Future Technologies (PDF)

E. L. Rhod , Universidade Federal do Rio Grande do Sul, Escola de Engenharia and Instituto de Informática, Porto Alegre, RS, Brazil, eduardo.rhod@ufrgs.br
C. A. Lisboa , Universidade Federal do Rio Grande do Sul, Escola de Engenharia and Instituto de Informática, Porto Alegre, RS, Brazil, calisboa@inf.ufrgs.br
L. Carro , Universidade Federal do Rio Grande do Sul, Escola de Engenharia and Instituto de Informática, Porto Alegre, RS, Brazil, carro@inf.ufrgs.br
pp. 1-6

Accurate and scalable reliability analysis of logic circuits (PDF)

Mihir R. Choudhury , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005, mihir@rice.edu
Kartik Mohanram , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005, kmram@rice.edu
pp. 1-6

A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA (PDF)

Balkaran S. Gill , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio; Intel Corporation, Oregon, USA
Chris Papachristou , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio
Francis G. Wolff , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio
pp. 1-6

Design Challenges at 65nm and Beyond (PDF)

Andrew B. Kahng , University of California at San Diego, abk@ucsd.edu http://vlsicad.ucsd.edu/
pp. 1-2

The ARTEMIS Cross-Domain Architecture for Embedded Systems (PDF)

Hermann Kopetz , Technische Universität Wien, Austria, hk@vmars.tuwien.ac.at
pp. 1-2

HW/SW Implementation from Abstract Architecture Models (PDF)

Ahmed Amine Jerraya , TIMA Laboratory - 46, av. Félix Viallet - 38031 Grenoble ¿ France
pp. 1-2

Instruction-Set Customization for Real-Time Embedded Systems (PDF)

Huynh Phung Huynh , School of Computing, National University of Singapore, huynhph1@comp.nus.edu.sg
Tulika Mitra , School of Computing, National University of Singapore, tulika@comp.nus.edu.sg
pp. 1-6

A Novel Technique to Use Scratch-pad Memory for Stack Management (PDF)

Soyoung Park , School of EECS, Seoul National University, Seoul, Korea, soy@iris.snu.ac.kr
Hae-woo Park , School of EECS, Seoul National University, Seoul, Korea, starlet@iris.snu.ac.kr
Soonhoi Ha , School of EECS, Seoul National University, Seoul, Korea, sha@iris.snu.ac.kr
pp. 1-6

Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison (PDF)

Isabelle Puaut , Université de Rennes I/IRISA, Campus Universitaire de Beaulieu, 35042 RENNES Cedex - France, E-mail: Isabelle.Puaut@irisa.fr
Christophe Pais , Université de Rennes I/IRISA, Campus Universitaire de Beaulieu, 35042 RENNES Cedex - France, E-mail: Christophe.Pais@irisa.fr
pp. 1-6

Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems (PDF)

Makoto Sugihara , ISIT, 2-1-22 Momochihama, Sawara-ku, Fukuoka 814-0001 Japan, sugihara@isit.or.jp
Tohru Ishihara , Kyushu University, 3-8-33 Momochihama, Sawara-ku, Fukuoka 814-0001 Japan
Kazuaki Murakami , Kyushu University, 744 Motooka, Nishi-ku, Fukuoka 819-0395 Japan
pp. 1-6

Fast Positive-Real Balanced Truncation of Symmetric Systems Using Cross Riccati Equations (PDF)

Ngai Wong , Department of Electrical and Electronic Engineering, The University of Hong Kong, Pokfulam Road, Hong Kong, nwong@eee.hku.hk
pp. 1-6

Random Sampling of Moment Graph: A Stochastic Krylov-Reduction Algorithm (PDF)

Zhenhai Zhu , Cadence Berkeley Labs, Berkeley, CA 94704, zhzhu@cadence.com
Joel Phillips , Cadence Berkeley Labs, Berkeley, CA 94704, jrp@cadence.com
pp. 1-6

Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations (PDF)

Jeffrey Fan , Department of Electrical Engineering University of California, Riverside, CA 92521
Ning Mi , Department of Electrical Engineering University of California, Riverside, CA 92521
Sheldon X.-D. Tan , Department of Electrical Engineering University of California, Riverside, CA 92521
Yici Cai , Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China
Xianlong Hong , Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China
pp. 1-6

A Sparse Grid based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology (PDF)

Hengliang Zhu , ASIC & System State Key Lab., Microelectronics Dept., Fudan University, Shanghai, P.R. China
Xuan Zeng , ASIC & System State Key Lab., Microelectronics Dept., Fudan University, Shanghai, P.R. China, e-mail: xzeng@fudan.edu.cn
Wei Cai , Department of Mathematics, University of North Carolina at Charlotte, USA
Jintao Xue , ASIC & System State Key Lab., Microelectronics Dept., Fudan University, Shanghai, P.R. China
Dian Zhou , ASIC & System State Key Lab., Microelectronics Dept., Fudan University, Shanghai, P.R. China; E.E. Dept., The University of Texas at Dallas, USA
pp. 1-6

Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's (Abstract)

S. Bronckers , IMEC, Belgium; ELEC, Vrije Universiteit Brussel, Belgium
C. Soens , IMEC, Belgium
G. van der Plas , IMEC, Belgium
G. Vandersteen , IMEC, Belgium; ELEC, Vrije Universiteit Brussel, Belgium
Y. Rolain , ELEC, Vrije Universiteit Brussel, Belgium
pp. 1-6

Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation is Easy (PDF)

Yongpan Liu , Electronic Engineering Dept., Tsinghua Universtiy, Beijing, 100084. China, ypliu99@mails.tsinghua.edu.cn
Robert P. Dick , EECS Dept., Northwestern University, Evanston, IL 60208, U.S.A., dickrp@eecs.northwestern.edu
Li Shang , ECE Dept., Queen's University, Kingston, ON K7L 3N6, Canada, shang@ee.queensu.ca
Huazhong Yang , Electronic Engineering Dept., Tsinghua Universtiy, Beijing, 100084. China, yanghz@mail.tsinghua.edu.cn
pp. 1-6

Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling (PDF)

Swaroop Ghosh , School of Electrical and Computer Engineering, Purdue University, IN, USA
Swarup Bhunia , School of Electrical and Computer Engineering, Purdue University, IN, USA; Electrical Engineering and Computer Science, Case Western Reserve University, OH, USA
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, IN, USA
pp. 1-6

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability (PDF)

Hratch Mangassarian , University of Toronto, ECE Department, Toronto, ON M5S 3G4, hratch@eecg.toronto.edu
Andreas Veneris , University of Toronto, ECE Department, Toronto, ON M5S 3G4; University of Toronto, CS Department, Toronto, ON M5S 3G4, veneris@eecg.toronto.edu
Sean Safarpour , University of Toronto, ECE Department, Toronto, ON M5S 3G4, sean@eecg.toronto.edu
Farid N. Najm , University of Toronto, ECE Department, Toronto, ON M5S 3G4, najm@eecg.toronto.edu
Magdy S. Abadir , Freescale Semiconductor, Inc., Austin, TX 78729, M. Abadir@freescale.com
pp. 1-6

Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing (PDF)

A. Sathanur , Politecnico di Torino, 10129 Torino, ITALY
A. Calimera , Politecnico di Torino, 10129 Torino, ITALY
L. Benini , Università di Bologna, 40136 Bologna, ITALY
A. Macii , Politecnico di Torino, 10129 Torino, ITALY
E. Macii , Politecnico di Torino, 10129 Torino, ITALY
M. Poncino , Politecnico di Torino, 10129 Torino, ITALY
pp. 1-6

Process Tolerant ?-ratio Modulation for Ultra-Dynamic Voltage Scaling (PDF)

Myeong-Eun Hwang , Purdue University, IN 47907, USA, E-mail: hwangm@ecn.purdue.edu
Tamer Cakici , Purdue University, IN 47907, USA, E-mail: cakici@ecn.purdue.edu
Kaushik Roy , Purdue University, IN 47907, USA, E-mail: kaushik@ecn.purdue.edu
pp. 1-6

A Tiny and Efficient Wireless Ad-hoc Protocol for Low-cost Sensor Networks (Abstract)

Pawel Gburzynski , University of Alberta, Department of Computing Science, Edmonton, Alberta, Canada T6G 2E8, pawel@cs.ualberta.ca
Bozena Kaminska , Simon Fraser University, School of Engineering Science, Burnaby, BC, Canada V5A 1S6, kaminska@sfu.ca
Wlodek Olesinski , Olsonet Communications Corporation, 51 Wycliffe Street, Ottawa, Ontario, Canada K2G 5L9, wlodek@olsonet.com
pp. 1-6

Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets (PDF)

Gummidipudi Krishnaian , Computer Science Department, Indian Institute of Technology, New Delhi, India, Krishna@cse.iitd.ac.in
Nur Engin , NXP Semiconductors, High Tech Campus 31, 5566 AE Eindhoven, The Netherlands, Nur.Engin@nxp.com
Sergei Sawitzki , NXP Semiconductors, High Tech Campus 31, 5566 AE Eindhoven, The Netherlands, Sergei.Sawitzki@nxp.com
pp. 1-6

A New Pipelined Implementation for Minimum Norm Sorting used in Square Root Algorithm for MIMO-VBLAST Systems (PDF)

Zahid Khan , School of Engineering and Electronics, The University of Edinburgh, Mayfield Road, Scotland, UK, z.khan@ed.ac.uk
Tughrul Arslan , School of Engineering and Electronics, The University of Edinburgh, Mayfield Road, Scotland, UK
John S. Thompson , School of Engineering and Electronics, The University of Edinburgh, Mayfield Road, Scotland, UK
Ahmet T. Erdogan , School of Engineering and Electronics, The University of Edinburgh, Mayfield Road, Scotland, UK
pp. 1-6

Optimization of the "FOCUS" Inband-FEC Architecture for 10-Gbps SDH/SONET Optical Communication Channels (PDF)

Afxendios Tychopoulos , Department of Electrical and Computer Engineering, Polytechnic School of the University of Patras, Rio Patras, Greece 26500, atychopoulos@ee.upatras.gr
Odysseas Koufopavlou , Department of Electrical and Computer Engineering, Polytechnic School of the University of Patras, Rio Patras, Greece 26500, odysseas@ee.upatras.gr
pp. 1-6

A Framework for System Reliability Analysis Considering Both System Error Tolerance and Component Test Quality (PDF)

Sung-Jui Pan , Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA 93106, srpan@ece.ucsb.edu
Kwang-Ting Cheng , Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA 93106, timcheng@ece.ucsb.edu
pp. 1-6

Experimental Evaluation of Protections Against Laser-induced Faults and Consequences on Fault Modeling (PDF)

R. Leveugle , TIMA Laboratory - 46 Avenue Félix Viallet - 38031 Grenoble Cedex - France
A. Ammari , TIMA Laboratory - 46 Avenue Félix Viallet - 38031 Grenoble Cedex - France
V. Maingot , TIMA Laboratory - 46 Avenue Félix Viallet - 38031 Grenoble Cedex - France
E. Teyssou , Thalès Communications - 160 Boulevard de Valmy, BP 82 - 92704 Colombes Cedex - France
P. Moitrel , Gemalto - La Vigie, Avenue du Jujubier, ZI athelia IV - 13705 La Ciotat Cedex - France
C. Mourtel , Gemalto - La Vigie, Avenue du Jujubier, ZI athelia IV - 13705 La Ciotat Cedex - France
N. Feyt , Gemalto - La Vigie, Avenue du Jujubier, ZI athelia IV - 13705 La Ciotat Cedex - France
J.-B. Rigaud , EMSE - SESAM Laboratory - CMPGC, rue des Anémones - 13541 Gardanne - France
A. Tria , CEA-LETI - SESAM Laboratory - CMPGC, rue des Anémones - 13541 Gardanne - France
pp. 1-6

Evaluation of Design for Reliability Techniques in Embedded Flash Memories (PDF)

Benoit Godard , Libraries and Design Tools Department - Embedded Non-Volatile Memory Group ATMEL Rousset - 13106 Rousset Cedex, France; Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM Université de Montpellier II / UMR5506 CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France, benoit.godard@rfo.atmel.com
Jean-Michel Daga , Libraries and Design Tools Department - Embedded Non-Volatile Memory Group ATMEL Rousset - 13106 Rousset Cedex, France, jean-michel.daga@rfo.atmel.com
Lionel Torres , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM Université de Montpellier II / UMR5506 CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France, torres@lirmm.fr
Gilles Sassatelli , Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM Université de Montpellier II / UMR5506 CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France, sassatelli@lirmm.fr
pp. 1-6

Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance (PDF)

Tong-Yu Hsieh , Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101
Kuen-Jong Lee , Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101, E-mail: kjlee@mail.ncku.edu.tw
Melvin A. Breuer , Department of Electrical Engineering University of Southern California Los Angeles, CA 90089-2562, USA E-mail: mb@poisson.usc.edu
pp. 1-6

Use of Statistical Timing Analysis on Real Designs (PDF)

A. Nardi , Magma Design Automation - Santa Clara, California, anardi@magma-da.com
E. Tuncer , Magma Design Automation - Santa Clara, California, emre@magma-da.com
S. Naidu , Magma Design Automation - Santa Clara, California, srinath@magma-da.com
A. Antonau , Magma Design Automation - Santa Clara, California, aantonau@magma-da.com
S. Gradinaru , Magma Design Automation - Santa Clara, California, sgradina@magma-da.com
T. Lin , Magma Design Automation - Santa Clara, California, tao@magma-da.com
J. Song , Magma Design Automation - Santa Clara, California, jhsong@magma-da.com
pp. 1-6

A Novel Criticality Computation Method in Statistical Timing Analysis (PDF)

Feng Wang , The Pennsylvania State University, University Park, PA, USA, fenwang@cse.psu.edu
Yuan Xie , The Pennsylvania State University, University Park, PA, USA, yuanxie@cse.psu.edu
Hai Ju , IBM China Research Laboratory, China, juhai@cn.ibm.com
pp. 1-6

Efficient Computation of the Worst-Delay Corner (PDF)

Luis Guerra e Silva , Cadence Labs/INESC-ID, IST/TU Lisbon, Lisbon, Portugal, lgs@inesc-id.pt
L. Miguel Silveira , Cadence Labs/INESC-ID, IST/TU Lisbon, Lisbon, Portugal, lms@inesc-id.pt
Joel R. Phillips , Cadence Berkeley Labs, Cadence Design Systems, San Jose, CA 95134, U.S.A., jrp@cadence.com
pp. 1-6

Accounting for Cache-Related Preemption Delay in Dynamic Priority Schedulability Analysis (PDF)

Lei Ju , Department of Computer Science, National University of Singapore, E-mail: julei@comp.nus.edu.sg
Samarjit Chakraborty , Department of Computer Science, National University of Singapore, E-mail: samarjit@comp.nus.edu.sg
Abhik Roychoudhury , Department of Computer Science, National University of Singapore, E-mail: abhik@comp.nus.edu.sg
pp. 1-6

Energy-Efficient Real-Time Task Scheduling with Task Rejection (PDF)

Jian-Jia Chen , Department of Computer Science and Information Engineering, National Taiwan University Taipei, Taiwan, Email:r90079@csie.ntu.edu.tw
Tei-Wei Kuo , Department of Computer Science and Information Engineering, National Taiwan University Taipei, Taiwan, Email:ktw@csie.ntu.edu.tw
Chia-Lin Yang , Department of Computer Science and Information Engineering, National Taiwan University Taipei, Taiwan, Email:yangc@csie.ntu.edu.tw
Ku-Jei King , xSeries Development IBM Systems Technology Group (STG) Email: kujei@tw.ibm.com
pp. 1-6

Feasibility Intervals for Multiprocessor Fixed-Priority Scheduling of Arbitrary Deadline Periodic Systems (PDF)

Liliana Cucu , Université Libre de Bruxelles, C.P. 212, 50 Avenue Franklin D. Roosevelt, 1050 Brussels, Belgium; Post-doctorante du F.N.R.S., E-mail: liliana.cucu@ulb.ac.be
Joel Goossens , Université Libre de Bruxelles, C.P. 212, 50 Avenue Franklin D. Roosevelt, 1050 Brussels, Belgium, E-mail:joel.goossens@ulb.ac.be
pp. 1-6

Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems (PDF)

Meikang Qiu , Department of Computer Science, University of Texas at Dallas, Richardson, Texas 75083, USA, mxq012100@utdallas.edu
Chun Xue , Department of Computer Science, University of Texas at Dallas, Richardson, Texas 75083, USA, cxx016000@utdallas.edu
Zili Shao , Department of Computing Hong Kong Polytechnic University Hung Hom, Kowloon, Hong Kong cszshao@comp.polyu.edu.hk
Edwin H.-M. Sha , Department of Computer Science, University of Texas at Dallas, Richardson, Texas 75083, USA, edsha@utdallas.edu
pp. 1-6

Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks (PDF)

Alireza Ejlali , Department of Computer Engineering, Sharif University of Technology, Azadi Ave., Tehran, Iran, ejlali@sharif.edu
Bashir M. Al-Hashimi , School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, UK, bmah@ecs.soton.ac.uk
Paul Rosinger , School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, UK, pmr@ecs.soton.ac.uk
Seyed Ghassem Miremadi , Department of Computer Engineering, Sharif University of Technology, Azadi Ave., Tehran, Iran, miremadi@sharif.edu
pp. 1-6

Impact of Process Variations on Multicore Performance Symmetry (Abstract)

Eric Humenay , Dept. of Computer Science, University of Virginia, Charlottesville, VA 22904, humenay@virginia.edu
David Tarjan , Dept. of Computer Science, University of Virginia, Charlottesville, VA 22904, dtarjan@cs.virginia.edu
Kevin Skadron , Dept. of Computer Science, University of Virginia, Charlottesville, VA 22904, skadron@cs.virginia.edu
pp. 1-6

Temperature Aware Task Scheduling in MPSoCs (PDF)

Ayse Kivilcim Coskun , University of California, San Diego
Tajana Simunic Rosing , University of California, San Diego
Keith Whisnant , Sun Microsystems, San Diego
pp. 1-6

Architectural Leakage-Aware Management of Partitioned Scratchpad Memories (PDF)

Olga Golubeva , Dipartimento di Automatica e Informatica, Politecnico di Torino, olga.golubeva@polito.it
Mirko Loghi , Dipartimento di Automatica e Informatica, Politecnico di Torino, mirko.loghi@polito.it
Massimo Poncino , Dipartimento di Automatica e Informatica, Politecnico di Torino, massimo.poncino@polito.it
Enrico Macii , Dipartimento di Automatica e Informatica, Politecnico di Torino, enrico.macii@polito.it
pp. 1-6

Memory Bank Aware Dynamic Loop Scheduling (PDF)

Mahmut Kandemir , Dept. of Computer Science and Engineering, The Pennsylvania State University, University Park, PA 16802, USA, kandemir@cse.psu.edu
Taylan Yemliha , College of Engineering and Computer Science, Syracuse University, Syracuse, NY 13244, USA tyemliha@syr.edu
Seung Woo Son , Dept. of Computer Science and Engineering, The Pennsylvania State University, University Park, PA 16802, USA, sson@cse.psu.edu
Ozcan Ozturk , Dept. of Computer Science and Engineering, The Pennsylvania State University, University Park, PA 16802, USA, ozturk@cse.psu.edu
pp. 1-6

System Level Clock Tree Synthesis for Power Optimization (PDF)

Saif Ali Butt , Chip Vision Design Systems AG, Oldenburg, Germany
Stefan Schmermbeck , Chip Vision Design Systems AG, Oldenburg, Germany
Jurij Rosenthal , Chip Vision Design Systems AG, Oldenburg, Germany
Alexander Pratsch , Chip Vision Design Systems AG, Oldenburg, Germany
Eike Schmidt , Chip Vision Design Systems AG, Oldenburg, Germany
pp. 1-6

Author index (PDF)

pp. 1-9
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