The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2007)
Nice
Apr. 16, 2007 to Apr. 20, 2007
ISBN: 978-3-9810801-2-4
TABLE OF CONTENTS
Papers

Covers (PDF)

pp. 1

Opinion (PDF)

pp. 7

Awards (PDF)

pp. 8

Tutorial (PDF)

pp. 9

Challenges of Digital Consumer and Mobile SoC's: More Moore Possible? (PDF)

Tohru Furuyama , General Manager, Center for Semiconductor Research&Development (CSRD), Toshiba Corp., JP
pp. 12

ATLAS: A Chip-Multiprocessor with Transactional Memory Support (Abstract)

J. Casper , Comput. Syst. Lab., Stanford Univ., CA
D. Ge , Comput. Syst. Lab., Stanford Univ., CA
N. Njoroge , Comput. Syst. Lab., Stanford Univ., CA
K. Olukotun , Comput. Syst. Lab., Stanford Univ., CA
Y. Teslyar , Comput. Syst. Lab., Stanford Univ., CA
C. Kozyrakis , Comput. Syst. Lab., Stanford Univ., CA
S. Wee , Comput. Syst. Lab., Stanford Univ., CA
pp. 14

A dynamically adaptive DSP for heterogeneous reconfigurable platforms (Abstract)

P. Rolandi , ST Microelectron., Agrate Brianza
M. Pizzotti , ST Microelectron., Agrate Brianza
L. Ciccarelli , ST Microelectron., Agrate Brianza
F. Campi , ST Microelectron., Agrate Brianza
A. Deledda , ST Microelectron., Agrate Brianza
pp. 15

An 0.9 x 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface (Abstract)

P. Stanley-Marbell , Dept. of ECE, Carnegie Mellon Univ., Pittsburgh, PA
D. Marculescu , Dept. of ECE, Carnegie Mellon Univ., Pittsburgh, PA
pp. 16

An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio (Abstract)

null Zhuan Ye , Wireless Solutions Res. Center, Schaumburg, IL
J. Grosspietsch , Wireless Solutions Res. Center, Schaumburg, IL
pp. 17

A Non-Intrusive Isolation Approach for Soft Cores (Abstract)

O. Sinanoglu , Dept. of Math&Comput. Sci., Kuwait Univ., Safat
pp. 18

Unknown Blocking Scheme for Low Control Data Volume and High Observability (Abstract)

null Seongmoon Wang , NEC Labs. America, Princeton, NJ
S.T. Chakradhar , NEC Labs. America, Princeton, NJ
null Wenlong Wei , NEC Labs. America, Princeton, NJ
pp. 19

High-Level Test Synthesis for Delay Fault Testability (Abstract)

null Tung-Hua Yeh , Dept. of Comput. Sci., National Chung-Hsing Univ., Taichung
null Sying-Jyan Wang , Dept. of Comput. Sci., National Chung-Hsing Univ., Taichung
pp. 21

Bus Access Optimisation for FlexRay-based Distributed Embedded Systems (Abstract)

T. Pop , Dept. of Comput.&Inf. Sci., Linkoping Univ.
pp. 22

A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors (Abstract)

K. Ravindran , Dept. of Electr. Eng.&Comput. Sci., California Univ., Berkeley, CA
N. Satish , Dept. of Electr. Eng.&Comput. Sci., California Univ., Berkeley, CA
K. Keutzer , Dept. of Electr. Eng.&Comput. Sci., California Univ., Berkeley, CA
pp. 23

Simulation-based reusable posynomial models for MOS transistor parameters (Abstract)

V. Aggarwal , EvoDesignOpt Group, MIT, Cambridge, MA
U.-M. O'Reilly , EvoDesignOpt Group, MIT, Cambridge, MA
pp. 25

Trade-Off Design of Analog Circuits using Goal Attainment and "Wave Front" Sequential Quadratic Programming (Abstract)

H. Graeb , Inst. for Electron. Design Autom., TU Muenchen
U. Schlichtmann , Inst. for Electron. Design Autom., TU Muenchen
D. Mueller , Inst. for Electron. Design Autom., TU Muenchen
pp. 26

An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection (Abstract)

G. Gielen , Dept. of Electr. Eng., ESAT-MICAS, Leuven
W. Sansen , Dept. of Electr. Eng., ESAT-MICAS, Leuven
M. Steyaert , Dept. of Electr. Eng., ESAT-MICAS, Leuven
T. Eeckelaert , Dept. of Electr. Eng., ESAT-MICAS, Leuven
R. Schoofs , Dept. of Electr. Eng., ESAT-MICAS, Leuven
pp. 27

A Coefficient Optimization and Architecture Selection Tool for ?? Modulators in MATLAB (Abstract)

G. Dundar , Dept. of Electr.&Electron. Eng., Bogazici Univ., Istanbul
S. Talay , Dept. of Electr.&Electron. Eng., Bogazici Univ., Istanbul
O. Yetik , Dept. of Electr.&Electron. Eng., Bogazici Univ., Istanbul
O. Saglamdemir , Dept. of Electr.&Electron. Eng., Bogazici Univ., Istanbul
pp. 28

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures (Abstract)

C. Ostler , Dept. of CSE, Arizona State Univ., Tempe, AZ
K.S. Chatha , Dept. of CSE, Arizona State Univ., Tempe, AZ
pp. 30

A Smooth Refinement Flow for Co-designing HW and SW Threads (Abstract)

P. Destro , Dipt. di Informatica, Univ. di Verona
G. Pravadelli , Dipt. di Informatica, Univ. di Verona
F. Fummi , Dipt. di Informatica, Univ. di Verona
pp. 31

Speeding Up SystemC Simulation through Process Splitting (Abstract)

Y.N. Naguib , Dept. of Electron.&Commun. Eng., Cairo Univ., Giza
R.S. Guindi , Dept. of Electron.&Commun. Eng., Cairo Univ., Giza
pp. 32

Hard Real-Time Reconfiguration Port Scheduling (Abstract)

F. Dittmann , Heinz Nixdorf Inst., Paderborn Univ.
S. Frank , Heinz Nixdorf Inst., Paderborn Univ.
pp. 34

An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs (Abstract)

null Jin Cui , Dept. of Comput. Sci., Northeastern Univ., Shenyang
null Qingxu Deng , Dept. of Comput. Sci., Northeastern Univ., Shenyang
pp. 35

Improving Utilization of Reconfigurable Resources Using Two Dimensional Compaction (Abstract)

H.M. El-Boghdadi , Comput. Eng. Dept., Cairo Univ., Giza
S.I. Shaheen , Comput. Eng. Dept., Cairo Univ., Giza
A.A. El Farag , Comput. Eng. Dept., Cairo Univ., Giza
pp. 36

Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems (Abstract)

R. Lysecky , Dept. of Electr.&Comput. Eng., Arizona Univ.
pp. 37

A Shift Register based Clause Evaluator for Reconfigurable SAT Solver (Abstract)

M.W. El-Kharashi , Comput.&Syst. Eng. Dept., Ain Shams Univ., Cairo
M. Safar , Comput.&Syst. Eng. Dept., Ain Shams Univ., Cairo
M. Shalan , Comput.&Syst. Eng. Dept., Ain Shams Univ., Cairo
pp. 39

Improve CAM Power Efficiency Using Decoupled Match Line Scheme (Abstract)

null Yuan-Hong Liao , Dept. of Comput. Sci., Nat. ChungHsing Univ., Taichung
null Yen-Jen Chang , Dept. of Comput. Sci., Nat. ChungHsing Univ., Taichung
pp. 41

Cyclostationary Feature Detection on a tiled-SoC (Abstract)

J. Kuper , Twente Univ.
G.J.M. Smit , Twente Univ.
null Thijs Krol , Twente Univ.
A.B.J. Kokkeler , Twente Univ.
pp. 42

An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm (Abstract)

E. Sahin , Fac. of Eng.&Natural Sci., Sabanci Univ., Istanbul
I. Hamzaoglu , Fac. of Eng.&Natural Sci., Sabanci Univ., Istanbul
pp. 44

An FPGA Implementation of Decision Tree Classification (Abstract)

null Gokhan Memik , Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
null Alok Choudhary , Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
R. Narayanan , Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
D. Honbo , Electr. Eng.&Comput. Sci., Northwestern Univ., Evanston, IL
pp. 45

Radix 4 SRT Division with Quotient Prediction and Operand Scaling (Abstract)

N.R. Srivastava , Illinois Inst. of Technol., Chicago, IL
pp. 46

Optimized Integration of Test Compression and Sharing for SOC Testing (Abstract)

A. Larsson , Embedded Syst. Lab., Linkopings Universitet, Linkoping
P. Eles , Embedded Syst. Lab., Linkopings Universitet, Linkoping
null Zebo Peng , Embedded Syst. Lab., Linkopings Universitet, Linkoping
E. Larsson , Embedded Syst. Lab., Linkopings Universitet, Linkoping
pp. 48

Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor (Abstract)

null Thuyen Le , IBM Deutschland Entwicklung, Boblingen
null Tilman Glokler , IBM Deutschland Entwicklung, Boblingen
pp. 50

Low Cost Debug Architecture using Lossy Compression for Silicon Debug (Abstract)

null Ehab Anis , Dept. of Electr.&Comput. Eng., McMaster Univ., Hamilton, Ont.
N. Nicolici , Dept. of Electr.&Comput. Eng., McMaster Univ., Hamilton, Ont.
pp. 51

An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers (Abstract)

M. Imanishi , Graduate Sch. of Inf. Sci., Nara Inst. of Sci.&Technol., Kansai Science
T. Yoneda , Graduate Sch. of Inf. Sci., Nara Inst. of Sci.&Technol., Kansai Science
H. Fujiwara , Graduate Sch. of Inf. Sci., Nara Inst. of Sci.&Technol., Kansai Science
pp. 52

CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions (Abstract)

M. Olbrich , Inst. of Microelectron. Syst., Leibniz Univ., Hannover
M. Zhang , Inst. of Microelectron. Syst., Leibniz Univ., Hannover
pp. 54

A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs (Abstract)

S. Tahar , Concordia Univ., Montreal, Que.
M.H. Zaki , Concordia Univ., Montreal, Que.
null Ghiath Al-Sammane , Concordia Univ., Montreal, Que.
pp. 55

Efficient Nonlinear Distortion Analysis of RF Circuits (Abstract)

D. Tannir , Dept. of Electr.&Comput. Eng., McGill Univ., Montreal, Que.
R. Khazaka , Dept. of Electr.&Comput. Eng., McGill Univ., Montreal, Que.
pp. 56

Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations (Abstract)

G. Vandersteen , Dept. ELEC, Vrije Universiteit, Brussel
R. Pintelon , Dept. ELEC, Vrije Universiteit, Brussel
J. Lataire , Dept. ELEC, Vrije Universiteit, Brussel
pp. 58

Performance Analysis of Complex Systems by Integration of Dataflow Graphs and Compositional Performance Analysis (Abstract)

R. Ernst , Inst. of Comput.&Commun. Network Eng., Braunschweig Tech. Univ.
S. Stein , Inst. of Comput.&Commun. Network Eng., Braunschweig Tech. Univ.
S. Schliecker , Inst. of Comput.&Commun. Network Eng., Braunschweig Tech. Univ.
pp. 59

Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL (Abstract)

S.K. Shukla , Bradley Dept. of Electr.&Comput. Eng., Virginia Polytech. Inst.&State Univ.
H.D. Patel , Bradley Dept. of Electr.&Comput. Eng., Virginia Polytech. Inst.&State Univ.
pp. 60

A Calculator for Pareto Points (Abstract)

T. Basten , Dept. of Electr. Eng., Eindhoven Univ. of Technol.
M. Geilen , Dept. of Electr. Eng., Eindhoven Univ. of Technol.
pp. 61

System Level Power Optimization of Sigma-Delta Modulator (Abstract)

null Fei Gong , Inst. of VLSI Design, Zhejiang Univ., Hangzhou
null Xiaobo Wu , Inst. of VLSI Design, Zhejiang Univ., Hangzhou
pp. 63

Executable system-level specification models containing UML-based behavioral patterns (Abstract)

A. Thuy , Inst. of Microelectron. Syst., Technische Universitdt Darmstadt
M. Glesner , Inst. of Microelectron. Syst., Technische Universitdt Darmstadt
L.S. Indrusiak , Inst. of Microelectron. Syst., Technische Universitdt Darmstadt
pp. 64

Two-Level Microprocessor-Accelerator Partitioning (Abstract)

S. Lonardi , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
F. Vahid , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
S. Sirowy , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
null Yonghui Wu , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
pp. 66

Design Space Exploration of Partially Re-configurable Embedded Processors (Abstract)

D. Kammler , Integrated Signal Process. Syst., RWTH Aachen Univ.
R. Leupers , Integrated Signal Process. Syst., RWTH Aachen Univ.
W. Ahmed , Integrated Signal Process. Syst., RWTH Aachen Univ.
H. Meyr , Integrated Signal Process. Syst., RWTH Aachen Univ.
K. Karari , Integrated Signal Process. Syst., RWTH Aachen Univ.
G. Ascheid , Integrated Signal Process. Syst., RWTH Aachen Univ.
A. Chattopadhyay , Integrated Signal Process. Syst., RWTH Aachen Univ.
pp. 67

Low Complexity LDPC Code Decoders for Next Generation Standards (Abstract)

T. Brack , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ.
T. Lehnigk-Emden , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ.
F. Kienle , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ.
M. Alles , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ.
N. Wehn , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ.
pp. 69

Non-fractional parallelism in LDPC Decoder implementations (Abstract)

J. Dielissen , NXP Semicond., Eindhoven
A. Hekstra , NXP Semicond., Eindhoven
pp. 70

Minimum-Energy LDPC Decoder for Real-Time Mobile Application (Abstract)

null Gwan Choi , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
null Weihuang Wang , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
pp. 71

Implementation of AES/Rijndael on a dynamically reconfigurable architecture (Abstract)

A. Deledda , ARCES, Bologna Univ.
A. Lodi , ARCES, Bologna Univ.
L. Vanzolini , ARCES, Bologna Univ.
R. Guerrieri , ARCES, Bologna Univ.
C. Mucci , ARCES, Bologna Univ.
pp. 73

Using the Inter- and Intra-Switch Regularity in NoC Switch Testing (Abstract)

M. Hosseinabady , Nanoelectronics-Center of Excellence, Tehran Univ.
Z. Navabi , Nanoelectronics-Center of Excellence, Tehran Univ.
A. Dalirsani , Nanoelectronics-Center of Excellence, Tehran Univ.
pp. 74

Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips (Abstract)

K. Petersen , Dept. of Electron. Comput.&Software Syst., R. Inst. of Technol., Kista
K. Oberg , Dept. of Electron. Comput.&Software Syst., R. Inst. of Technol., Kista
pp. 75

Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks (Abstract)

O. Laouamri , DeFacTo Technol., Moirans
C. Aktouf , DeFacTo Technol., Moirans
pp. 76

Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations (Abstract)

F. Balasa , Dept. of Comput. Sci., Illinois Univ., Chicago, IL
H.I. Luican , Dept. of Comput. Sci., Illinois Univ., Chicago, IL
null Hongwei Zhu , Dept. of Comput. Sci., Illinois Univ., Chicago, IL
pp. 78

Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip (Abstract)

S. Lonardi , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
S. Sirowy , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
null Yonghui Wu , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
F. Vahid , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
pp. 80

System-Level Process Variation Driven Throughput Analysis for Single and Multiple Voltage-Frequency Island Designs (Abstract)

D. Marculescu , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
S. Garg , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
pp. 81

Reliability-Aware System Synthesis (Abstract)

T. Streichert , Erlangen-Nuremberg Univ., Erlangen
C. Haubelt , Erlangen-Nuremberg Univ., Erlangen
M. Lukasiewycz , Erlangen-Nuremberg Univ., Erlangen
J. Teich , Erlangen-Nuremberg Univ., Erlangen
M. Glass , Erlangen-Nuremberg Univ., Erlangen
pp. 82

Flexibility-oriented Design Methodology for Reconfigurable ?? Modulators (Abstract)

null Pengbo Sun , Dept. of Electr.&Comput. Eng., State Univ. of New York, Stony Brook, NY
null Ying Wei , Dept. of Electr.&Comput. Eng., State Univ. of New York, Stony Brook, NY
A. Doboli , Dept. of Electr.&Comput. Eng., State Univ. of New York, Stony Brook, NY
pp. 83

Experimental Validation of a Tuning Algorithm for High-Speed Filters (Abstract)

G. Matarrese , Dipt. di Elettrotecnica ed Elettronica, Politecnico di Bari
C. Marzocca , Dipt. di Elettrotecnica ed Elettronica, Politecnico di Bari
F. Corsi , Dipt. di Elettrotecnica ed Elettronica, Politecnico di Bari
pp. 84

Design of High-Resolution MOSFET-Only Pipelined ADCs with Digital Calibration (Abstract)

H. Aminzadeh , Dept. of EE, Ferdowsi Univ. of Mashhad
M. Danaie , Dept. of EE, Ferdowsi Univ. of Mashhad
R. Lotfi , Dept. of EE, Ferdowsi Univ. of Mashhad
pp. 85

Automatic Synthesis of Compressor Trees: Reevaluating Large Counters (Abstract)

P. Ienne , Sch. of Comput.&Commun. Sci., Ecole Polytechnique Federale de Lausanne
A.K. Verma , Sch. of Comput.&Commun. Sci., Ecole Polytechnique Federale de Lausanne
pp. 88

Area Optimization of Multi-Cycle Operators in High-Level Synthesis (Abstract)

R. Hermida , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid
R. Ruiz-Sautua , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid
M.C. Molina , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid
J.M. Mendias , Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid
pp. 89

Data-Flow Transformations using Taylor Expansion Diagrams (Abstract)

D. Gomez-Prado , Dept. of Electr.&Comput. Eng., Massachusetts Univ., Amherst, MA
S. Askar , Dept. of Electr.&Comput. Eng., Massachusetts Univ., Amherst, MA
M. Ciesielski , Dept. of Electr.&Comput. Eng., Massachusetts Univ., Amherst, MA
pp. 90

Automatic Application Specific Floating-point Unit Generation (Abstract)

null Yee Jern Chong , Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW
null Sri Parameswaran , Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW
pp. 91

Time-Constrained Clustering for DSE of Clustered VLIW-ASP (Abstract)

M. Scholzel , Dept. of Comput. Sci., Brandenburg Univ. of Technol., Cottbus
pp. 92

Timing Simulation of Interconnected AUTOSAR Software-Components (Abstract)

O. Bringmann , FZI Forschungszentrum Informatik Haid-und-Neu-Strasse, Karlsruhe
M. Krause , FZI Forschungszentrum Informatik Haid-und-Neu-Strasse, Karlsruhe
pp. 94

Low-g Accelerometer Fast Prototyping for Automotive Applications (Abstract)

M. Tonarelli , Dept. of Inf. Eng., Pisa Univ.
F.D. Ascoli , Dept. of Inf. Eng., Pisa Univ.
C. Marino , Dept. of Inf. Eng., Pisa Univ.
F. Iozzi , Dept. of Inf. Eng., Pisa Univ.
L. Fanucci , Dept. of Inf. Eng., Pisa Univ.
M. Melani , Dept. of Inf. Eng., Pisa Univ.
pp. 96

Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508 (Abstract)

G. Boschi , YOGITECH SpA, Pisa
F. Colucci , YOGITECH SpA, Pisa
R. Mariani , YOGITECH SpA, Pisa
pp. 97

Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System (Abstract)

C. Claus , Lehrstuhl fur integrierte Syst., Technische Univ. Munchen
F. Muller , Lehrstuhl fur integrierte Syst., Technische Univ. Munchen
J. Zeppenfeld , Lehrstuhl fur integrierte Syst., Technische Univ. Munchen
W. Stechele , Lehrstuhl fur integrierte Syst., Technische Univ. Munchen
pp. 98

Towards a Methodology for the Quantitative Evaluation of Automotive Architectures (Abstract)

P. Popp , Gen. Motors Res.&Dev., Warren, MI
M. DiNatale , Gen. Motors Res.&Dev., Warren, MI
pp. 99

Dynamic Learning Based Scan Chain Diagnosis (Abstract)

null Yu Huang , Mentor Graphics Corp., Marlborough, MA
pp. 100

Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations (Abstract)

O. Sinanoglu , Dept. of Math&Comput. Sci., Kuwait Univ., Safat
pp. 101

On Test Generation by Input Cube Avoidance (Abstract)

I. Pomeranz , Sch. of Electr.&Comput. Eng., Purdue Univ., W. Lafayette, IN
pp. 102

Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution (Abstract)

A. Ney , Lab. d'Informatique, de Robotique et de Microelectronique de Montpellier, Univ. de Montpellier
P. Girard , Lab. d'Informatique, de Robotique et de Microelectronique de Montpellier, Univ. de Montpellier
C. Landrault , Lab. d'Informatique, de Robotique et de Microelectronique de Montpellier, Univ. de Montpellier
S. Pravossoudovitch , Lab. d'Informatique, de Robotique et de Microelectronique de Montpellier, Univ. de Montpellier
A. Virazel , Lab. d'Informatique, de Robotique et de Microelectronique de Montpellier, Univ. de Montpellier
pp. 103

On Power-profiling and Pattern Generation for Power-safe Scan Tests (Abstract)

C.P. Ravikumar , ASIC, Texas Instruments India Pvt. Ltd., Bangalore
V.R. Devanathan , ASIC, Texas Instruments India Pvt. Ltd., Bangalore
pp. 104

Automatic Test Pattern Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults (Abstract)

S. Kundu , Massachusetts Univ., Amherst, MA
K.P. Ganeshpure , Massachusetts Univ., Amherst, MA
pp. 105

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation (Abstract)

null Hong Luo , Dept. of E.E., Tsinghua Univ., Beijing
null Huazhong Yang , Dept. of E.E., Tsinghua Univ., Beijing
null Ku He , Dept. of E.E., Tsinghua Univ., Beijing
null Rong Luo , Dept. of E.E., Tsinghua Univ., Beijing
null Yu Wang , Dept. of E.E., Tsinghua Univ., Beijing
pp. 106

A Cross-Referencing-Based Droplet Manipulation Method for High-Throughput and Pin-Constrained Digital Microfluidic Arrays (Abstract)

null Tao Xu , Dept. of Electr.&Comput. Eng., Duke Univ., Durham, NC
K. Chakrabarty , Dept. of Electr.&Comput. Eng., Duke Univ., Durham, NC
pp. 107

Distributed Power-Management Techniques for Wireless Network Video Systems (Abstract)

N.H. Zamora , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
null Jung-Chun Kao , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
R. Marculescu , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
pp. 109

Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits (Abstract)

K. Nepal , Div. of Eng., Brown Univ., Providence, RI
R.I. Bahar , Div. of Eng., Brown Univ., Providence, RI
W.R. Patterson , Div. of Eng., Brown Univ., Providence, RI
J. Mundy , Div. of Eng., Brown Univ., Providence, RI
A. Zaslavsky , Div. of Eng., Brown Univ., Providence, RI
pp. 111

Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints (Abstract)

R.G. Dimond , Dept. of Comput., Imperial Coll. London
K. Atasu , Dept. of Comput., Imperial Coll. London
O. Mencer , Dept. of Comput., Imperial Coll. London
W. Luk , Dept. of Comput., Imperial Coll. London
pp. 113

Resource Prediction for Media Stream Decoding (Abstract)

L. Eeckhout , Dept. of ELIS, Ghent Univ.
J. Hamers , Dept. of ELIS, Ghent Univ.
pp. 114

Register Pointer Architecture for Efficient Embedded Processors (Abstract)

null Sung-Boem Park , Comput. Syst. Lab., Stanford Univ., CA
J.D. Balfour , Comput. Syst. Lab., Stanford Univ., CA
C. Kozyrakis , Comput. Syst. Lab., Stanford Univ., CA
D. Black-Schaffer , Comput. Syst. Lab., Stanford Univ., CA
W.J. Dally , Comput. Syst. Lab., Stanford Univ., CA
null JongSoo Park , Comput. Syst. Lab., Stanford Univ., CA
pp. 115

A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy (Abstract)

V. Porpodas , Dept. of Electr.&Comput. Eng., Patras Univ., Rio
A. Milidonis , Dept. of Electr.&Comput. Eng., Patras Univ., Rio
C.E. Goutis , Dept. of Electr.&Comput. Eng., Patras Univ., Rio
H. Michail , Dept. of Electr.&Comput. Eng., Patras Univ., Rio
N. Alachiotis , Dept. of Electr.&Comput. Eng., Patras Univ., Rio
A.P. Kakarountas , Dept. of Electr.&Comput. Eng., Patras Univ., Rio
pp. 117

An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification (Abstract)

N. Jayakumar , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
S.P. Khatri , Dept. of Electr.&Comput. Eng., Texas A&M Univ., College Station, TX
pp. 118

Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network (Abstract)

J.L. Oatley , Div. of Eng.&Appl. Sci., Harvard Univ., Cambridge, MA
M.S. Gupta , Div. of Eng.&Appl. Sci., Harvard Univ., Cambridge, MA
pp. 119

Process Variation Tolerant Low Power DCT Architecture (Abstract)

K. Roy , Purdue Univ., West Lafayette, IN
G. Karakonstantis , Purdue Univ., West Lafayette, IN
N. Banerjee , Purdue Univ., West Lafayette, IN
pp. 120

Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction (Abstract)

null Yan Lin , Dept. of Electr. Eng., California Univ., Los Angeles, CA
null Lei He , Dept. of Electr. Eng., California Univ., Los Angeles, CA
pp. 121

Hardware Scheduling Support in SMP Architectures (Abstract)

A.C. Nacul , Center for Embedded Syst., California Univ., Irvine, CA
pp. 122

Butterfly and Benes-Based on-Chip Communication Networks for Multiprocessor Turbo Decoding (Abstract)

O. Muller , Dept. of Electron., ENST Bretagne, Brest
M. Jezequel , Dept. of Electron., ENST Bretagne, Brest
A. Baghdadi , Dept. of Electron., ENST Bretagne, Brest
H. Moussa , Dept. of Electron., ENST Bretagne, Brest
pp. 124

Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs (Abstract)

J. Suhonen , Inst. of Comput.&Digital Syst., Tampere Univ. of Technol.
pp. 126

Design methods for Security and Trust (Abstract)

I. Verbauwhede , ESAT/COSIC, Katholieke Universiteit, Leuven
pp. 127

Testable Design for Advanced Serial-Link Transceivers (Abstract)

M. Lin , Dept. of Electr.&Comput. Eng., California Univ., Santa Barbara, CA
pp. 132

Method for Reducing Jitter in Multi-Gigahertz ATE (Abstract)

D.C. Keezer , Georgia Inst. of Technol., Atlanta , GA
pp. 133

An ADC-BiST Scheme Using Sequential Code Analysis (Abstract)

E.S. Erdogan , Dept. of Electr.&Comput. Eng., Duke Univ., Durham, NC
pp. 135

Boosting SER Test for RF Transceivers by Simple DSP Technique (Abstract)

J. Dabrowski , Dept. of Electr. Eng., Linkoping Univ.
pp. 136

Engineering Trust with Semantic Guardians (Abstract)

I. Wagner , Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI
pp. 140

A One-Shot Configurable-Cache Tuner for Improved Energy and Performance (Abstract)

A. Gordon-Ross , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
pp. 142

Stochastic Modeling and Optimization for Robust Power Management in a Partially Observable System (Abstract)

null Qing Wu , Dept. of Electr.&Comput. Eng., Binghamton Univ., NY
null Qinru Qiu , Dept. of Electr.&Comput. Eng., Binghamton Univ., NY
null Ying Tan , Dept. of Electr.&Comput. Eng., Binghamton Univ., NY
pp. 146

Efficient and Scalable Compiler-Directed Energy Optimization for Realtime Applications (Abstract)

null Po-Kuan Huang , Dept. of Electr.&Comput. Eng., California Univ., Davis, CA
pp. 147

Peripheral-Conscious Scheduling on Energy Minimization for Weakly Hard Real-time Systems (Abstract)

null Gang Quan , Dept. of Comput. Sci.&Eng., South Carolina Univ., Columbia, SC
null Linwei Niu , Dept. of Comput. Sci.&Eng., South Carolina Univ., Columbia, SC
pp. 148

Task Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoC (Abstract)

M. Kondo , Res. Center of Adv. Sci.&Technol. (RCAST), Tokyo Univ.
T. Nanya , Res. Center of Adv. Sci.&Technol. (RCAST), Tokyo Univ.
M. Imai , Res. Center of Adv. Sci.&Technol. (RCAST), Tokyo Univ.
R. Watanabe , Res. Center of Adv. Sci.&Technol. (RCAST), Tokyo Univ.
H. Nakamura , Res. Center of Adv. Sci.&Technol. (RCAST), Tokyo Univ.
pp. 149

Instruction Trace Compression for Rapid Instruction Cache Simulation (Abstract)

A. Janapsatya , Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW
pp. 150

Efficient Code Density Through Look-up Table Compression (Abstract)

J. Henkel , Dept. of Comput. Sci., Karlsruhe Univ.
T. Bonny , Dept. of Comput. Sci., Karlsruhe Univ.
pp. 151

Soft-core Processor Customization using the Design of Experiments Paradigm (Abstract)

F. Vahid , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
S. Lonardi , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
D. Sheldon , Dept. of Comput. Sci.&Eng., California Univ., Riverside, CA
pp. 153

Portable Multimedia SoC Design: a Global Challenge (Abstract)

S. Ducrey , Application Processor Div., STMicroelectronics, Grenoble
M. Paganini , Application Processor Div., STMicroelectronics, Grenoble
G. Caubit , Application Processor Div., STMicroelectronics, Grenoble
G. Kimmich , Application Processor Div., STMicroelectronics, Grenoble
V. Coeffe , Application Processor Div., STMicroelectronics, Grenoble
pp. 156

What If You Could Design Tomorrow's System Today? (Abstract)

N. Wingen , NXP Semicond., Eindhoven
pp. 157

Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling (Abstract)

Y.B. Kim , Dept. of Electr.&Comput. Eng., Northeastern Univ., Boston, MA
F. Lombardi , Dept. of Electr.&Comput. Eng., Northeastern Univ., Boston, MA
B. Jang , Dept. of Electr.&Comput. Eng., Northeastern Univ., Boston, MA
pp. 159

Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs (Abstract)

W. Rao , Dept. of CSE, California Univ., San Diego, CA
A. Orailoglu , Dept. of CSE, California Univ., San Diego, CA
pp. 162

A Multi-Core Debug Platform for NoC-Based Systems (Abstract)

S. Tang , Dept. of Comput. Sci.&Eng., Chinese Univ. of Hong Kong, Kowloon
null Qiang Xu , Dept. of Comput. Sci.&Eng., Chinese Univ. of Hong Kong, Kowloon
pp. 163

Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support (Abstract)

M. de Nanclas , Dept. of Comput. Eng., Ecole Polytechnique de Montreal, Que.
L. Moss , Dept. of Comput. Eng., Ecole Polytechnique de Montreal, Que.
S. Fontaine , Dept. of Comput. Eng., Ecole Polytechnique de Montreal, Que.
G. Bois , Dept. of Comput. Eng., Ecole Polytechnique de Montreal, Que.
M. Aboulhamid , Dept. of Comput. Eng., Ecole Polytechnique de Montreal, Que.
L. Filion , Dept. of Comput. Eng., Ecole Polytechnique de Montreal, Que.
pp. 164

Incremental ABV for Functional Validation of TL-to-RTL Design Refinement (Abstract)

F. Fummi , Dipt. di Informatica, Universita di Verona
N. Bombieri , Dipt. di Informatica, Universita di Verona
G. Pravadelli , Dipt. di Informatica, Universita di Verona
pp. 165

Efficient Testbench Code Synthesis for a Hardware Emulator System (Abstract)

I. Mavroidis , Microprocessor&Hardware Lab (MHL), Tech. Univ. of Crete
I. Papaefstathiou , Microprocessor&Hardware Lab (MHL), Tech. Univ. of Crete
pp. 166

Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions (Abstract)

I.G. Harris , Dept. of Comput. Sci., California Irvine Univ., CA
null Kiran Ramineni , Dept. of Comput. Sci., California Irvine Univ., CA
null Shireesh Verma , Dept. of Comput. Sci., California Irvine Univ., CA
pp. 168

Simulation Platform for UHF RFID (Abstract)

V. Derbek , Inst. of Tech. Informatics, Graz Univ. of Technol.
C. Steger , Inst. of Tech. Informatics, Graz Univ. of Technol.
R. Weiss , Inst. of Tech. Informatics, Graz Univ. of Technol.
pp. 171

Tool-support for the analysis of hybrid systems and models (Abstract)

M. Pister , Inst. fur Informatik, Technische Univ. Munchen
M. Tautschnig , Inst. fur Informatik, Technische Univ. Munchen
A. Bauer , Inst. fur Informatik, Technische Univ. Munchen
pp. 172

Automatic Model Generation for Black Box Real-Time Systems (Abstract)

null Thomas Huining Feng , Dept. of Electri. Eng.&Comput. Sci., California Univ., Berkeley, CA
null Wei Zheng , Dept. of Electri. Eng.&Comput. Sci., California Univ., Berkeley, CA
L. Wang , Dept. of Electri. Eng.&Comput. Sci., California Univ., Berkeley, CA
pp. 173

Routing Table Minimization for Irregular Mesh NoCs (Abstract)

R. Ginosar , Electr. Eng. Dept., Israel Inst. of Technol., Haifa
E. Bolotin , Electr. Eng. Dept., Israel Inst. of Technol., Haifa
I. Cidon , Electr. Eng. Dept., Israel Inst. of Technol., Haifa
A. Kolodny , Electr. Eng. Dept., Israel Inst. of Technol., Haifa
pp. 175

Testing in the Year 2020 (Abstract)

R. Galivanche , Intel Corp., Santa Clara, CA
pp. 178

Transaction Level Modelling of SCA Compliant Software Defined Radio Waveforms and Platforms PIM/PSM (Abstract)

G. Gailliard , Thales Commun. S.A., Colombes
E. Nicollet , Thales Commun. S.A., Colombes
M. Sarlotte , Thales Commun. S.A., Colombes
pp. 179

Event Driven Data Processing Architecture (Abstract)

null Ingemar Soderquist , Saab AB, Saab Avitronics, Linkoping
pp. 180

Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments (Abstract)

C. Dierker , IDA TU Braunschweig
B. Fiethe , IDA TU Braunschweig
H. Michalik , IDA TU Braunschweig
G. Zhou , IDA TU Braunschweig
B. Osterloh , IDA TU Braunschweig
pp. 181

Enabling certification for dynamic partial reconfiguration using a minimal flow (Abstract)

D. Merkenbreack , Lab. de Microelectronique, Univ. Catholique de Louvain, Louvain-la-Neuve
D. Galerin , Lab. de Microelectronique, Univ. Catholique de Louvain, Louvain-la-Neuve
B. Rousseau , Lab. de Microelectronique, Univ. Catholique de Louvain, Louvain-la-Neuve
P. Manet , Lab. de Microelectronique, Univ. Catholique de Louvain, Louvain-la-Neuve
J.-D. Legat , Lab. de Microelectronique, Univ. Catholique de Louvain, Louvain-la-Neuve
pp. 182

Identification of Process/Design Issues during 0.18?m Technology Qualification for Space Application (Abstract)

K. Sanchez , Electron. Anal. Dept., CNES, Toulouse
P. Perdu , Electron. Anal. Dept., CNES, Toulouse
J. Ferrigno , Electron. Anal. Dept., CNES, Toulouse
pp. 183

WAVSTAN: Waveform based Variational Static Timing Analysis (Abstract)

S.K. Tiwary , Cadence Berkeley Labs., CA
J.R. Phillips , Cadence Berkeley Labs., CA
pp. 185

Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times (Abstract)

J. Roychowdhury , Dept. of Electr.&Comput. Eng., Minnesota Univ.
S. Srivastava , Dept. of Electr.&Comput. Eng., Minnesota Univ.
pp. 186

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops (Abstract)

B. Lasbouygues , Design Dept., STMicroelectronics, Crolles
R. Wilson , Design Dept., STMicroelectronics, Crolles
pp. 187

Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models (Abstract)

D. Tadesse , Div. of Eng., Brown Univ., Providence, RI
D. Sheffield , Div. of Eng., Brown Univ., Providence, RI
pp. 188

Leightweight Middleware for Seamless HW-SW Interoperability, with Application to Wireless Sensor Networks (Abstract)

D. Villa , Dept. of Inf. Technol.&Syst., Sch. of Comput. Sci., Ciudad Real
J.C. Lopez , Dept. of Inf. Technol.&Syst., Sch. of Comput. Sci., Ciudad Real
J. Barba , Dept. of Inf. Technol.&Syst., Sch. of Comput. Sci., Ciudad Real
F. Rincon , Dept. of Inf. Technol.&Syst., Sch. of Comput. Sci., Ciudad Real
F.J. Villanueva , Dept. of Inf. Technol.&Syst., Sch. of Comput. Sci., Ciudad Real
F. Moya , Dept. of Inf. Technol.&Syst., Sch. of Comput. Sci., Ciudad Real
pp. 192

A Middleware-centric Design Flow for Networked Embedded Systems (Abstract)

D. Quaglia , Dept. of Comput. Sci., Verona Univ.
F. Fummi , Dept. of Comput. Sci., Verona Univ.
R. Pietrangeli , Dept. of Comput. Sci., Verona Univ.
G. Perbellini , Dept. of Comput. Sci., Verona Univ.
pp. 193

Dynamic Power Management under Uncertain Information (Abstract)

M. Pedram , Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA
null Hwisung Jung , Dept. of Electr. Eng., Southern California Univ., Los Angeles, CA
pp. 195

Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors (Abstract)

F. Catthoor , IMEC, Leuven
P. Raghavan , IMEC, Leuven
H. Corporaal , IMEC, Leuven
D. Verkest , IMEC, Leuven
A. Lambrechts , IMEC, Leuven
M. Jayapala , IMEC, Leuven
pp. 196

Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory (Abstract)

M. Choudhury , Rice Univ., Houston, TX
K. Ringgenberg , Rice Univ., Houston, TX
pp. 197
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