The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2006)
Munich, Germany
Mar. 6, 2006 to Mar. 10, 2006
ISBN: 3-9810801-1-4
TABLE OF CONTENTS
Papers

Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software (Abstract)

N.R. Potlapally , Dept. of Electrical Engineering, Princeton University, Princeton, NJ 08544, npotlapa@princeton.edu
pp. 7

An 830mW, 586kbps 1024-bit RSA chip design (Abstract)

null Chingwei Yeh , Nat. Chung-Cheng Univ., Chia-Yi, Taiwan
null En-Feng Hsu , Nat. Chung-Cheng Univ., Chia-Yi, Taiwan
null Kai-Wen Cheng , Nat. Chung-Cheng Univ., Chia-Yi, Taiwan
null Jinn-Shyan Wang , Nat. Chung-Cheng Univ., Chia-Yi, Taiwan
null Nai-Jen Chang , Nat. Chung-Cheng Univ., Chia-Yi, Taiwan
pp. 8

Platform Independent Debug Port Controller Architecture with Security Protection for Multi-Processor System-on-Chip ICs (Abstract)

D. Akselrod , Freescale Semiconductor Israel, Ltd., Herzlia, Israel, 32000; ECE Dept., McMaster University, Hamilt
pp. 9

Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time (Abstract)

F.-J. Veredas , Infineon Technol. AG, Munich, Germany
M. Scheppler , Infineon Technol. AG, Munich, Germany
pp. 10

Energy-Efficient FPGA Interconnect Design (Abstract)

M. Meijer , Philips Research Laboratories Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands, maurice.meijer@
pp. 11

A new approach to compress the configuration information of programmable devices (Abstract)

M. Martina , Dipt. di Elettronica, Politecnico di Torino, Italy
G. Masera , Dipt. di Elettronica, Politecnico di Torino, Italy
A. Molino , Dipt. di Elettronica, Politecnico di Torino, Italy
F. Vacca , Dipt. di Elettronica, Politecnico di Torino, Italy
pp. 12

Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys) (Abstract)

J. Davila , Dipt. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
A. de Torres , Dipt. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
J.M. Sanchez , Dipt. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
M. Sanchez-Elez , Dipt. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain
pp. 13

Application specific instruction processor based implementation of a GNSS receiver on an FPGA (Abstract)

G. Kappen , RWTH, Aachen Univ., Germany
T.G. Noll , RWTH, Aachen Univ., Germany
pp. 14

Synthesis of System Verilog Assertions (Abstract)

S. Das , Department of Computer Science & Engineering Indian Institute of Technology Kharagpur, India
pp. 16

Generating Finite State Machines from System C (Abstract)

A. Habibi , Department of Electrical and Computer Engineering Concordia University 1455 de Maisonneuve West Mont
pp. 17

Flexible Specification and Application of Rule-based Transformations in an Automotive Design Flow (Abstract)

J.-H. Oetjens , Robert Bosch GmbH AE/EIM3 Postfach 1342 72703 Reutlingen jan-hendrik. oetjens@de.bosch.com
pp. 18

A Mixed-Signal Verification Kit for Verification of Analogue-Digital Circuits (Abstract)

G. Bonfini , YOGITECH SpA, San Martino Ulmiano (Pisa), Italia -www. yogitech. com
pp. 19

A Complete and Fully Qualified Design Flow for Verification of Mixed-Signal SoC with Embedded Flash Memories (Abstract)

P. Daglio , STMicroelectronics?Agrate Brianza?Milan?Italy E-mail: pierluigi. daglio@st.com
pp. 20

Software-friendly HW/SW Co-Simulation: An Industrial Case Study (Abstract)

J. Noguera , Large-Format Technology Lab, Inkjet Commercial Division, Hewlett-Packard Sant Cugat del Valles, Barc
pp. 21

Modeling and simulation of mobile gateways interacting with wireless sensor networks (Abstract)

F. Fummi , Dipt. di Informatica, Universita di Verona, Italy
D. Quaglia , Dipt. di Informatica, Universita di Verona, Italy
pp. 22

A Hardware-Engine for Layer-2 classification in low-storage, ultra high bandwidth environments (Abstract)

V. Papaefstathiou , Foundation of Research & Technology Hellas (FORTH), Institute of Computer Science (ICS), Vassili
pp. 23

ASIP Architecture for Multi-Standard Wireless Terminals (Abstract)

D. Lo Iacono , Advanced System Technology STMicroelectronics, daniele. loiacono@st.com
pp. 24

Interconnection framework for high-throughput, flexible LDPC decoders (Abstract)

F. Quaglio , Dipt. di Elettronica, Politecnico di Torino, Italy
F. Vacca , Dipt. di Elettronica, Politecnico di Torino, Italy
C. Castellano , Dipt. di Elettronica, Politecnico di Torino, Italy
A. Tarable , Dipt. di Elettronica, Politecnico di Torino, Italy
G. Masera , Dipt. di Elettronica, Politecnico di Torino, Italy
pp. 25

Low cost LDPC decoder for DVB-S2 (Abstract)

J. Dielissen , Philips Research, High Tech Campus 5, 5656 AE Eindhoven, The Netherlands, E-mail: john. dielissen@ph
pp. 26

3dID: a low-power, low-cost hand motion capture device (Abstract)

M. Sama , DEIS, Bologna Univ., Italy
V. Pacella , DEIS, Bologna Univ., Italy
E. Farella , DEIS, Bologna Univ., Italy
L. Benini , DEIS, Bologna Univ., Italy
B. Ricco , DEIS, Bologna Univ., Italy
pp. 27

Networks on Chips for High-End Consumer-Electronics TV System Architectures (Abstract)

F. Steenhof , IC Lab, Philips Consumer Electronics, Eindhoven, The Netherlands frits.steenhof@philips.com
pp. 29

Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh (Abstract)

L. Bononi , Dipt. di Sci. dell'Informazion, Universita degli Studi di Bologna, Italy
N. Concer , Dipt. di Sci. dell'Informazion, Universita degli Studi di Bologna, Italy
pp. 30

GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links (Abstract)

G. Campobello , Dipartimento di Fisica della Materia e Tecnologie Fisiche Avanzate, University of Messina, Italy
pp. 31

Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application (Abstract)

F. Dumitrascu , TIMA Lab., Grenoble, France
I. Bacivarov , TIMA Lab., Grenoble, France
L. Pieralisi , TIMA Lab., Grenoble, France
M. Bonaciu , TIMA Lab., Grenoble, France
A.A. Jerraya , TIMA Lab., Grenoble, France
pp. 32

STAX: Statistical Crosstalk Target Set Compaction (Abstract)

S. Nazarian , University of Southern California, Dept. of Electrical Engineering
pp. 33

A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs (Abstract)

null Kuo-Hsing Cheng , Dept. of Electr. Eng., National Central Univ., Taoyuan, Taiwan
null Yu-Lung Lo , Dept. of Electr. Eng., National Central Univ., Taoyuan, Taiwan
pp. 34

How OEMs and Suppliers can face the Network Integration Challenges (Abstract)

K. Richter , Symtavision GmbH Hans-Sommer-Stra?e 66 38106 Braunschweig, Germany, richter@symtavision.com
pp. 35

On the verification of automotive protocols (Abstract)

G. Zarri , YOGITECH SpA, Pisa, Italy
F. Colucci , YOGITECH SpA, Pisa, Italy
F. Dupuis , YOGITECH SpA, Pisa, Italy
R. Mariani , YOGITECH SpA, Pisa, Italy
M. Pasquariello , YOGITECH SpA, Pisa, Italy
G. Risaliti , YOGITECH SpA, Pisa, Italy
pp. 37

FlexRay Transceiver in a 0.35?m CMOS High-Voltage Technology (Abstract)

F. Baronti , Dipartimento di Ingegneria dell?Informazione: Elettronica, Informatica, Telecomunicazioni, Uni
pp. 38

Space-efficient FPGA-accelerated collision detection for virtual prototyping (Abstract)

A. Raabe , Tech. Comput. Sci., Bonn Univ., Germany
S. Hochgurtel , Tech. Comput. Sci., Bonn Univ., Germany
J. Anlauf , Tech. Comput. Sci., Bonn Univ., Germany
pp. 39

Mixed-Signal Design of a Digital Input Power Amplifier for Automotive Audio Applications (Abstract)

S. Saponara , DIIEIT, University of Pisa, via Caruso, 56122, Pisa, Italy
pp. 40

Automatic SystemC design configuration for a faster evaluation of different partitioning alternatives (Abstract)

N. Bannow , Robert Bosch GmbH, Automotive Electron. Driver Assistance Syst., Germany
K. Haug , Robert Bosch GmbH, Automotive Electron. Driver Assistance Syst., Germany
pp. 41

Multi-Sensor Configurable Platform for Automotive Applications (Abstract)

L. Serafini , Kayser Italia Srl, via di Popogna, 501, 57128, Livorno, Italy; Dept. of Information Engineering, Uni
pp. 42

Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit (Abstract)

K. Karuri , Institute for Integrated Signal Processing Systems, RWTH Aachen University, Germany
pp. 43

A Novel FPGA-based Implementation of Time Adaptive Clustering for Logical Story Unit Segmentation (Abstract)

S. Arifin , Imperial College London Circuits and Systems Group Department of EEE, London (UK), sutjipto. arifin@
pp. 44

ASIP Design and Synthesis for Non Linear Filtering in Image Processing (Abstract)

L. Fanucci , DIIEIT, University of Pisa, via G. Caruso, I-56122, Pisa, Italy, l. fanucci@iet.unipi.it
pp. 45

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications (Abstract)

null Ju-Ho Sohn , Semiconductor System Laboratory, Department of EECS Korea Advanced Institute of Science and Technolo
pp. 48

Author Index (PDF)

pp. 49
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