The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2006)
Munich, Germany
Mar. 6, 2006 to Mar. 10, 2006
ISBN: 3-9810801-1-4
TABLE OF CONTENTS
Papers

[Cover] (PDF)

pp. 1

Table of contents (PDF)

pp. iv-xxiv

Foreword (PDF)

pp. 7

Tutorials (PDF)

pp. 9

Efficient Link Capacity and QoS Design for Network-on-Chip (Abstract)

Z. Guz , Electrical Engineering Department, Technion, Haifa, Israel, zguz@tx.technion.ac.il
pp. 11

Time Domain Model Order Reduction by Wavelet Collocation Method (Abstract)

Xuanzeng , ASIC & System State-key Laboratory, Microelectronics Department, Fudan University, Shanghai, Chi
pp. 13

Large power grid analysis using domain decomposition (Abstract)

Quming Zhou , Department of Electrical and Computer Engineering, Rice University, Houston, USA, quming@rice.edu
pp. 14

Analysis and Modeling of Power Grid Transmission lines (Abstract)

J. Balachandran , Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium, Phone: + 32 16 28870
pp. 15

A Logarithmic Full-Chip Thermal Analysis Algorithm Based on Multi-Layer Green's Function (Abstract)

Baohua Wang , Department of EECS University of Michigan, Ann Arbor, USA baohuaw@eecs.umich.edu
pp. 16

Large Scale RLC Circuit Analysis Using RLCG-MNA Formulation (Abstract)

Y. Tanji , Dept. of RlSE Kagawa University Takamatsu, Japan tanji@eng.kagawa-u.ac.jp
pp. 17

Soft Delay Error Analysis in Logic Circuits (Abstract)

B.S. Gill , Department of Electrical Engineering and Computer Science Case Western Reserve University, Cleveland
pp. 18

A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap (Abstract)

Tsu-Wei Tseng , Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Jin-Fu Li , Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Da-Ming Chang , Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
pp. 19

Analysis of the impact of bus implemented EDCs on on-chip SSN (Abstract)

D. Rossi , DEIS, Bologna Univ., Italy
C. Steiner , DEIS, Bologna Univ., Italy
C. Metra , DEIS, Bologna Univ., Italy
pp. 20

Berger Code-Based Concurrent Error Detection in Asynchronous Burst-Mode Machines (Abstract)

S. Almukhaizim , Electrical Engineering Department, Yale University New Haven, CT 06520, USA
pp. 22

Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications (Abstract)

F. Carbognani , Integrated Systems Laboratory, ETH Zurich, Switzerland, carbo@iis.ee.ethz.ch
pp. 23

A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes (Abstract)

Se-Joong Lee , Dept. of Electr. Eng.&Comput. Sci., Korea Adv. Inst. of Sci.&Technol., Daejeon, South Korea
Kwanho Kim , Dept. of Electr. Eng.&Comput. Sci., Korea Adv. Inst. of Sci.&Technol., Daejeon, South Korea
Hyejung Kim , Dept. of Electr. Eng.&Comput. Sci., Korea Adv. Inst. of Sci.&Technol., Daejeon, South Korea
Namjun Cho , Dept. of Electr. Eng.&Comput. Sci., Korea Adv. Inst. of Sci.&Technol., Daejeon, South Korea
Hoi-Jun Yoo , Dept. of Electr. Eng.&Comput. Sci., Korea Adv. Inst. of Sci.&Technol., Daejeon, South Korea
pp. 24

A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology (Abstract)

C. Niclass , Ecole Polytechnique Fédérale de Lausanne (EPFL) CH-1015 Lausanne, Switzerland
pp. 25

MATLAB/Simulink for Automotive Systems Design (Abstract)

J. Friedman , The MathWorks, Inc., Natick, MA, USA, Jon. Friedman@MathWorks.com
pp. 26

Model-Based Development of In-Vehicle Software (Abstract)

M. Conrad , DaimlerChrysler AG, Germany, mirko.conrad@daimlerchrysler.com
pp. 27

Model-Based Testing of Automotive Electronics (Abstract)

K. Lamberg , dSPACE GmbH, Paderborn, Germany, klamberg@dspace.de
pp. 28

Designing signal processing systems for FPGAs (Abstract)

J. Heighton , Xilinx, Weybridge, UK
pp. 29

From UML/SysML to Matlab/Simulink: Current State and Future Perspectives (Abstract)

Y. Vanderperren , EE Dept., ESAT-MICAS, Katholieke Universiteit Leuven, B-3001 Leuven, Belgium
pp. 30

An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles (Abstract)

E. Viaud , Laboratoire LIP6/ASIM Université Pierre et Marie Curie, emmanuel.viaud@lip6.fr
pp. 31

Exploiting TLM and Object Introspection for System-Level Simulation (Abstract)

G. Beltrame , Politecnico di Milano Milano, Italy, beltrame@elet.polimi.it
pp. 32

Efficient Assertion Based Verification using TLM (Abstract)

A. Habibi , Department of Electrical and Computer Engineering Concordia University 1455 de Maisonneuve West Mont
pp. 33

Constructing Portable Compiled Instruction-set Simulators-An ADL-driven Approach (Abstract)

J. D'Errico , Department of Electrical and Computer Engineering Boston University, Boston, MA 02215, USA, jderrico
pp. 34

A Methodology for Mapping Multiple Use-Cases onto Networks on Chips (Abstract)

S. Murali , CSL, Stanford University Stanford, USA smurali@stanford.edu
pp. 35

Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness (Abstract)

F. Angiolini , Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, 40136 Bologna, Italy
pp. 36

A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures (Abstract)

K. Srinivasan , Department of CSE, PO BOX 878809, Arizona State University, Tempe, AZ 85287-8809, Email: ksrinivasan
pp. 37

A dynamically reconfigurable packet-switched network-on-chip (Abstract)

T. Pionteck , Inst. of Comput. Eng., Lubeck Univ., Germany
C. Albrecht , Inst. of Comput. Eng., Lubeck Univ., Germany
R. Koch , Inst. of Comput. Eng., Lubeck Univ., Germany
pp. 38

Arbitrary Design of High Order Noise Transfer Function for A Novel Class of Reduced-Sample-Rate Sigma-Delta-Pipeline ADCs (Abstract)

V. Majidzadeh , IC Design Center, ECE Department, University of Tehran, Tehran, Iran, v. majidzadeh@ece.ut.ac.ir
pp. 39

Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation (Abstract)

M. Yavari , Dept. of Electr.&Comput. Eng., Tehran Univ., Iran
O. Shoaei , Dept. of Electr.&Comput. Eng., Tehran Univ., Iran
pp. 40

Systematic stability-analysis method for analog circuits (Abstract)

G. Vandersteen , IMEC vzw., Kapeldreef 75, B-3001 Leuven, Belgium; Vrije Universiteit Brussel, Dept. ELEC, Pleinlaan
pp. 41

ALAMO: An Improveds-Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits (Abstract)

Hui Zhang , Department of Electrical and Computer Engineering Stony Brook University Stony Brook, New York 11794
pp. 42

A Synthesis Tool for Power-Efficient Base-Band Filter Design (Abstract)

V. Giannini , Dip. di Ing. dell'Innovazione Universitàdi Lecce, Italy; IMEC Leuven, Belgium
pp. 43

An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits (Abstract)

R.R. Rao , Department of EECS, University of Michigan, Ann Arbor, MI 48109, rrrao@eecs.umich.edu
pp. 44

Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects (Abstract)

M. Omana , DEIS, University of Bologna, Viale Risorgimento 2, 40136 Bologna, Italy
pp. 45

Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods (Abstract)

U. Krautz , University of Kaiserslautern at the Electronic Design Automation Group, P. O. Box 3049, 67653 Kaiser
pp. 46

Soft-error classification and impact analysis on real-time operating systems (Abstract)

N. Ignat , Ecole Poly technique de Montreal, Que., Canada
B. Nicolescu , Ecole Poly technique de Montreal, Que., Canada
Y. Savaria , Ecole Poly technique de Montreal, Que., Canada
G. Nicolescu , Ecole Poly technique de Montreal, Que., Canada
pp. 47

40Gbps De-Layered Silicon Protocol Engine for TCP Record (Abstract)

H. Shrikumar , Ipsil Inc., Cambridge MA, shri@ipsil.com
pp. 48

Disclosing the LDPC code decoder design space (Abstract)

T. Brack , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany
F. Kienle , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany
N. Wehn , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany
pp. 50

Automating Processor Customisation: Optimised Memory Access and Resource Sharing (Abstract)

R. Dimond , Department of Computing, Imperial College, 180 Queens Gate, London. SW7 2RH, frgd00@doc.ic.ac.uk
pp. 51

Automatic Identification of Application-Specific Functional Units with Architecturally Visible Storage (Abstract)

P. Biswas , Center for Embedded Computer Systems, Donald Bren School of Information and Computer Science, Univer
pp. 52

Combining Algorithm Exploration with Instruction Set Design: A Case Study in Elliptic Curve Cryptography (Abstract)

J. Großschädl , Graz University of Technology, Institute for Applied Information Processing
P. Ienne , Ecole Polytechnique Fédérale de Lausanne, School of Computer and Communication Sciences
L. Pozzi , Ecole Polytechnique Fédérale de Lausanne, School of Computer and Communication Sciences
S. Tillich , Graz University of Technology, Institute for Applied Information Processing
A.K. Verma , Ecole Polytechnique Fédérale de Lausanne, School of Computer and Communication Sciences
pp. 53

Simultaneously Improving Code Size, Performance, and Energy in Embedded Processors (Abstract)

A. Zmily , Electrical Engineering Department, Stanford University, zmily@stanford.edu
pp. 54

Quantitative Analysis of Transaction Level Models for the AMBA Bus (Abstract)

G. Schirner , Center of Embedded Computer Systems, University of California, Irvine, hschirne@uci.edu
pp. 55

Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design (Abstract)

A. Viehl , FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany, viehl@fzi.de
pp. 57

Performance Evaluation for System-on-Chip Architectures using Trace-based Transaction Level Simulation (Abstract)

T. Wild , Technical University of Munich, Institute for Integrated Systems, Munich, Germany, http://www. lis.
pp. 58

Is"Network" the Next "Big Idea" in Design? (Abstract)

R. Marculescu , Dept. of Electrical and Computer Engineering, Carnegie Mellon University, radum@ece.cmu.edu
pp. 59

Efficient AC Analysis of Oscillators using Least-Squares Methods (Abstract)

Ting Mei , University of Minnesota, Twin Cities, USA, meixx004@umn.edu
pp. 61

Top-Down Heterogeneous Synthesis of Analog and Mixed-Signal Systems (Abstract)

E. Martens , Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT-MICAS, Kasteelpark Arenbe
pp. 63

Nonlinear Model Order Reduction Using Remainder Functions (Abstract)

J.A. Martinez , Department of Electrical and Computer Engineering, University of Pittsburgh
pp. 64

Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning (Abstract)

Zhiyuan He , Embedded Systems Laboratory (ESLAB), Linköping University, Sweden, zhihe@ida.liu.se
pp. 67

Power-Constrained Test Scheduling for Multi-Clock Domain SoCs (Abstract)

T. Yoneda , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit
pp. 68

Reuse-based test access and integrated test scheduling for network-on-chip (Abstract)

Z. Link , Dept. of Comput.&Electron. Eng., Nebraska Univ., Lincoln, NE, USA
pp. 69

A Design for Failure Analysis (DFFA) Technique to Ensure Incorruptible Signatures (Abstract)

S. Kundu , ECE Department University of Massachusetts, Amherst, kundu@ecs.umass.edu
pp. 70

Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits (Abstract)

P. Gupta , Dept. of Electrical Engineering Princeton University Princeton, NJ 08544, pgupta@ee.princeton.edu
pp. 71

Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams (Abstract)

A. Abdollahi , Department of Electrical Engineering University of Southern California, afshin@usc.edu
pp. 72

Priority Scheduling in Digital Microfluidics-Based Biochips (Abstract)

A.J. Ricketts , The Pennsylvania State University, University Park, PA, 16802, rickets@cse.psu.edu
pp. 74

A hybrid framework for design and analysis of fault-tolerant architectures (Abstract)

D. Bhaduri , Virginia Tech., Blacksburg, VA, USA
S. Shukla , Virginia Tech., Blacksburg, VA, USA
pp. 75

Optical Routing for 3D System-On-Package (Abstract)

J.R. Minz , School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA jrminz@ec
pp. 76

Distributed Loop Controller Architecture for Multi-threading in Uni-threaded VLIW Processors (Abstract)

P. Raghavan , IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium; KULeuven, Belgium ragha@imec.be
pp. 77

Compositional, efficient caches for a chip multi-processor (Abstract)

A.M. Molnos , Delft University of Technology Mekelweg 4, Delft, The Netherlands; Philips Research Laboratories HTC
pp. 78

Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors (Abstract)

S. Eyerman , ELIS, Ghent University, Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium, seyerman@elis.UGent.be
pp. 79

Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses (Abstract)

H. Vandierendonck , Ghent University Dept. ELIS /HiPEAC St.-Pietersnieuwstraat 41 B-9000 Gent, Belgium hans. vandierendo
pp. 80

A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures (Abstract)

Minwook Ahn , Center for SoC Design Technol., Seoul Nat. Univ., South Korea
J.W. Yoon , Center for SoC Design Technol., Seoul Nat. Univ., South Korea
Yunheung Paek , Center for SoC Design Technol., Seoul Nat. Univ., South Korea
pp. 81

Compiler-driven FPGA-area allocation for reconfigurable computing (Abstract)

E.M. Panainte , Dept. of Comput. Eng., Delft Univ. of Technol., Netherlands
K. Bertels , Dept. of Comput. Eng., Delft Univ. of Technol., Netherlands
S. Vassiliadis , Dept. of Comput. Eng., Delft Univ. of Technol., Netherlands
pp. 82

Temporal Partitioning for Image Processing Based on Time-Space Complexity in Reconfigurable Architectures (Abstract)

P.S.B. do Nascimento , Centro de Informática-CIN/UFPE-Caixa Postal 7851-Cidade Universitária Fo
pp. 83

System-level Scheduling on Instruction Cell Based Reconfigurable Systems (Abstract)

Ying Yi , School of Engineering and Electronics University of Edinburgh, Edinburgh, EH9 3JL Tel: (+ 44) 131 65
pp. 84

Systematic Methodology for Designing Reconfigurabl D S Modulator Topologies for Multimode Communication Systems (Abstract)

Ying Wei , Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY, 11794 yw
pp. 86

Double-Sampling Single-Loop Sigma-Delta Modulator Topologies for Broadband Applications (Abstract)

M. Yavari , IC Design Laboratory, ECE Department, University of Tehran, Tehran 14395-515, Iran E-mail: myavari@u
pp. 87

A 10-GHz 15-dB Four-Stage Distributed Amplifier in 0.18µm CMOS Process (Abstract)

K.K. Moez , Department of Electrical and Computer Engineering University of Waterloo Waterloo, Ontario, Canada
pp. 88

Bootstrapped full-swing CMOS driver for low supply voltage operation (Abstract)

J.C. Garcia , Dept. of Electron. Eng.&Autom., Univ. of Las Palmas de Gran Canaria, Spain
J.A. Montiel-Nelson , Dept. of Electron. Eng.&Autom., Univ. of Las Palmas de Gran Canaria, Spain
pp. 89

An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs (Abstract)

P. Bernardi , Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy, paolo.bernardi@polito.
pp. 90

Timing-reasoning-based delay fault diagnosis (Abstract)

Kai Yang , California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng , California Univ., Santa Barbara, CA, USA
pp. 91

Multiple-Fault Diagnosis Based on Single-Fault Activation and Single-Output Observation (Abstract)

Yung-Chieh Lin , Dept. of ECE, University of California, Santa Barbara Santa Barbara, CA 93106, USA, younglin@ece.ucs
pp. 92

Software-Based Self-Test of Processors under Power Constraints (Abstract)

Jun Zhou , Institute of Computer Architecture and Computer Engineering, University of Stuttgart Pfaffenwaldring
pp. 93

Diagnosis of Defects on Scan Enable and Clock Trees (Abstract)

Yu Huang , Mentor Graphics Corporation, Marlborough, MA, USA
pp. 94

Lock-Free Synchronization for Dynamic Embedded Real-Time Systems (Abstract)

Hyeonjoong Cho , ECE Dept., Virginia Tech Blacksburg, VA 24061, USA hjcho@vt.edu
pp. 95

Performance analysis of greedy shapers in real-time systems (Abstract)

E. Wandeler , Comput. Eng.&Networks Lab., Swiss Fed. Inst. of Technol., Switzerland
A. Maxiaguine , Comput. Eng.&Networks Lab., Swiss Fed. Inst. of Technol., Switzerland
L. Thiele , Comput. Eng.&Networks Lab., Swiss Fed. Inst. of Technol., Switzerland
pp. 96

Improved offset-analysis using multiple timing-references (Abstract)

R. Henia , Inst. of Comput.&Commun. Network Eng., Tech. Univ. of Braunschweig, Germany
R. Ernst , Inst. of Comput.&Commun. Network Eng., Tech. Univ. of Braunschweig, Germany
pp. 97

Procrastinating voltage scheduling with discrete frequency sets (Abstract)

Zhijian Lu , Dept. of Electr.&Comput. Eng., Virginia Univ., Charlottesville, VA, USA
Yan Zhang , Dept. of Electr.&Comput. Eng., Virginia Univ., Charlottesville, VA, USA
M. Stan , Dept. of Electr.&Comput. Eng., Virginia Univ., Charlottesville, VA, USA
K. Lach , Dept. of Electr.&Comput. Eng., Virginia Univ., Charlottesville, VA, USA
pp. 98

A SW performance estimation framework for early system-level-design using fine-grained instrumentation (Abstract)

T. Kempf , Inst. for Integrated Signal Process. Syst., Aachen Univ., Germany
K. Karuri , Inst. for Integrated Signal Process. Syst., Aachen Univ., Germany
S. Wallentowitz , Inst. for Integrated Signal Process. Syst., Aachen Univ., Germany
G. Ascheid , Inst. for Integrated Signal Process. Syst., Aachen Univ., Germany
R. Leupers , Inst. for Integrated Signal Process. Syst., Aachen Univ., Germany
H. Meyr , Inst. for Integrated Signal Process. Syst., Aachen Univ., Germany
pp. 100

A Unified System-Level Modeling and Simulation Environment for MPSoC design: MPEG-4 Decoder Case Study (Abstract)

V. Reyes , Institute for Applied Microelectronics, University of Las Palmas GC, Spain, vreyes@iuma.ulpgc.es
pp. 101

Task-accurate performance modeling in SystemC for real-time multi-processor architectures (Abstract)

M. Streubuhr , Erlangen-Nuremberg Univ., Erlangen, Germany
J. Falk , Erlangen-Nuremberg Univ., Erlangen, Germany
Ch. Haubelt , Erlangen-Nuremberg Univ., Erlangen, Germany
J. Teich , Erlangen-Nuremberg Univ., Erlangen, Germany
pp. 102

Application Specific NoC Design (Abstract)

L. Benini , DEIS Universitá di Bologna lbenini@deis.unibo.it
pp. 105

Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors (Abstract)

V. Viswanath , Computer Engineering Research Center University of Texas at Austin vinod@cerc.utexas.edu
pp. 106

Power Analysis of Mobile 3D Graphics (Abstract)

B. Mochocki , Dept of CSE, University of Notre Dame Notre Dame, IN bmochock@cse.nd.edu
pp. 107

Automatic Run-Time Selection of Power Policies for Operating Systems (Abstract)

N. Pettis , Electrical and Computer Engineering Purdue University, West Lafayette, Indiana, USA npettis@purdue.e
pp. 108

Energy Reduction by Workload Adaptation in a Multi-Process Environment (Abstract)

Changjiu Xian , Department of Computer Science Purdue University West Lafayette, IN 47907 cjx@cs.purdue.edu
pp. 109

Dynamic Bit-width Adaptation in DCT: Image Quality versus Computation Energy Trade-off (Abstract)

Jongsun Park , School of Electrical and Computer Engineering, Purdue University West Lafayette, IN 47907, USA jongs
pp. 110

Bus Stuttering : An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission (Abstract)

B.J. LaMeres , Design Validation Division Agilent Technologies Inc. Colorado Springs, CO 80907 USA brocklameres@agi
pp. 111

Non-Gaussian Statistical Interconnect Timing Analysis (Abstract)

S. Abbaspour , Department of Electrical Engineering, University of Southern California, sabbaspo@usc.edu
pp. 113

Cell Delay Analysis Based on Rate-of-Current Change (Abstract)

S. Nazarian , University of Southern California, Department of Electrical Engineering, Los Angeles, CA 90089, shah
pp. 114

AutoVision - flexible processor architecture for video-assisted driving (Abstract)

A. Herkersdorf , Inst. for Integrated Syst., Munich Univ. of Technol., Germany
W. Stechele , Inst. for Integrated Syst., Munich Univ. of Technol., Germany
pp. 119

Domain specific model driven design for automotive electronic control units (Abstract)

K.D. Mueller-Glaser , Inst. fur Technik der Informationsverarbeitung, Univ. Karlsruhe, Germany
pp. 120

Automotive Semi-Conductor Trend & Challenges (Abstract)

P. Leteinturier , Infineon Technologies AG; AIM MC ATV Balanstraße 73 D-81541 Munich patrick. leteinturier@Infine
pp. 122

A systematic IP and bus subsystem modeling for platform-based system design (Abstract)

Junhyung Um , CAE Center, Samsung Electron., South Korea
Woo-Cheol Kwon , CAE Center, Samsung Electron., South Korea
Sungpack Hong , CAE Center, Samsung Electron., South Korea
Young-Taek Kim , CAE Center, Samsung Electron., South Korea
Kyu-Myung Choi , CAE Center, Samsung Electron., South Korea
Jeong-Taek Kong , CAE Center, Samsung Electron., South Korea
Soo-Kwan Eo , CAE Center, Samsung Electron., South Korea
pp. 123

Heterogeneous Behavioral Hierarchy for System Level Designs (Abstract)

H.D. Patel , Virginia Polytechnic and State University hiren@vt.edu
pp. 124

Design with race-free hardware semantics (Abstract)

P. Schaumont , Dept. of Electr.&Comput. Eng., Virginia Tech, USA
S. Shukla , Dept. of Electr.&Comput. Eng., Virginia Tech, USA
pp. 125

Comfortable Modeling of Complex Reactive Systems (Abstract)

S. Prochnow , Real-Time and Embedded Systems Group, Dept. of Computer Science and Applied Mathematics Christian-Al
pp. 126

Faster Exploration of High Level Design Alternatives using UML for Better Partitions (Abstract)

W. Ahmed , Curtin University of Technology Sarawak Campus, Malaysia waseem@curtin.edu.my
pp. 127

A design flow for configurable embedded processors based on optimized instruction set extension synthesis (Abstract)

R. Leupers , Inst. for Integrated Signal Process. Syst., KWTH Aachen Univ., Germany
K. Karuri , Inst. for Integrated Signal Process. Syst., KWTH Aachen Univ., Germany
S. Kraemer , Inst. for Integrated Signal Process. Syst., KWTH Aachen Univ., Germany
M. Pandey , Inst. for Integrated Signal Process. Syst., KWTH Aachen Univ., Germany
pp. 128

Energy efficiency vs. programmability trade-off: architectures and design principles (Abstract)

J.P. Robelly , Dresden Silicon GmbH. Helmholtzstrasse 18, 01069 Dresden, Germany robelly@dresdensilicon.com
pp. 129

Automatic ADL-based Operand Isolation for Embedded Processors (Abstract)

A. Chattopadhyay , Integrated Signal Processing Systems RWTH Aachen University 52056 Aachen, Germany anupam@iss.rwth-aa
pp. 132

An analytical state dependent leakage power model for FPGAs (Abstract)

A. Kumar , Dept. of Electr.&Comput. Eng., Waterloo Univ., Ont., Canada
M. Anis , Dept. of Electr.&Comput. Eng., Waterloo Univ., Ont., Canada
pp. 134

Smart Bit-width Allocation for Low Power Optimization in a SystemC based ASIC Design Environment (Abstract)

A. Mallik , Electrical Engineering and Computer Science Northwestern University Evanston, IL 60208, USA arindam@
pp. 135

Value-Based Bit Ordering for Energy Optimization of On-Chip Global Signal Buses (Abstract)

K. Sundaresan , Dept. of Elect. & Comp. Eng., Michigan State University, East Lansing, MI 48824-1226, U.S.A. E-m
pp. 136

Modeling multiple input switching of CMOS gates in DSM technology using HDMR (Abstract)

J. Sridharan , Dept. of Electr.&Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
T. Chen , Dept. of Electr.&Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
pp. 137

A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits (Abstract)

O. Soffke , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
P. Zipf , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
T. Murgan , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 138

Using conjugate symmetries to enhance gate-level simulations (Abstract)

P.M. Maurer , Dept. of Comput. Sci., Baylor Univ., Waco, TX, USA
pp. 139

An Improved RF Loopback for Test Time Reduction (Abstract)

M. Negreiros , Escola de Engenharia - Departamento de Engenharia Elétrica - DELET negreiro@inf.ufrgs.br
pp. 141

Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking (Abstract)

C. Liu , Dept. of Comput.&Electron. Eng., Nebraska-Lincoln Univ., Omaha, NE, USA
pp. 142

Pseudorandom Functional BIST for Linear and Nonlinear MEMS (Abstract)

A. Dhayni , TIMA Laboratory Grenoble, France, achraf.dhayni@imag.fr
pp. 144

On-chip 8GHz Non-Periodic High-Swing Noise Detector (Abstract)

M. Abbas , Dept. of Electronic Engineering mohamed@silicon.u-tokyo.ac.jp
pp. 145

Battery-aware Code Partitioning for a Text to Speech System (Abstract)

A. Lahiri , Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, INDIA 721
pp. 146

Performance optimization for energy-aware adaptive checkpointing in embedded real-time systems (Abstract)

Zhongwei Li , Inf. Sci.&Technol. Coll., Xiamen Univ., China
Hong Chen , Inf. Sci.&Technol. Coll., Xiamen Univ., China
pp. 147

Software Annotations for Power Optimization on Mobile Devices (Abstract)

R. Cornea , Donald Bren School of Information and Computer Science University of California, Irvine, CA 92697-34
pp. 148

Dynamic partitioning of processing and memory resources in embedded MPSoC architectures (Abstract)

L. Xue , Dept. Comput. Sci.&Eng., Pennsylvania State Univ., USA
O. Ozturk , Dept. Comput. Sci.&Eng., Pennsylvania State Univ., USA
F. Li , Dept. Comput. Sci.&Eng., Pennsylvania State Univ., USA
M. Kandemir , Dept. Comput. Sci.&Eng., Pennsylvania State Univ., USA
pp. 149

Activity Clustering for Leakage Management in SPMs (Abstract)

M. Kandemir , Computer Science and Engineering Department Pennsylvania State University University Park, PA 16802,
pp. 150

Adaptive Data Placement in an Embedded Multiprocessor Thread Library (Abstract)

P. Stanley-Marbell , Dept of ECE, Carnegie Mellon University Pittsburgh, PA pstanley@ece.cmu.edu
pp. 151

COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC (Abstract)

S. Pasricha , Center for Embedded Computer Systems University of California, Irvine, CA 92697, USA, sudeep@cecs.uc
pp. 152

Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-offs for Distributed Embedded Systems (Abstract)

V. Izosimov , Computer and Information Science Dept., Linköping University, Sweden, viaiz@ida.liu.se
pp. 153

Communication architecture optimization: making the shortest path shorter in regular networks-on-chip (Abstract)

U.Y. Ogras , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Marculescu , Dept. of Electr.&Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 154

Cooptimization of Interface Hardware and Software for I/O Controllers (Abstract)

Kuan Jen Lin , Department of Electronic Engineering, Fu Jen Catholic University, Taiwan, kjlin@mails.fju.edu.tw
pp. 156

SoC-Fuelling the Hopes of the Mobile Industry (Abstract)

U. Lambrette , Booz Allen Hamilton
pp. 158

FPGA Architecture Characterization for System Level Performance Analysis (Abstract)

D. Densmore , University of California, Berkeley densmore@eecs.berkeley.edu
pp. 160

Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications (Abstract)

A. Bartzas , VLSI Design&Testing Center, Democritus Univ., Xanthi, Greece
S. Mamagkakis , VLSI Design&Testing Center, Democritus Univ., Xanthi, Greece
G. Pouiklis , VLSI Design&Testing Center, Democritus Univ., Xanthi, Greece
pp. 161

Customization of application specific heterogeneous multi-pipeline processors (Abstract)

S. Radhakrishnan , Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW, Australia
Hui Guo , Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW, Australia
S. Parameswaran , Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW, Australia
pp. 162

Impact of Bit-Width Specification on the Memory Hierarchy for a Real-Time Video Processing System (Abstract)

B. Thornberg , Mid-Sweden University, Sundsvall, SWEDEN, Email: benny.thornberg@miun.se
pp. 163

Efficient Factorization of DSP Transforms using Taylor Expansion Diagrams (Abstract)

J. Guillot , Laboratoire LESTER Université de Bretagne Sud BP 92116, 56321 Lorient Cedex, France, jeremie. g
pp. 164

Integrated Placement and Skew Optimization for Rotary Clocking (Abstract)

G. Venkataraman , Dept. of Electrical Engineering, Texas A& M University, College Station, TX 77843, ganesh@ee.tam
pp. 165

Associative Skew Clock Routing for Difficult Instances (Abstract)

Min-Seok Kim , Department of Electrical and Computer Engineering Texas A& M University College Station, TX 7784
pp. 166

Defect Tolerance of QCA Tiles (Abstract)

Jing Huang , Dept of Electrical and Computer Engineering Northeastern University, Boston, MA 02115, hjing@ece.neu
pp. 168

Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits (Abstract)

B.C. Paul , Toshiba America Research Inc., San Jose, CA 95131, USA; School of Electrical and Computer Engineerin
pp. 169

Novel designs for thermally robust coplanar crossing in QCA (Abstract)

S. Bhanja , Dept. of Electr. Eng., South Florida Univ., Tampa, FL, USA
pp. 170

Designing MRF based Error Correcting Circuits for Memory Elements (Abstract)

K. Nepal , Brown University, Division of Engineering, Providence, RI 02912
pp. 171

A Time-Triggered Ethernet (TTE) Switch (Abstract)

K. Steinhammer , Vienna University of Technology, Real-Time Systems Group, Treitlstr. 3/182-1, A-1040 Vienna, Austria
pp. 172

A Time Predictable Java Processor (Abstract)

M. Schoeberl , Institute of Computer Engineering, Vienna University of Technology, Austria, mschoebe@mail.tuwien.ac
pp. 173

Quantifier structure in search based procedures for QBFs (Abstract)

E. Giunchiglia , DIST, Universita di Genova Viale Causa, Italy
M. Narizzano , DIST, Universita di Genova Viale Causa, Italy
A. Tacchella , DIST, Universita di Genova Viale Causa, Italy
pp. 175

Strong Conflict Analysis for Propositional Satisfiability (Abstract)

HoonSang Jin , CAE center, System LSI division, Semicon. Business, Samsung Elec. CO., LTD
pp. 176

Equivalence verification of arithmetic datapaths with multiple word-length operands (Abstract)

N. Shekhar , Dept. of Electr.&Comput. Eng., Utah Univ., Salt Lake City, UT, USA
P. Kalla , Dept. of Electr.&Comput. Eng., Utah Univ., Salt Lake City, UT, USA
pp. 177

Thermal resilient bounded-skew clock tree optimization methodology (Abstract)

A. Chakraborty , DAUIN, Politecnico di Torino, Italy
P. Sithambaram , DAUIN, Politecnico di Torino, Italy
K. Duraisami , DAUIN, Politecnico di Torino, Italy
A. Macii , DAUIN, Politecnico di Torino, Italy
E. Macii , DAUIN, Politecnico di Torino, Italy
M. Poncino , DAUIN, Politecnico di Torino, Italy
pp. 179

Adaptive Chip-Package Thermal Analysis for Synthesis and Design (Abstract)

Yonghong Yang , ECE Department, Queen's University, Kingston, ON K7L 3N6, Canada, 4yy6@qlink.queensu.ca
pp. 181

On-chip Bus Thermal Analysis and Optimization (Abstract)

Feng Wang , The Pennsylvania State University, University Park, PA 16802, USA, fenwang@cse.psu.edu
pp. 182

A Control Theoretic Approach to Run-Time Energy Optimization of Pipelined Processing in MPSoCs (Abstract)

A. Alimonda , Dept. of Mathematics and Informatics, University of Cagliari, Cagliari, Italy
pp. 187

3D Floorplanning with Thermal Vias (Abstract)

Eric Wong , School of Electrical and Computer Engineering, Georgia Institute of Technology, ewong@ece.gatech.edu
pp. 188

Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization (Abstract)

T. Iizuka , Dept. of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan,
pp. 189

Lens Aberration Aware Timing-Driven Placement (Abstract)

A.B. Kahng , CSE and ECE Departments, University of California at San Diego, abk@cs.ucsd.edu
pp. 190

On test conditions for the detection of open defects (Abstract)

B. Kruseman , Philips Res. Labs., Eindhoven, Netherlands
M. Heiligers , Philips Res. Labs., Eindhoven, Netherlands
pp. 191

A compact model to identify delay faults due to crosstalk (Abstract)

J.L. Rossello , Electron. Technol. Group, Univ. de les Illes Balears, Palma de Mallorca, Spain
J. Segura , Electron. Technol. Group, Univ. de les Illes Balears, Palma de Mallorca, Spain
pp. 192

Generation of Broadside Transition Fault Test Sets that Detect Four-Way Bridging Faults (Abstract)

I. Pomeranz , School of Electrical & Computer Eng. Purdue University, W. Lafayette, IN 47907, U. S. A.
pp. 193

Extraction of Defect Density and Size Distributions from Wafer Sort Test Results (Abstract)

J.E. Nelson , Center for Silicon System Implementation, Department of Electrical and Computer Engineering, Carnegi
pp. 194

An integrated scratch-pad allocator for affine and non-affine code (Abstract)

S. Udayakumaran , Maryland Univ., College Park, MD, USA
R. Barua , Maryland Univ., College Park, MD, USA
pp. 196

Dynamic Scratch-Pad Memory Management for Irregular Array Access Patterns (Abstract)

G. Chen , Computer Science and Engineering Department, Pennsylvania State university, University Park, PA 1680
pp. 197

Dynamic Code Overlay of SDF-Modeled Programs on Low-end Embedded Systems (Abstract)

Hae-woo Park , School of EECS, Seoul National University, Seoul, Korea, starlet@iris.snu.ac.kr
pp. 200

optiMap: a tool for automated generation of NoC architectures using multi-port routers for FPGAs (Abstract)

B. Sethuraman , Dept. of ECECS, Cincinnati Univ., OH, USA
R. Vemuri , Dept. of ECECS, Cincinnati Univ., OH, USA
pp. 201

Hardware Efficient Architectures for Eigenvalue Computation (Abstract)

Yang Liu , Department of Electrical & Electronic Engineering, Imperial College London, yang.liu@imperial.ac
pp. 202

Memory centric thread synchronization on platform FPGAs (Abstract)

C. Kulkarni , Xilinx Inc San Jose, Ca Chidamber. Kulkarni@xilinx.com
pp. 203

A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead (Abstract)

Yang Qu , Technical Research Centre of Finland (VTT), Kaitoväylä1, FIN-90571 Oulu, Finland, Yang. Qu
pp. 204

Wireless Sensor Networks and Beyond (Abstract)

P.J.M. Havinga , Twente U., NL
pp. 205

Fast-prototyping Using the BTnode Platform (Abstract)

J. Beutel , Swiss Federal Institute of Technology (ETH) Zurich 8092 Zurich, Switzerland beutelgtik. ee. ethz. ch
pp. 207

Circuit-aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design (Abstract)

Qikai Chen , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA qikaichen@
pp. 208

Architectural and Technology Influence on the Optimal Total Power Consumption (Abstract)

S. Christian , IMT, University of Neuchâtel, Switzerland, christian. schuster@unine.ch
pp. 209

Exploiting Data-Dependent Slack Using Dynamic Multi-VDD to Minimize Energy Consumption in Datapath Circuits (Abstract)

K.R. Gandhi , Department of Electrical & Computer Engineering Michigan State University, East Lansing, MI 4882
pp. 211

On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL (Abstract)

N. Bombieri , Dipartimento di Informatica - Universit` a di Verona bombieri@sci.univr.it
pp. 212

Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation (Abstract)

F. Balarin , Cadence Berkeley Laboratories 1995 University Ave Suite 460 Berkeley CA 94704 felice@cadence.com
pp. 213

A Coverage Metric for the Validation of Interacting Processes (Abstract)

I.G. Harris , Department of Computer Science University of California Irvine Irvine, CA 92697 USA harris@ics.uci.e
pp. 214

New Methods and Coverage Metrics for Functional Verification (Abstract)

V. Jerinic , CONSOLEDA GmbH, Chemnitz Chemnitz University of Technology Germany, email: vje@infotech.tu-chemnitz.
pp. 215

Classification Trees for Random Tests and Functional Coverage (Abstract)

A. Krupp , Paderborn University/C-LAB, Paderborn, Germany
pp. 216

Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding (Abstract)

X. Kavousianos , Computer Science Dept., University of Ioannina, 45110 Ioannina, Greece, kabousia@cs.uoi.gr
pp. 217

Functional Constraints vs. Test Compression in Scan-Based Delay Testing (Abstract)

I. Polian , Graduate School of Information Science Nara Institute of Science and Technology, Japan; Institute fo
pp. 218

Concurrent Core Test for SOC Using Shared Test Set and Scan Chain Disable (Abstract)

Gang Zeng , Graduate School of Science and Technology, Chiba University, Japan E-mail: sogo@graduate.chiba-u.jp
pp. 219

Efficient Unknown Blocking Using LFSR Reseeding (Abstract)

Seongmoon Wang , NEC Laboratories America, 4 Independence Way, Princeton, NJ 08540, USA Email: swang@nec-labs.com
pp. 220

Online energy-aware I/O device scheduling for hard real-time systems (Abstract)

Hui Cheng , Dept. of Comput. Sci.&Eng., Nebraska Univ., Lincoln, NE, USA
S. Goddard , Dept. of Comput. Sci.&Eng., Nebraska Univ., Lincoln, NE, USA
pp. 222

Multiprocessor Synthesis for Periodic Hard Real-Time Tasks under a Given Energy Constraint (Abstract)

Heng-Ruey Hsu , Department of Computer Science and Information Engineering Graduate Institute of Networking and Mult
pp. 223

Scheduling under Resource Constraints using Dis-Equations (Abstract)

H. Cherroun , LIP, ENS-Lyon, 46, Allée d'Italie, 69007 Lyon, France Hadda.Cherroun@ens-lyon.fr
pp. 224

Scalable Performance-Energy Trade-off Exploration of Embedded Real-Time Systems on Multiprocessor Platforms (Abstract)

Zhe Ma , IMEC Kapeldreef 75, B-3000 Leuven, Belgium; Ph.D. student of ESAT, K. U. Leuven, Belgium mazhe@imec.
pp. 225

Building a Better Boolean Matcher and Symmetry Detector (Abstract)

D. Chai , University of California at Berkeley, CA, USA
pp. 226

Optimizing sequential cycles through Shannon decomposition and retiming (Abstract)

C. Soviani , Dept. of Comput. Sci., Columbia Univ., USA
O. Tardieu , Dept. of Comput. Sci., Columbia Univ., USA
S.A. Edwards , Dept. of Comput. Sci., Columbia Univ., USA
pp. 227

Efficient Incremental Clock Latency Scheduling for Large Circuits (Abstract)

C. Albrecht , Cadence Berkeley Labs, Berkeley, CA, USA
pp. 228

Analyzing Timing Uncertainty in Mesh-based Clock Architectures (Abstract)

S.M. Reddy , Fujitsu Laboratories of America, Inc. California, USA subodh@fla.fujitsu.com
pp. 229

Platform-Based Design of Wireless Sensor Networks for Industrial Applications (Abstract)

A. Bonivento , University of California at Berkeley, e-mail: alvise@eecs.berkeley.edu
pp. 230

An environment for controlled experiments with in-house sensor networks (Abstract)

V. Handziski , TU Berlin, Germany
A. Koepke , TU Berlin, Germany
A. Willig , TU Berlin, Germany
A. Wolisz , TU Berlin, Germany
pp. 231

Hogthrob: towards a sensor network infrastructure for sow monitoring (wireless sensor network special day) (PDF)

P. Bonnet , Copenhagen Univ., Denmark
M. Leopold , Copenhagen Univ., Denmark
K. Madsen , Copenhagen Univ., Denmark
pp. 232

Ultra-Efficient (Embedded) SOC Architectures based on Probabilistic CMOS (PCMOS) Technology (Abstract)

L.N. Chakrapani , Center for Research on Embedded Systems and Technology Georgia Institute of Technology Atlanta, Geor
pp. 233

Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel Distributed Power Supply Network (Abstract)

M. Budnik , Purdue University School of Electrical and Computer Engineering 465 Northwestern Avenue West Lafayet
pp. 234

An Ultra Low-Power TLB Design (Abstract)

Yen-Jen Chang , Department of Computer Science, National ChungHsing University, Taiwan ychang@cs.nchu.edu.tw
pp. 235

Determining the Optimal Timeout Values for a Power-Managed System based on the Theory of Markovian Processes: Offline and Online Algorithms (Abstract)

Peng Rong , Dept. of Electrical Engineering University of Southern California Los Angeles, CA 90089 e-mail : pro
pp. 236

A Formal Model and Efficient Traversal Algorithm for Generating Testbenches for Verification of IEEE Standard Floating Point Division (Abstract)

D.W. Matula , Department of Computer Science and Engineering Southern Methodist University Dallas, TX 75275 email
pp. 237

An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration (Abstract)

F. Angiolini , Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, 40136 Bologna, Italy
pp. 239

Parallel co-simulation using virtual synchronization with redundant host execution (Abstract)

D. Kim , Dept. of Comput. Sci.&Eng., California Univ., San Diego, CA, USA
pp. 240

Minimizing Test Power in SRAM through Reduction of Pre-charge Activity (Abstract)

L. Dilillo , University of Southampton - Electronics and Computer Science (ECS) Department Highfield, Southampton
pp. 242

Efficient On-line Interconnect Testing in FPGAs with Provable Detectability for Multiple Faults (Abstract)

V. Suthar , Dept. of ECE, University of Illinois-Chicago vsuthar@ece.uic.edu
pp. 243

A concurrent testing method for NoC switches (Abstract)

M. Hosseinabady , Electr.&Comput. Eng., Tehran Univ., Iran
A. Banaiyan , Electr.&Comput. Eng., Tehran Univ., Iran
M.N. Bojnordi , Electr.&Comput. Eng., Tehran Univ., Iran
Z. Navabi , Electr.&Comput. Eng., Tehran Univ., Iran
pp. 244

A secure Scan Design Methodology (Abstract)

D. Hely , Smartcard Division, ST Microelectronics Rousset, France; LIRMM/UMR 5506 CNRS, UniversitéMontpel
pp. 245

RAS-NANO: A Reliability-Aware Synthesis Framework for Reconfigurable Nanofabrics (Abstract)

Chen He , Department of Electrical and Computer Engineering The University of Texas at Austin; Freescale Semic
pp. 246

Layout Driven Data Communication Optimization for High Level Synthesis (Abstract)

R. Kastner , Department of Electrical & Computer Engineering University of California, Santa Barbara kastner@
pp. 247

Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits (Abstract)

S.P. Mohanty , Comput. Sci.&Eng., North Texas Univ., Denton, TX, USA
Ramakrishna Velagapudi , Comput. Sci.&Eng., North Texas Univ., Denton, TX, USA
pp. 248

High Level Synthesis of Higher Order Continuous Time State Variable Filters with Minimum Sensitivity and Hardware Count (Abstract)

S. Pandit , Indian Institute of Technology, Kharagpur, India, E-Mail: soumya_pandit@ieee.org
pp. 250

Distance-Guided Hybrid Verification with GUIDO (Abstract)

S. Shyam , Advanced Computer Architecture Lab University of Michigan, Ann Arbor, MI 48109 smithash@umich.edu
pp. 252

What lies between Design Intent Coverage and Model Checking? (Abstract)

S. Das , Department of Computer Science & Engineering Indian Institute of Technology Kharagpur, India.
pp. 253

On the Numerical Verification of Probabilistic Rewriting Systems (Abstract)

J.B. Hassen , Department of Electrical and Computer Engineering Concordia University Montreal, Quebec, Canada, jou
pp. 254

Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks (Abstract)

G. Fey , Institute of Computer Science University of Bremen, 28359 Bremen, Germany, fey@informatik.uni-bremen
pp. 255

Formal Verification of SystemC Designs Using a Petri-Net Based Representation (Abstract)

D. Karlsson , Department of Computer and Information Science, Linköpings universitet, Sweden danka@ida.liu.se
pp. 257

Monolithic Verification of Deep Pipelines with Collapsed Flushing (Abstract)

R. Kane , College of Computing Georgia Tech, Atlanta, GA 30318 kroma@cc.gatech.edu
pp. 258

Functional Test Generation using Property Decompositions for Validation of Pipelined Processors (Abstract)

Heon-Mo Koo , Department of Computer and Information Science and Engineering University of Florida, Gainesville, F
pp. 259

Proven correct monitors from PSL specifications (Abstract)

K. Morin-Allory , Tima Laboratory, 46 avenue Félix Viallet 38031 Grenoble Cedex, France katell. morin@imag.fr
pp. 260

Space of DRAM Fault Models and Corresponding Testing (Abstract)

Z. Al-Ars , Delft University of Technology, Faculty of EE, Mathematics and CS Lab of Computer Engineering, Mekel
pp. 261

Automatic March Tests Generations for Static Linked Faults in SRAMs (Abstract)

A. Benso , Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy E-mail benso@polito.it
pp. 262

Test Compaction for Transition Faults under Transparent-Scan (Abstract)

I. Pomeranz , School of Electrical & Computer Eng. Purdue University W. Lafayette, IN 47907, U. S. A.
pp. 263

Vulnerability Analysis of L2 Cache Elements to Single Event Upsets (Abstract)

H. Asadi , Dept. of Electrical & Computer Engineering, Northeastern University 360 Huntington Ave., Boston
pp. 265

Area-Efficient Error Protection for Caches (Abstract)

Soontae Kim , Department of Computer Science and Engineering University of South Florida, FL 33620 sookim@cse.usf.
pp. 266

Microarchitectural Floorplanning Under Performance and Thermal Tradeoff (Abstract)

M. Healy , School of Electrical and Computer Engineering Georgia Institute of Technology mbhealy@ece.gatech.edu
pp. 267

Optimizing High Speed Arithmetic Circuits Using Three-Term Extraction (Abstract)

A. Hosangadi , University of California, Santa Barbara anup@ece.ucsb.edu
pp. 268

Efficient Minimization of Fully Testable 2-SPP Networks (Abstract)

A. Bernasconi , Department of Computer Science University of Pisa, Italy annab@di.unipi.it
pp. 269

Pre-synthesis Optimization of Multiplications to Improve Circuit Performance (Abstract)

R. Ruiz-Sautua , Dpto. Arquitectura de Computadores y Automática Universidad Complutense de Madrid rsautua@fdi.u
pp. 270

Crosstalk-aware Domino Logic Synthesis (Abstract)

Yi-Yu Liu , Dept. of Computer Science, Tsing Hua University, Hsinchu, Taiwan, R. O. C.
pp. 271

TRAIN: A Virtual Transaction Layer Architecture for TLM-based HW/SW Codesign of Synthesizable MPSoC (Abstract)

W. Klingauf , Technical University of Braunschweig, Dept. E. I. S., Muihlenpfordtstr. 23, D-38106 Braunschweig, Ge
pp. 272

Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications (Abstract)

T. Arpinen , Tampere University of Technology, Institute of Digital and Computer Systems, Korkeakoulunkatu 1, FI-
pp. 273

ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding (Abstract)

O. Muller , Electronics Department, ENST Bretagne, Technopôle Brest Iroise, 29238 Brest, France, olivier. m
pp. 274

Author Index (PDF)

pp. 275
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