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Design, Automation & Test in Europe Conference & Exhibition (2006)
Munich, Germany
Mar. 6, 2006 to Mar. 10, 2006
ISBN: 3-9810801-1-4
pp: 106
V. Viswanath , Computer Engineering Research Center University of Texas at Austin
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation. Our technique automatically annotates existing RTL code to optimize the circuit for lowering power dissipated by switching activity. Our technique can be applied at the architectural level as well, achieving similar power gains. We demonstrate our technique on architectural and RTL models of a 32-bit OpenRISC processor (OR1200), showing power gains for the SPEC2000 benchmarks.
V. Viswanath, J.A. Abraham, W.A. Hunt, "Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors", Design, Automation & Test in Europe Conference & Exhibition, vol. 01, no. , pp. 106, 2006, doi:10.1109/DATE.2006.243858
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