The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2005)
Munich, Germany
Mar. 7, 2005 to Mar. 11, 2005
ISSN: 1530-1591
ISBN: 0-7695-2288-2
TABLE OF CONTENTS
6A: High-Level Verification

Effective Lower Bounding Techniques for Pseudo-Boolean Optimization (Abstract)

Jo? Marques-Silva , IST/INESC-ID, Technical University of Lisbon, Portugal
Vasco M. Manquinho , IST/INESC-ID, Technical University of Lisbon, Portugal
pp. 660-665

Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver (Abstract)

K.-T. Cheng , University of California - Santa Barbara
G. Parthasarathy , University of California - Santa Barbara
M. K. Iyer , University of California - Santa Barbara
pp. 666-671

A Faster Counterexample Minimization Algorithm Based on Refutation Analysis (Abstract)

ShengYu Shen , National University of Defence Technology
SiKun Li , National University of Defence Technology
Ying Qin , National University of Defence Technology
pp. 672-677

Functional Coverage Driven Test Generation for Validation of Pipelined Processors (Abstract)

Prabhat Mishra , University of Florida, Gainesville, FL
Nikil Dutt , University of California, Irvine, CA
pp. 678-683
Interactive Presentations

Pueblo: A Modern Pseudo-Boolean SAT Solver (PDF)

Karem A. Sakallah , University of Michigan, Ann Arbor
Hossein M. Sheini , University of Michigan, Ann Arbor
pp. 684-685

Space-Efficient Bounded Model Checking (PDF)

Jacob Katz , Intel Corporation, Haifa
Ziyad Hanna , Intel Corporation, Haifa
Nachum Dershowitz , Tel Aviv University, Israel
pp. 686-687

Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking (PDF)

Sergio Nocco , Politecnico di Torino, Italy
Stefano Quer , Politecnico di Torino, Italy
Gianpiero Cabodi , Politecnico di Torino, Italy
Marco Crivellari , Politecnico di Torino, Italy
pp. 688-689
6B: System Modelling with UML

A Model-Based Approach for Executable Specifications on Reconfigurable Hardware (Abstract)

Tim Schattkowsky , University of Paderborn/C-LAB, Germany
Achim Rettberg , University of Paderborn/C-LAB, Germany
Wolfgang Mueller , University of Paderborn/C-LAB, Germany
pp. 692-697

The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application (Abstract)

Yvon Savaria , ?cole Polytechnique de Montr?al
El Mostapha Aboulhamid , Universit? de Montr?al
Alexandre Chureau , ?cole Polytechnique de Montr?al
pp. 698-703

A SoC Design Methodology Involving a UML 2.0 Profile for SystemC (Abstract)

S. Bocchio , STMicroelectronics AST (Italy)
P. Scandurra , Universit? di Catania (Italy)
A. Rosti , STMicroelectronics AST (Italy)
E. Riccobene , Universit? di Catania (Italy)
pp. 704-709

UML 2.0 Profile for Embedded System Design (Abstract)

Marko H?nnik?inen , Tampere University of Technology, Finland
Klaus Kronl? , Nokia Research Center, Finland
Timo D. H?m?l?inen , Tampere University of Technology, Finland
Jouni Riihim?ki , Tampere University of Technology, Finland
Petri Kukkala , Tampere University of Technology, Finland
pp. 710-715
Interactive Presentations

UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design (PDF)

Yves Vanderperren , Katholieke Universiteit Leuven, Belgium
Wim Dehaene , Katholieke Universiteit Leuven, Belgium
pp. 716-717

Design Refinement for Efficient Cluste ing of Objects in Embedded Systems (PDF)

Waseem Ahmed , Curtin University of Technology, Sarawak Campus, Malaysia
Doug Myers , Curtin University of Technology, Bentley Campus, Western Australia
pp. 718-719
6C: Hot Topic - Challenges in Embedded Memory Design and Test

Challenges in Embedded Memory Design and Test (Abstract)

Yervant Zorian , Virage Logic, Fremont, CA, USA
Doris Keitel-Schulz , Infineon Technologies, Munich, Germany
Betty Prince , Memory Strategies International, Leander, TX, USA
Erik Jan Marinissen , Philips Research Labs, The Netherlands
pp. 722-727
6E: Parallel and Multithreaded Processor Architectures

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures (Abstract)

M. Balakrishnan , Indian Institute of Technology Delhi, India
Anshul Kumar , Indian Institute of Technology Delhi, India
Anup Gangwar , Indian Institute of Technology Delhi, India
Preeti R. Panda , Indian Institute of Technology Delhi, India
pp. 730-735

Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture (Abstract)

Poggiali Antonio , University of Bologna, DEIS, Italy
Paul Marchal , IMEC vzw, Belgium
Poletti Francesco , University of Bologna, DEIS, Italy
pp. 736-741

Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler (Abstract)

Andr? C. N?cul , University of California, Irvine
Tony Givargis , University of California, Irvine
pp. 742-747
Interactive Presentation

Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications (PDF)

Mariagiovanna Sami , Politecnico di Milano
Daniele Bagni , STMicroelectronics
Domenico Barretta , Politecnico di Milano
William Fornaciari , Politecnico di Milano
pp. 748-749
6F: Very Deep Submicron Simulation

An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation (Abstract)

Zhao Li , University of Washington, Seattle, WA
C.-J. Richard Shi , University of Washington, Seattle, WA
pp. 752-757

Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design (Abstract)

Bharat Sukhwani , University of Arizona, Tucson
Janet M. Wang , University of Arizona, Tucson
Uday Padmanabhan , University of Arizona, Tucson
pp. 758-763

Statistical Timing Analysis using Levelized Covariance Propagation (Abstract)

Bipul C. Paul , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Kunhyuk Kang , Purdue University, West Lafayette, IN
pp. 764-769
Interactive Presentation

Modeling and Propagation of Noisy Waveforms in Static Timing Analysis (PDF)

Tao Lin , Magma Design Automation, Santa Clara, CA
Emre Tuncer , Magma Design Automation, Santa Clara, CA
Amir H. Ajami , Magma Design Automation, Santa Clara, CA
Massoud Pedram , University of Southern California, Los Angeles
Shahin Nazarian , University of Southern California, Los Angeles
pp. 776-777
6G: SoC Prototyping and Simulation

A Network Traffic Generator Model for Fast Network-on-Chip Simulation (Abstract)

Federico Angiolini , University of Bologna, Italy
Shankar Mahadevan , Technical University of Denmark (DTU)
Jens Spars? , Technical University of Denmark (DTU)
Rasmus Gr?ndahl Olsen , Technical University of Denmark (DTU)
Jan Madsen , Technical University of Denmark (DTU)
Michael Storgaard , Technical University of Denmark (DTU)
pp. 780-785

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation (Abstract)

Mehrdad Reshadi , University of California Irvine, CA
Nikil Dutt , University of California Irvine, CA
pp. 786-791

Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs (Abstract)

Wolfgang Rosenstiel , FZI Forschungszentrum Informatik, Germany; Universit?t T?bingen, Germany
Oliver Bringmann , FZI Forschungszentrum Informatik, Germany
J?rgen Schnerr , FZI Forschungszentrum Informatik, Germany
pp. 792-797

Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation (Abstract)

Mirko Loghi , Universit? di Verona, Italy
Massimo Poncino , Politecnico di Torino, Italy
Franco Fummi , Universit? di Verona, Italy
Marco Monguzzi , SITEK S.p.A., Italy
Stefano Martini , Universit? di Verona, Italy
Giovanni Perbellini , Universit? di Verona, Italy
pp. 798-803
Interactive Presentation

Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip (PDF)

M. Monchiero , Politecnico di Milano, Italy
G. Palermo , Politecnico di Milano, Italy
O. Villa , UCLA
pp. 804-805
7A: Memory Optimisation and Clocking for SoC

FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations (Abstract)

Nikil Dutt , University of California, Irvine
Ilya Issenin , University of California, Irvine
pp. 808-813

Nonuniform Banking for Reducing Memory Energy Consumption (Abstract)

Mahmut Kandemir , The Pennsylvania State University, University Park
Ozcan Ozturk , The Pennsylvania State University, University Park
pp. 814-819

Systematic Analysis of Active Clock Deskewing Systems Using Control Theory (Abstract)

Peter M. Young , Colorado State University, Fort Collins
Vinil Varghese , Colorado State University, Fort Collins
Tom Chen , Colorado State University, Fort Collins
pp. 820-825
Interactive Presentations

Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip (PDF)

Sankalp S. Kallakuri , Stony Brook University, NY
Alex Doboli , Stony Brook University, NY
Eugene A. Feinberg , Stony Brook University, NY
pp. 826-827

Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory (PDF)

Ling Ming , Southeast University, Nanjing, China
Pu Hanlai , Southeast University, Nanjing, China
Jin Jing , Southeast University, Nanjing, China
pp. 828-829
7B: Embedded Tutorial - UML for System-on-Chip Design: Current Applications and Future Perspectives

UML 2.0 - Overview and Perspectives in SoC Design (PDF)

Tim Schattkowsky , University of Paderborn/C-LAB, Germany
pp. 832-833

Why Systems-on-Chip Needs More UML like a Hole in the Head (PDF)

Stephen J. Mellor , Accelerated Technologies, Tucson AZ, USA
John R. Wolfe , Accelerated Technologies, Tucson AZ, USA
Campbell McCausland , Accelerated Technologies, Tucson AZ, USA
pp. 834-835

Integrating UML into SoC Design Process (PDF)

Ryosuke Oishi , Fujitsu Laboratories LTD., Japan
Qiang Zhu , Fujitsu Laboratories LTD., Japan
Tsuneo Nakata , Fujitsu Laboratories LTD., Japan
Takashi Hasegawa , Fujitsu Limited, Japan
pp. 836-837
7C: Test Power Reduction and Diagnosis

Rapid Generation of Thermal-Safe Test Schedules (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
Bashir Al-Hashimi , University of Southampton, UK
Paul Rosinger , University of Southampton, UK
pp. 840-845

Simultaneous Reduction of Dynamic and Static Power in Scan Structures (Abstract)

Mohammad Hosseinabady , University of Tehran, Iran
Ali Afzali-Kusha , University of Tehran, Iran
Javid Jaffari , University of Tehran, Iran
Shervin Sharifi , University of Tehran, Iran
Zainalabedin Navabi , University of Tehran, Iran
pp. 846-851

A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs (Abstract)

Andr? Ivanov , University of British Columbia, Vancouver, Canada
Yuejian Wu , Nortel Networks, Ontario, Canada
Baosheng Wang , University of British Columbia, Vancouver, Canada
pp. 852-857
Interactive Presentations

New Schemes for Self-Testing RAM (PDF)

A. Labunetz , Technical University of Moldova
D. Bodean , Technical University of Moldova
Gh. Bodean , Technical University of Moldova
pp. 858-859

At-Speed Logic BIST for IP Cores (PDF)

J. Cho , SynTest Korea, Ltd.
P. Hsu , SynTest Technologies, Inc., Taiwan
B. Cheon , Samsung Electronics, Co.
H. Chao , SynTest Technologies, Inc., Taiwan
E. Lee , Samsung Electronics, Co.
L.-T. Wang , SynTest Technologies, Inc.
X. Wen , Kyushu Institute of Technology
S. Wu , SynTest Technologies, Inc.
J. Park , SynTest Korea, Ltd.
pp. 860-861
7E: Scheduling and Memory Optimisation for Multiprocessor Embedded Systems

Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems (Abstract)

Viacheslav Izosimov , Link?ping University, Sweden
Zebo Peng , Link?ping University, Sweden
Paul Pop , Link?ping University, Sweden
Petru Eles , Link?ping University, Sweden
pp. 864-869

Locality-Aware Process Scheduling for Embedded MPSoCs (Abstract)

Mahmut Kandemir , The Pennsylvania State University
Guilin Chen , The Pennsylvania State University
pp. 870-875

A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms (Abstract)

Malte Doerper , Aachen University of Technology, Germany
Bart Vanthournout , CoWare, Inc., Leuven, Belgium
Torsten Kempf , Aachen University of Technology, Germany
R. Leupers , Aachen University of Technology, Germany
Tim Kogel , CoWare, Inc., Leuven, Belgium
G. Ascheid , Aachen University of Technology, Germany
H. Meyr , Aachen University of Technology, Germany
pp. 876-881

Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems (Abstract)

H. Saputra , The Pennsylvania State University
I. Kolcu , UMIST, UK
O. Ozturk , The Pennsylvania State University
M. Kandemir , The Pennsylvania State University
pp. 882-887

System Synthesis for Networks of Programmable Blocks (Abstract)

Harry Hsieh , University of California, Riverside
Ryan Mannion , University of California, Riverside
Susan Cotterell , University of California, Riverside
Frank Vahid , University of California, Riverside; UC Irvine
pp. 888-893
Interactive Presentations

Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks (PDF)

J? Teich , University of Erlangen-Nuremberg, Germany
Christian Haubelt , University of Erlangen-Nuremberg, Germany
Thilo Streichert , University of Erlangen-Nuremberg, Germany
pp. 894-895

Synchronization Processor Synthesis for Latency Insensitive Systems (PDF)

Pierre Bomel , LESTER, Universit? de Bretagne Sud, Lorient, France
Emmanuel Boutillon , LESTER, Universit? de Bretagne Sud, Lorient, France
Eric Martin , LESTER, Universit? de Bretagne Sud, Lorient, France
pp. 896-897

Thermal-Aware Task Allocation and Scheduling for Embedded Systems (PDF)

M. Kandemir , The Pennsylvania State University, University Park
W-L. Hung , The Pennsylvania State University, University Park
N. Vijaykrishnan , The Pennsylvania State University, University Park
Y. Xie , The Pennsylvania State University, University Park
M. J. Irwin , The Pennsylvania State University, University Park
pp. 898-899
7F: Layout Issues

An Improved Multi-Level Framework for Force-Directed Placement (Abstract)

Andrew Kennings , University of Waterloo, Canada
Kristofer Vorwerk , University of Waterloo, Canada
pp. 902-907

Bright-Field AAPSM Conflict Detection and Correction (Abstract)

A. Kahng , University of California, San Diego
X. Xu , University of California, San Diego
A. Zelikovsky , Georgia State University
S. Sinha , Synopsys
C. Chiang , Synopsys
pp. 908-913

Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules (Abstract)

Wim Dehaene , Dept. ESAT-MICAS, KUL, Leuven, Belgium
Hua Wang , IMEC, Leuven, Belgium
Francky Catthoor , IMEC, Leuven, Belgium
Miguel Miranda , IMEC, Leuven, Belgium
Karen Maex , IMEC, Leuven, Belgium
pp. 914-919
Interactive Presentations

TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform (PDF)

Hugo Cl?ment , University Paris VI, LIP6/ASIM laboratory
Jean-Paul Chaput , University Paris VI, LIP6/ASIM laboratory
R?my Escassut , Silvaco
Christian Masson , University Paris VI, LIP6/ASIM laboratory; Bull SA
Christophe Alexandre , University Paris VI, LIP6/ASIM laboratory
Marek Sroka , University Paris VI, LIP6/ASIM laboratory
pp. 920-921
7G: Quantifying Architecture Trade-Off

Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies (Abstract)

Animesh Datta , Purdue University, West Lafayette, IN
Saibal Mukhopadhyay , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Nilanjan Banerjee , Purdue University, West Lafayette, IN
Swarup Bhunia , Purdue University, West Lafayette, IN
pp. 926-931

Compositional Memory Systems for Multimedia Communicating Tasks (Abstract)

A. M. Molnos , Delft University of Technology, The Netherlands; Philips Research Laboratories, The Netherlands
J. T. J. van Eijndhoven , Philips Research Laboratories, The Netherlands
S. D. Cotofana , Delft University of Technology, The Netherlands; Philips Research Laboratories, The Netherlands
M. J. M. Heijligers , Philips Research Laboratories, The Netherlands
pp. 932-937

Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes (Abstract)

Judita Kruse , Technical University of Braunschweig, Germany
Clive Thomsen , Technical University of Braunschweig, Germany
Thomas Spengler , Technical University of Braunschweig, Germany
Thomas Volling , Technical University of Braunschweig, Germany
Rolf Ernst , Technical University of Braunschweig, Germany
pp. 938-943
Interactive Presentations

A New System Design Methodology for Wire Pipelined SoC (PDF)

Luca Macchiarulo , University of Hawaii, HI
Mario R. Casu , Politecnico di Torino, Italy
pp. 944-945
8A: Panel Session - Is There a Market for SystemC Tools?
8B: Interconnect Solutions: Timing, Noise, and Process Variations

Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction (Abstract)

Peng Li , Texas A&M University, USA
Lawrence T. Pileggi , Carnegie Mellon University, USA
Frank Liu , IBM Austin Research Laboratories, USA
Xin Li , Carnegie Mellon University, USA
Sani R. Nassif , IBM Austin Research Laboratories, USA
pp. 958-963

Stochastic Power Grid Analysis Considering Process Variations (Abstract)

Janet Wang , University of Arizona, Tucson
Praveen Ghanta , University of Arizona, Tucson
Rajendran Panda , FreeScale Semiconductor Inc., Austin
Sarma Vrudhula , University of Arizona, Tucson
pp. 964-969

Buffer Insertion Considering Process Variation (Abstract)

Lei He , University of California at Los Angeles
Jinjun Xiong , University of California at Los Angeles
Kingho Tam , University of California at Los Angeles
pp. 970-975

EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation (Abstract)

Baohua Wang , University of Michigan, Ann Arbor
Pinaki Mazumder , University of Michigan, Ann Arbor
pp. 976-981
Interactive Presentations

Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis (PDF)

Davide Pandini , STMicroelectronics, Central R&D, Italy
Cristiano Forzan , STMicroelectronics, Central R&D, Italy
pp. 982-983

Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions (PDF)

Tom Chen , Colorado State University, USA
Ajith Chandy , Colorado State University, USA
pp. 984-985

Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization (PDF)

Walter Stechele , Lehrstuhl f?r Integrierte Systeme, TU M?nchen
Ra?l Medina Belt?n de Ot?lora , Lehrstuhl f?r Integrierte Systeme, TU M?nchen
Paul Zuber , Lehrstuhl f?r Integrierte Systeme, TU M?nchen
Armin Windschieg , IBM Deutschland Entwicklung, B?blingen
Andreas Herkersdorf , Lehrstuhl f?r Integrierte Systeme, TU M?nchen
pp. 986-987
8C: Advances in Pattern Generation for Fault Detection and Diagnosis

Implicit and Exact Path Delay Fault Grading in Sequential Circuits (Abstract)

S. Chakravarty , Intel Corporation, Santa Clara, CA
R. Jayabharathi , Intel Corporation, Sacramento, CA
M. M. Vaseekar Kumar , Southern Illinois University, Carbondale, IL
S. Tragoudas , Southern Illinois University, Carbondale, IL
pp. 990-995

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs (Abstract)

Yu-Shen Yang , University of Toronto, ON
Andreas Veneris , University of Toronto, ON
Srikanth Venkataraman , Intel Corporation, Hillsboro, OR
Paul Thadikaran , Intel Corporation, Hillsboro, OR
pp. 996-1001

The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits (Abstract)

Sudhakar M. Reddy , University of Iowa, Iowa City, IA
Irith Pomeranz , Purdue University, W. Lafayette, IN
pp. 1008-1013
Interactive Presentations

Framework for Fault Analysis and Test Generation in DRAMs (PDF)

Georg Mueller , Infineon Technologies AG, Germany
Zaid Al-Ars , CatRam Solutions, The Netherlands; Delft University of Technology, The Netherlands; Infineon Technologies AG, Germany
Ad J. van de Goor , Delft University of Technology, The Netherlands
Said Hamdioui , Delft University of Technology, The Netherlands
pp. 1020-1021

Mutation Sampling Technique for the Generation of Structural Test Data (PDF)

B. Rouzeyre , LIRMM, Universit? de Montpellier, France
M. Scholiv? , LCIS-ESISAR, France
C. Robach , LCIS-ESISAR, France
V. Beroulle , LCIS-ESISAR, France
M. L. Flottes , LIRMM, Universit? de Montpellier, France
pp. 1022-1023
8E: Embedded Software Technology

Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing (Abstract)

Feihui Li , The Pennsylvania State University, University Park, PA
Ozcan Ozturk , The Pennsylvania State University, University Park, PA
Guangyu Chen , The Pennsylvania State University, University Park, PA
Guilin Chen , The Pennsylvania State University, University Park, PA
Mahmut Kandemir , The Pennsylvania State University, University Park, PA
pp. 1026-1031

BB-GC: Basic-Block Level Garbage Collection (Abstract)

Mary Jane Irwin , The Pennsylvania State University, University Park, PA
Ozcan Ozturk , The Pennsylvania State University, University Park, PA
Mahmut Kandemir , The Pennsylvania State University, University Park, PA
pp. 1032-1037

Fine Grain QoS Control for Multimedia Application Software (Abstract)

Jacques Combaz , Verimag, France; STMicroelectronics, France
Joseph Sifakis , Verimag, France
Thierry Lepley , STMicroelectronics, France
Jean-Claude Fernandez , Verimag, France
pp. 1038-1043

Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development (Abstract)

L. Mangeruca , PARADES E.E.I.G., Italy
U. Freund , ETAS GmbH, Germany
A. Ferrari , PARADES E.E.I.G., Italy
H.-J. Wolff , PARADES E.E.I.G., Italy
E. Schlenker , ETAS GmbH, Germany
A. L. Sangiovanni-Vincentelli , PARADES E.E.I.G., Italy; University of California at Berkeley
M. Baleani , PARADES E.E.I.G., Italy
pp. 1044-1049

galsC: A Language for Event-Driven Embedded Systems (Abstract)

Elaine Cheong , University of California, Berkeley
Jie Liu , Microsoft Research, Redmond, WA
pp. 1050-1055
Interactive Presentations

Compiler-Directed Instruction Duplication for Soft Error Detection (PDF)

N. Vijaykrishnan , The Pennsylvania State University
Jie S. Hu , New Jersey Institute of Technology
Feihui Li , The Pennsylvania State University
Vijay Degalahal , The Pennsylvania State University
Mahmut Kandemir , The Pennsylvania State University
Mary J. Irwin , The Pennsylvania State University
pp. 1056-1057

OS Debugging Method Using a Lightweight Virtual Machine Monitor (PDF)

Tadashi Takeuchi , Hitachi Systems Development Laboratory, Japan
pp. 1058-1059

Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications (PDF)

Spiridon Nikolaidis , Aristotle University of Thessaloniki, Greece
Nikolaos Kavvadias , Aristotle University of Thessaloniki, Greece
pp. 1060-1061
8F: Advanced Analogue Performance Modelling

Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces (Abstract)

Tom Eeckelaert , Katholieke Universiteit Leuven
Georges Gielen , Katholieke Universiteit Leuven
Trent McConaghy , Katholieke Universiteit Leuven
pp. 1070-1075

Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework (Abstract)

Gerd Vandersteen , IMEC vzw., Belgium
Rik Pintelon , Vrije Universiteit Brussel, Belgium
Ludwig De Locht , IMEC vzw., Belgium
Snezana Jenei , IMEC vzw., Belgium
Yves Rolain , Vrije Universiteit Brussel, Belgium
pp. 1076-1081

CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming (Abstract)

Georges Gielen , K.U. Leuven, ESAT-MICAS, Belgium
Tom Eeckelaert , K.U. Leuven, ESAT-MICAS, Belgium
Trent McConaghy , K.U. Leuven, ESAT-MICAS, Belgium
pp. 1082-1087
Interactive Presentation

A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling (PDF)

Ranga Vemuri , University of Cincinnati, OH
Mengmeng Ding , University of Cincinnati, OH
pp. 1088-1089
8G: Hot Topic - Biochips: Principles and Application

New Perspectives and Opportunities From the Wild West of Microelectronic Biochips (PDF)

Vincent Auger , Silicon Biosystems, Bologna, Italy
Melanie Abonnenc , Silicon Biosystems, Bologna, Italy
Nicol? Manaresi , Silicon Biosystems, Bologna, Italy
Roberto Guerrieri , ARCES-University of Bologna, Bologna, Italy
Aldo Romani , ARCES-University of Bologna, Bologna, Italy
Paul Vulto , ARCES-University of Bologna, Bologna, Italy
Luigi Altomare , ARCES-University of Bologna, Bologna, Italy
Marco Tartagni , ARCES-University of Bologna, Bologna, Italy
Gianni Medoro , Silicon Biosystems, Bologna, Italy
pp. 1092-1093
9A: Efficient SAT Based Verification

Verification of Embedded Memory Systems using Efficient Memory Modeling (Abstract)

Aarti Gupta , NEC Laboratories America, Princeton, NJ
Malay K. Ganai , NEC Laboratories America, Princeton, NJ
Pranav Ashar , NEC Laboratories America, Princeton, NJ
pp. 1096-1101

An Efficient Sequential SAT Solver With Improved Search Strategies (Abstract)

F. Lu , University of California at Santa Barbara
K.-T. Cheng , University of California at Santa Barbara
L.-C. Wang , University of California at Santa Barbara
K. C. Chen , Cadence Corporation
G. Parthasarathy , University of California at Santa Barbara
M. K. Iyer , University of California at Santa Barbara
pp. 1102-1107

Considering Circuit Observability Don't Cares in CNF Satisfiability (Abstract)

Zhaohui Fu , Princeton University, NJ
Sharad Malik , Princeton University, NJ
Yinlei Yu , Princeton University, NJ
pp. 1108-1113
9B: Embedded Tutorial - How Do They Manage Designing Complex SoC?

Integration, Verification and Layout of a Complex Multimedia SOC (PDF)

Youn-Long Lin , National Tsing Hua University, Taiwan
Jiing-Yuan Lin , Global UniChip Corp., Taiwan
Chien-Liang Chen , Global UniChip Corp., Taiwan
pp. 1116-1117

JPEG, MPEG-4, and H.264 Codec IP Development (PDF)

Chung-Jr Lian , National Taiwan University, Taipei
Hung-Chi Fang , National Taiwan University, Taipei
Yu-Wen Huang , National Taiwan University, Taipei
Liang-Gee Chen , National Taiwan University, Taipei
Yung-Chi Chang , National Taiwan University, Taipei
pp. 1118-1119

SOC Testing Methodology and Practice (PDF)

Cheng-Wen Wu , National Tsing Hua University, Hsinchu
pp. 1120-1121
9C: Test Pattern Compression and Delay Test Schemes

Evolutionary Optimization in Code-Based Test Compression (Abstract)

Bernd Becker , Albert-Ludwigs-University, Germany
Ilia Polian , Albert-Ludwigs-University, Germany
Alejandro Czutro , Albert-Ludwigs-University, Germany
pp. 1124-1129

Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination (Abstract)

Kedarnath J. Balakrishnan , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 1130-1135

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application (Abstract)

Arijit Raychowdhury , Purdue University, IN
Swarup Bhunia , Purdue University, IN
Hamid Mahmoodi , Purdue University, IN
Kaushik Roy , Purdue University, IN
pp. 1136-1141

Hybrid BIST Based on Repeating Sequences and Cluster Analysis (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
Lei Li , Freescale Semiconductor, Inc., Austin, TX
pp. 1142-1147
9E: Compiler/Architecture Codesign

C Compiler Retargeting Based on Instruction Semantics Models (Abstract)

Manuel Hohenauer , Aachen University of Technology
Heinrich Meyr , Aachen University of Technology
Jianjiang Ceng , Aachen University of Technology
Gerd Ascheid , Aachen University of Technology
Gunnar Braun , CoWare, Inc., Aachen, Germany
Rainer Leupers , Aachen University of Technology
pp. 1150-1155

A Constraint Network Based Approach to Memory Layout Optimization (Abstract)

M. Karakoy , Imperial College, UK
M. Kandemir , The Pennsylvania State University
G. Chen , The Pennsylvania State University
pp. 1156-1161

Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access (Abstract)

F. Catthoor , Katholieke Universiteit Leuven, Belgium
M. J. Absar , Katholieke Universiteit Leuven, Belgium
pp. 1162-1167

Structural Testing Based on Minimum Kernels (Abstract)

Elena Dubrova , Royal Institute of Technology, IMIT/KTH, Sweden
pp. 1168-1173
9F: Network-on-Chip Design Flows

An Application-Specific Design Methodology for STbus Crossbar Generation (Abstract)

Srinivasan Murali , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
pp. 1176-1181

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification (Abstract)

Santiago Gonz?lez Pestana , Philips Research Laboratories, Eindhoven, The Netherlands
Kees Goossens , Philips Research Laboratories, Eindhoven, The Netherlands
Edwin Rijpkema , Philips Research Laboratories, Eindhoven, The Netherlands
Andrei Radulescu , Philips Research Laboratories, Eindhoven, The Netherlands
Om Prakash Gangwal , Philips Research Laboratories, Eindhoven, The Netherlands
John Dielissen , Philips Research Laboratories, Eindhoven, The Netherlands
pp. 1182-1187

?pipes Lite: A Synthesis Oriented Design Library For Networks on Chips (Abstract)

Stergios Stergiou , Stanford University, CA
Giovanni De Micheli , Stanford University, CA
Luigi Raffo , University of Cagliari, Italy
Davide Bertozzi , University of Bologna, Italy
Salvatore Carta , University of Cagliari, Italy
Federico Angiolini , University of Bologna, Italy
pp. 1188-1193
9G: Biochips and Quantum Computing

Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips (Abstract)

Krishnendu Chakrabarty , Duke University, Durham, NC
Fei Su , Duke University, Durham, NC
pp. 1202-1207

Quantum Circuit Simplification Using Templates (Abstract)

D. Maslov , University of Victoria, Canada
C. Young , University of Victoria, Canada
D. M. Miller , University of Victoria, Canada
G. W. Dueck , University of New Brunswick, Canada
pp. 1208-1213

Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths (Abstract)

Kaijie Wu , University of Illinois at Chicago
Ramesh Karri , Polytechnic University, Brooklyn
Kyosun Kim , University of Incheon, Korea
pp. 1214-1219
9K: CMOS-Based Biosensor Arrarys

CMOS-Based Biosensor Arrays (PDF)

M. Schienle , Infineon Technologies, Munich / Regensburg, Germany
F. Hofmann , Infineon Technologies, Munich / Regensburg, Germany
G. Beer , Infineon Technologies, Munich / Regensburg, Germany
R. Thewes , Infineon Technologies, Munich / Regensburg, Germany
P. Schindler-Bauer , Infineon Technologies, Munich / Regensburg, Germany
M. Augustyniak , Infineon Technologies, Munich / Regensburg, Germany
A. Frey , Infineon Technologies, Munich / Regensburg, Germany
R. Brederlow , Infineon Technologies, Munich / Regensburg, Germany
H.-C. Hanke , Infineon Technologies, Munich / Regensburg, Germany
B. Eversmann , Infineon Technologies, Munich / Regensburg, Germany
B. Holzapfl , Infineon Technologies, Munich / Regensburg, Germany
T. Haneder , Infineon Technologies, Munich / Regensburg, Germany
M. Jenkner , Infineon Technologies, Munich / Regensburg, Germany
M. Atzesberger , Infineon Technologies, Munich / Regensburg, Germany
C. Paulus , Infineon Technologies, Munich / Regensburg, Germany
pp. 1222-1223
10A: Efficient Network-on-Chip Architectures

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip (Abstract)

Tobias Bjerregaard , Technical University of Denmark (DTU)
Jens Spars? , Technical University of Denmark (DTU)
pp. 1226-1231

A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips (Abstract)

Wolf-Dietrich Weber , Sonics, Inc.?
Drew Wingard , Sonics, Inc.?
Ian Swarbrick , Sonics, Inc.?
Joe Chou , Google, Inc.?
pp. 1232-1237

A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks (Abstract)

Sharad Malik , Princeton University, Princeton, NJ
Hangsheng Wang , Princeton University, Princeton, NJ
Li-Shiuan Peh , Princeton University, Princeton, NJ
pp. 1238-1243
10B: Architectural Synthesis and Design Space Exploration

ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement (Abstract)

Laura Pozzi , Ecole Polytechnique F?d?rale de Lausanne (EPFL), Switzerland
Paolo Ienne , Ecole Polytechnique F?d?rale de Lausanne (EPFL), Switzerland
Sudarshan Banerjee , University of California, Irvine
Nikil Dutt , University of California, Irvine
Partha Biswas , University of California, Irvine
pp. 1246-1251

Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis (Abstract)

M. C. Molina , Universidad Complutense de Madrid
J. M. Mend?as , Universidad Complutense de Madrid
R. Ruiz-Sautua , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 1252-1257

Reliability-Centric High-Level Synthesis (Abstract)

N. Mansouri , Syracuse University
Yuan Xie , Pennsylvania State University
E. Arvas , Syracuse University
S. Tosun , Syracuse University
M. Kandemir , Pennsylvania State University
pp. 1258-1263

PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors (Abstract)

Nikil Dutt , University of California, Irvine
Eugene Earlie , Intel Corporation, Hudson, MA
Alex Nicolau , University of California, Irvine
Aviral Shrivastava , University of California, Irvine
pp. 1264-1269
10C: Concurrent Error Detection and Correction

Concurrent Error Detection in Asynchronous Burst-Mode Controllers (Abstract)

Sobeeh Almukhaizim , Yale University, New Haven, CT
Yiorgos Makris , Yale University, New Haven, CT
pp. 1272-1277

Reliable System Specification for Self-Checking Data-Paths (Abstract)

C. Bolchini , Politecnico di Milano, Italy
L. Pomante , CEFRIEL, Milano, Italy
F. Salice , Politecnico di Milano, Italy
D. Sciuto , Politecnico di Milano, Italy
pp. 1278-1283

Evaluation of Error-Resilience for Reliable Compression of Test Data (Abstract)

Fabrizio Lombardi , Northeastern University, Boston, MA
Luca Schiano , Northeastern University, Boston, MA
Hamidreza Hashempour , LTX Corp., San Jose, CA
pp. 1284-1289

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs (Abstract)

M. Sonza Reorda , Politecnico di Torino, Italy
L. Carro , Universidade Federal do Rio, Brazil
L. Sterpone , Politecnico di Torino, Italy
F. Lima Kastensmidt , Universidade Estadual do Rio, Brazil; Universidade Federal do Rio, Brazil
pp. 1290-1295
10E: Formal Verification of Processor Architecture and DSP Programs

Automatic Formal Verification of Fused-Multiply-Add FPUs (Abstract)

Jason Baumgartner , IBM Systems Group, Austin, TX
Viresh Paruthi , IBM Systems Group, Austin, TX
Christian Jacobi , IBM Deutschland Entwicklung GmbH, Boeblingen, Germany
Kai Weber , IBM Deutschland Entwicklung GmbH, Boeblingen, Germany
pp. 1298-1303

Refinement Maps for Efficient Verification of Processor Models (Abstract)

Panagiotis Manolios , Georgia Tech, Atlanta, GA
Sudarshan K. Srinivasan , Georgia Tech, Atlanta, GA
pp. 1304-1309

Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code (Abstract)

K. C. Shashidhar , Interuniversitair Micro-Elektronica Centrum (IMEC) vzw, Belgium
Gerda Janssens , Katholieke Universiteit Leuven, Belgium
Maurice Bruynooghe , Katholieke Universiteit Leuven, Belgium
Francky Catthoor , Interuniversitair Micro-Elektronica Centrum (IMEC) vzw, Belgium; Katholieke Universiteit Leuven, Belgium
pp. 1310-1315
10F: Interconnect Optimisation

Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission (Abstract)

Sunil P. Khatri , Texas A&M University, College Station
Brock J. LaMeres , University of Colorado, Boulder
pp. 1318-1323

An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types (Abstract)

Zhuo Li , Texas A&M University, College Station
Weiping Shi , Texas A&M University, College Station
pp. 1324-1329

RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power (Abstract)

Yuantao Peng , North Carolina State University, Raleigh, NC
Marios C. Papaefthymiou , University of Michigan, Ann Arbor, MI
Xun Liu , North Carolina State University, Raleigh, NC
pp. 1330-1335
10G: Hot Topic - Silicon Based Biochips

Cantilever-Based Biosensors in CMOS Technology (PDF)

C. Vancura , ETH Zurich, Switzerland
W. H. Song , ETH Zurich, Switzerland
M. Zimmermann , ETH Zurich, Switzerland
T. Volden , ETH Zurich, Switzerland
K.-U. Kirstein , ETH Zurich, Switzerland
J. Lichtenberg , ETH Zurich, Switzerland
A. Hierlemannn , ETH Zurich, Switzerland
Y. Li , ETH Zurich, Switzerland
pp. 1340-1341

Author Index (PDF)

pp. 1342-1348
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