The Community for Technology Leaders
RSS Icon
Subscribe
Munich, Germany
March 7, 2005 to March 11, 2005
ISBN: 0-7695-2288-2
pp: 896-897
Pierre Bomel , LESTER, Universit? de Bretagne Sud, Lorient, France
Eric Martin , LESTER, Universit? de Bretagne Sud, Lorient, France
Emmanuel Boutillon , LESTER, Universit? de Bretagne Sud, Lorient, France
ABSTRACT
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. Our contribution consists in IP encapsulation into a new wrapper model which speed and area are optimized and synthetizability guarantied. The main benefit of our approach is to preserve the local IP performances when encapsulating them and reduce SoC silicon area.
INDEX TERMS
null
CITATION
Pierre Bomel, Eric Martin, Emmanuel Boutillon, "Synchronization Processor Synthesis for Latency Insensitive Systems", DATE, 2005, Proceedings. Design, Automation and Test in Europe, Proceedings. Design, Automation and Test in Europe 2005, pp. 896-897, doi:10.1109/DATE.2005.287
12 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool