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Design, Automation & Test in Europe Conference & Exhibition (2005)
Munich, Germany
Mar. 7, 2005 to Mar. 11, 2005
ISSN: 1530-1591
ISBN: 0-7695-2288-2
pp: 896-897
Pierre Bomel , LESTER, Universit? de Bretagne Sud, Lorient, France
Emmanuel Boutillon , LESTER, Universit? de Bretagne Sud, Lorient, France
Eric Martin , LESTER, Universit? de Bretagne Sud, Lorient, France
ABSTRACT
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. Our contribution consists in IP encapsulation into a new wrapper model which speed and area are optimized and synthetizability guarantied. The main benefit of our approach is to preserve the local IP performances when encapsulating them and reduce SoC silicon area.
INDEX TERMS
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CITATION
Pierre Bomel, Emmanuel Boutillon, Eric Martin, "Synchronization Processor Synthesis for Latency Insensitive Systems", Design, Automation & Test in Europe Conference & Exhibition, vol. 02, no. , pp. 896-897, 2005, doi:10.1109/DATE.2005.287
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