The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2005)
Munich, Germany
Mar. 7, 2005 to Mar. 11, 2005
ISSN: 1530-1591
ISBN: 0-7695-2288-2
TABLE OF CONTENTS
Intro

Foreword (PDF)

pp. xxvii-xxviii

Best Paper Awards (PDF)

pp. xxix

Master Courses (PDF)

pp. xxxiv
Keynote Addresses

SoC in Nanoera: Challenges and Endless Possibility (PDF)

Jeong-Taek Kong , Samsung Electronics Co Ltd, Korea
pp. 2
1A: Partitioning and Optimisation for Reconfigurable Computing

A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures (Abstract)

Nastaran Baradaran , University of Southern California / Information Sciences Institute, Marina del Rey, California
Pedro C. Diniz , University of Southern California / Information Sciences Institute, Marina del Rey, California
pp. 6-11

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization (Abstract)

Chulsoo Park , Seoul National University, South Korea
Kiyoung Choi , Seoul National University, South Korea
Mary Kiemb , Seoul National University, South Korea
Jinyong Jung , Seoul National University, South Korea
Yoonjin Kim , Seoul National University, South Korea
pp. 12-17

A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning (Abstract)

Roman Lysecky , University of California, Riverside
Frank Vahid , University of California, Riverside
pp. 18-23

Reconfigurable Elliptic Curve Cryptosystems on a Chip (Abstract)

Ray C. C. Cheung , Imperial College London, UK
Wayne Luk , Imperial College London, UK
Peter Y. K. Cheung , Imperial College London, UK
pp. 24-29
Interactive Presentations

An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs (PDF)

Rui Rodrigues , University of Algarve, Portugal
Jo?o M. P. Cardoso , University of Algarve, Portugal
pp. 30-31

FPGA Architecture for Multi-Style Asynchronous Logic (PDF)

L. Fesquet , TIMA Laboratory, France
M. Renaudin , TIMA Laboratory, France
H. Dubreuil , TIMA Laboratory, France
N. Huot , TIMA Laboratory, France
pp. 32-33
1B: Hot Topic - Analogue/Digital Circuit Design in 65nm: End of the Road

Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? (Abstract)

Phillip Christie , Philips, The Netherlands
Karen Maex , IMEC, Belgium
Ted Vucurevich , Cadence, USA
Georges Gielen , K.U. Leuven, Belgium
Wim Dehaene , K.U. Leuven, Belgium
Edmond Janssens , ST Microelectronics, Belgium
Dieter Draxelmayr , Infineon, Austria
pp. 36-42
1C: SoC Design-for-Test

On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips (Abstract)

Erik Jan Marinissen , Philips Research Laboratories, The Netherlands
Sandeep Kumar Goel , Philips Research Laboratories, The Netherlands
pp. 44-49

Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores (Abstract)

Fang Liu , Duke University, Durham, NC
Krishnendu Chakrabarty , Duke University, Durham, NC
Sule Ozev , Duke University, Durham, NC
Anuja Sehgal , Duke University, Durham, NC
pp. 50-55

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality (Abstract)

Matthias Beck , Infineon Technologies AG, Germany
Frank Poehl , Infineon Technologies AG, Germany
Olivier Barondeau , Infineon Technologies AG, Germany
Xijiang Lin , Mentor Graphics Corporation, Wilsonville, OR
Ron Press , Mentor Graphics Corporation, Wilsonville, OR
Martin Kaibel , Infineon Technologies AG, Germany
pp. 56-61
Interactive Presentation

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture (PDF)

Alexandre M. Amory , PPGC - II - UFRGS, Brazil
Edson I. Moreno , PPGCC - FACIN - PUCRS, Brazil
Fernando G. Moraes , PPGCC - FACIN - PUCRS, Brazil
Marcelo Lubaszewski , PPGC - II - UFRGS, Brazil; PPGEE - EE - UFRGS, Brazil; IMSE-CNM-Universidad de Sevilla, Spain
pp. 62-63
1E: Embedded Tutorial - Cross-Pollination between HW and SW - Hard Lessons for Software, and Vice Versa

Applying UML and MDA to Real Systems Design (PDF)

Ian Oliver , Nokia Research Center, Finland
pp. 70-71
1F: Low Power Design with Error Tolerance

Energy Bounds for Fault-Tolerant Nanoscale Designs (Abstract)

Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 74-79

DVS for On-Chip Bus Designs Based on Timing Error Correction (Abstract)

David Blaauw , University of Michigan, Ann Arbor, MI
Himanshu Kaul , Intel Corporation, Hillsboro, OR
Todd Austin , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Trevor Mudge , University of Michigan, Ann Arbor, MI
pp. 80-85

Joint Power Management of Memory and Disk (Abstract)

Yung-Hsiang Lu , Purdue University
Le Cai , Purdue University
pp. 86-91

Assertion-Based Design Exploration of DVS in Network Processor Architectures (Abstract)

Felice Balarin , Cadence Berkeley Laboratories
Jia Yu , University of California, Riverside
Jun Yang , University of California, Riverside
Xi Chen , University of California, Riverside
Wei Wu , University of California, Riverside
Harry Hsieh , University of California, Riverside
pp. 92-97
2A: Scheduling and Synthesis for Reconfigurable Computing

Instruction Scheduling for Dynamic Hardware Configurations (Abstract)

Koen Bertels , Delft University of Technology, The Netherlands
Stamatis Vassiliadis , Delft University of Technology, The Netherlands
Elena Moscu Panainte , Delft University of Technology, The Netherlands
pp. 100-105

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware (Abstract)

Javier Resano , Universidad Complutense de Madrid
Daniel Mozos , Universidad Complutense de Madrid
Francky Catthoor , IMEC vzw, Leuven, Belgium
pp. 106-111

Optimized Generation of Data-Path from C Codes for FPGAs (Abstract)

Walid Najjar , University of California Riverside
Zhi Guo , University of California Riverside
Kees Vissers , Xilinx Corp.
Betul Buyukkurt , University of California Riverside
pp. 112-117
2B: Analogue Simulation, Placement and Statistical Analysis

Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series (Abstract)

Ewout Martens , Katholieke Universiteit Leuven, Belgium
Georges Gielen , Katholieke Universiteit Leuven, Belgium
pp. 120-125

On Statistical Timing Analysis with Inter- and Intra-Die Variations (Abstract)

Mohab Anis , University of Waterloo, Canada
Hratch Mangassarian , University of Waterloo, Canada
pp. 132-137
2C: Analogue and Gigahertz Test

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL (Abstract)

C. Gray , Georgia Institute of Technology, Atlanta, GA
A. Majid , Georgia Institute of Technology, Atlanta, GA
D. C. Keezer , Georgia Institute of Technology, Atlanta, GA
N. Taher , Georgia Institute of Technology, Atlanta, GA
pp. 152-157

Noise Figure Evaluation Using Low Cost BIST (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul - UFRGS, Porto Alegre, RS, Brazil
Altamiro A. Susin , Universidade Federal do Rio Grande do Sul - UFRGS, Porto Alegre, RS, Brazil
Marcelo Negreiros , Universidade Federal do Rio Grande do Sul - UFRGS, Porto Alegre, RS, Brazil
pp. 158-163

Specification Test Compaction for Analog Circuits and MEMS (Abstract)

Larry T. Pileggi , Carnegie Mellon University, Pittsburgh, PA
Sounil Biswas , Carnegie Mellon University, Pittsburgh, PA
R. D. (Shawn) Blanton , Carnegie Mellon University, Pittsburgh, PA
Peng Li , Texas A&M University, College Station
pp. 164-169
Interactive Presentations

Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach (PDF)

R. Kheriji , ST Microelectronics, France; TIMA laboratory, France
J. L. Carbonero , ST Microelectronics, France
V. Danelon , ST Microelectronics, France
S. Mir , TIMA laboratory, France
pp. 170-171

IEEE 1149.4 Compatible ABMs for Basic RF Measurements (PDF)

Markku Moilanen , University of Oulu, Finland
Juha Hakkinen , University of Oulu, Finland
Pekka Syri , University of Oulu, Finland
pp. 172-173

Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits (PDF)

Carlos Eduardo Savioli , Brazilian Navy Electronics Center
Antonio Carneiro de Mesquita Filho , Federal University of Rio de Janeiro
Jose Vicente Calvano , Brazilian Navy Research Institute
Claudio C. Czendrodi , Brazilian Navy Electronics Center
pp. 174-175
2E: Ubiquitous Computing: Security and Energy Aspects

Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring (Abstract)

Niraj K. Jha , Princeton University, Princeton, NJ
Anand Raghunathan , NEC Laboratories America, Princeton, NJ
Divya Arora , Princeton University, Princeton, NJ
Srivaths Ravi , NEC Laboratories America, Princeton, NJ
pp. 178-183

Energy-Aware Routing for E-Textile Applications (Abstract)

Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Jung-Chun Kao , Carnegie Mellon University, Pittsburgh, PA
pp. 184-189

LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks (Abstract)

Arijit Ghosh , University of California, Irvine, CA
Tony Givargis , University of California, Irvine, CA
pp. 190-195

Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives (Abstract)

Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge, MA
Wim Dehaene , K. U. Leuven, Belgium
Denis C. Daly , Massachusetts Institute of Technology, Cambridge, MA
Bruno Bougard , IMEC, Leuven, Belgium; K. U. Leuven, Belgium
Francky Catthoor , IMEC, Leuven, Belgium; K. U. Leuven, Belgium
pp. 196-201
Interactive Presentation

Lifetime Modeling of a Sensor Network (PDF)

Vivek Rai , Texas A&M University, College Station, TX
Rabi N. Mahapatra , Texas A&M University, College Station, TX
pp. 202-203
2F: Power Aware Design in DSM Technology

A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs (Abstract)

S. A. Bota , Universitat de les Illes Balears, Spain
J. Segura , Universitat de les Illes Balears, Spain
A. Keshavarzi , Intel Corp., Portland (OR)
J. L. Rossell? , Universitat de les Illes Balears, Spain
V. Canals , Universitat de les Illes Balears, Spain
pp. 206-211

Activity Packing in FPGAs for Leakage Power Reduction (Abstract)

Antoine El Daher , University of Waterloo, Canada
Hassan Hassan , University of Waterloo, Canada
Mohab Anis , University of Waterloo, Canada
Mohamed Elmasry , University of Waterloo, Canada
pp. 212-217

Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures (Abstract)

N. Vijaykrishnan , Pennsylvania State University, University Park
Suresh Srinivasan , Pennsylvania State University, University Park
Lin Li , Pennsylvania State University, University Park
pp. 218-223

Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN
Swarup Bhunia , Purdue University, West Lafayette, IN
Saibal Mukhopadhyay , Purdue University, West Lafayette, IN
pp. 224-229
Interactive Presentation

Leakage-Aware Interconnect for On-Chip Network (PDF)

Vijaykrishnan Narayaynan , Penn State University
Yuh-Fang Tsai , Penn State University
Mary Jane Irwin , Penn State University
Yuan Xie , Penn State University
pp. 230-231
3A: Reconfigurability in MPSoC

Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles (Abstract)

T. Marescaux , IMEC, Leuven, Belgium
V. Nollet , IMEC, Leuven, Belgium
P. Avasare , IMEC, Leuven, Belgium; Vrije Universiteit Brussel and at Katholieke Universiteit Leuven
J-Y. Mignolet , IMEC, Leuven, Belgium
pp. 234-239

Symmetric Multiprocessing on Programmable Chips Made Easy (Abstract)

William Bishop , University of Waterloo, Ontario, Canada
Austin Hung , University of Waterloo, Ontario, Canada
Andrew Kennings , University of Waterloo, Ontario, Canada
pp. 240-245

A Complete Network-On-Chip Emulation Framework (Abstract)

R. Hermida , DACYA/UCM, Madrid, Spain
J. M. Mendias , DACYA/UCM, Madrid, Spain
G. De Micheli , Stanford University, Palo Alto, USA
D. Atienza , DACYA/UCM, Madrid, Spain
F. Catthoor , IMEC vzw, Leuven, Belgium
N. Genko , Stanford University, Palo Alto, USA
pp. 246-251
Interactive Presentations

Low Cost Task Migration Initiation in a Heterogeneous MP-SoC (PDF)

J-Y. Mignolet , IMEC, Leuven, Belgium
P. Avasare , IMEC, Leuven, Belgium
V. Nollet , IMEC, Leuven, Belgium
D. Verkest , IMEC, Leuven, Belgium; Vrije Universiteit Brussel and at Katholieke Universiteit Leuven
pp. 252-253

Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip (PDF)

Marc Geilen , Eindhoven University of Technology, The Netherlands
Sander Stuijk , Eindhoven University of Technology, The Netherlands
Twan Basten , Eindhoven University of Technology, The Netherlands
Bart Mesman , Eindhoven University of Technology, The Netherlands; Philips Research Laboratories, The Netherlands
pp. 254-255
3B: Analogue, Mixed-Signal and RF Circuits and Systems

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit (Abstract)

Paul Muller , Ecole Polytechnique F?d?rale de Lausanne (EPFL), Switzerland
Mojtaba Atarodi , Sharif University of Technology, Teheran, Iran
Armin Tajalli , Sharif University of Technology, Teheran, Iran
Yusuf Leblebici , Ecole Polytechnique F?d?rale de Lausanne (EPFL), Switzerland
pp. 258-263

MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption (Abstract)

Alex Doboli , Stony Brook University, Stony Brook, NY
Hua Tang , Stony Brook University, Stony Brook, NY
Ying Wei , Stony Brook University, Stony Brook, NY
pp. 264-269

Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (Abstract)

C. Soens , IMEC; Vrije Universiteit Brussel, Belgium
P. Wambacq , IMEC; Vrije Universiteit Brussel, Belgium
S. Donnay , IMEC
pp. 270-275
Interactive Presentations

Systematic Figure of Merit Computation for the Design of Pipeline ADC (PDF)

S. Crand , IETR, Universit? de Rennes, France
L. Barrandon , IETR, Universit? de Rennes, France
D. Houzet , IETR, Universit? de Rennes, France
pp. 277-278

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters (PDF)

Gin-Kou Ma , SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan
Yu-Tsun Chien , SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan
Dong Chen , Carnegie Mellon University, Pittsburgh, Pennsylvania
Tamal Mukherjee , Carnegie Mellon University, Pittsburgh, Pennsylvania
Rob A. Rutenbar , Carnegie Mellon University, Pittsburgh, Pennsylvania
Jea-Hong Lou , SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan
pp. 279-280
3C: Reliability at the Very Deep Sub-Micron Region

Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices (Abstract)

George F. Viamontes , Los Alamos National Lab, NM
Smita Krishnaswamy , University of Michigan, Ann Arbor
Igor L. Markov , University of Michigan, Ann Arbor
John P. Hayes , University of Michigan, Ann Arbor
pp. 282-287

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits (Abstract)

Yuvraj Singh Dhillon , Georgia Institute of Technology, Atlanta, GA
Abdulkadir Utku Diril , Georgia Institute of Technology, Atlanta, GA
Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, GA
pp. 288-293

Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques (Abstract)

Osama Neiroukh , Intel Corporation, Hillsboro, OR
Xiaoyu Song , Portland State University, OR
pp. 294-299
Interactive Presentations

An Accurate SER Estimation Method Based on Propagation Probability (PDF)

Mehdi B. Tahoori , Northeastern University, Boston MA
Ghazanfar Asadi , Northeastern University, Boston MA
pp. 306-307

Techniques for Fast Transient Fault Grading Based on Autonomous Emulation (PDF)

Marta Portela-Garc? , University Carlos III of Madrid, Spain
Mario Garc?a-Valderas , University Carlos III of Madrid, Spain
Luis Entrena-Arrontes , University Carlos III of Madrid, Spain
Celia L?pez-Ongil , University Carlos III of Madrid, Spain
pp. 308-309
3F: HW/SW Solutions for Low Power Multimedia Systems

TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques (Abstract)

Arne Hamann , Technical University of Braunschweig, Germany
Rolf Ernst , Technical University of Braunschweig, Germany
pp. 312-317

Scheduling of Soft Real-Time Systems for Context-Aware Applications (Abstract)

Lei He , University of California, Los Angeles
Miodrag Potkonjak , University of California, Los Angeles
Weiping Liao , University of California, Los Angeles
Fei Li , University of California, Los Angeles
Jennifer L. Wong , University of California, Los Angeles
pp. 318-323

Model Reuse through Hardware Design Patterns (Abstract)

Jes? Barba , University of Castilla-La Mancha
Juan Carlos L?pez , University of Castilla-La Mancha
Francisco Moya , University of Castilla-La Mancha
Fernando Rinc? , University of Castilla-La Mancha
pp. 324-329

A Public-Key Watermarking Technique for IP Designs (Abstract)

Sofi?ne Tahar , Concordia University, Montr?al, Canada
Amr T. Abdel-Hamid , Concordia University, Montr?al, Canada
El Mostapha Aboulhamid , Universit? de Montr?al, Canada
pp. 330-335
Interactive Presentation
3F: HW/SW Solutions for Low Power Multimedia Systems

Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing (PDF)

Michael S. Hsiao , Virginia Tech, Blacksburg
Dong S. Ha , Virginia Tech, Blacksburg
Shrirang M. Yardi , Virginia Tech, Blacksburg
Thomas L. Martin , Virginia Tech, Blacksburg
pp. 340-345

HEBS: Histogram Equalization for Backlight Scaling (Abstract)

Hanif Fatemi , University of Southern California
Massoud Pedram , University of Southern California
Ali Iranli , University of Southern California
pp. 346-351

Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach (Abstract)

Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
Umit Y. Ogras , Carnegie Mellon University, Pittsburgh, PA
pp. 352-357

A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors (Abstract)

Farzan Fallah , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Tohru Ishihara , Fujitsu Laboratories of America, Inc., Sunnyvale, CA
pp. 358-363
4A: Embedded System Partitioning and Validation

Design Space Exploration for Dynamically Reconfigurable Architectures (Abstract)

Beno? Miramond , LaMI, Universit? d'Evry Val d'Essonne, France
Jean-Marc Delosme , LaMI, Universit? d'Evry Val d'Essonne, France
pp. 366-371

A Dependability-Driven System-Level Design Approach for Embedded Systems (Abstract)

Sorin A. Huss , TU Darmstadt, Darmstadt, Germany
Stephan Klaus , TU Darmstadt, Darmstadt, Germany
Arshad Jhumka , University of Warwick, England
pp. 372-377

A Time Slice Based Scheduler Model for System Level Design (Abstract)

Yosinori Watanabe , Cadence Berkeley Laboratories, CA
Luciano Lavagno , Politecnico di Torino, Italy
Claudio Passerone , Politecnico di Torino, Italy
Vishal Shah , Politecnico di Torino, Italy
pp. 378-383

A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation (Abstract)

Sang-Heon Lee , Korea Advanced Institute of Science and Technology
Chong-Min Kyung , Korea Advanced Institute of Science and Technology
Jae-Gon Lee , Korea Advanced Institute of Science and Technology
Ki-Yong Ahn , Korea Advanced Institute of Science and Technology
Moo-Kyoung Chung , Korea Advanced Institute of Science and Technology
pp. 384-389

Automated Synthesis of Assertion Monitors using Visual Specifications (Abstract)

S. Ramesh , Indian Institute of Technology Bombay, India
Ambar A. Gadkari , Indian Institute of Technology Bombay, India
pp. 390-395
Interactive Presentation

A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms (PDF)

Greg Stitt , University of California, Riverside
Frank Vahid , University of California, Riverside
pp. 396-397
4B: Logic Synthesis

Statistical Timing Based Optimization using Gate Sizing (Abstract)

David Blaauw , University of Michigan, Ann Arbor, MI
Kaviraj Chopra , University of Michigan, Ann Arbor, MI
Aseem Agarwal , University of Michigan, Ann Arbor, MI
pp. 400-405

An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs (Abstract)

Elena Dubrova , Royal Institute of Technology, IMIT/KTH, Sweden
Maxim Teslenko , Royal Institute of Technology, IMIT/KTH, Sweden
pp. 406-411

SAT-Based Complete Don't-Care Computation for Network Optimization (Abstract)

Alan Mishchenko , University of California, Berkeley
Robert K. Brayton , University of California, Berkeley
pp. 412-417

Efficient Solution of Language Equations Using Partitioned Representations (Abstract)

Nina Yevtushenko , Tomsk State University, Russia
Alan Mishchenko , University of California, Berkeley
Robert Brayton , University of California, Berkeley
Tiziano Villa , University of Udine, Italy
Roland Jiang , University of California, Berkeley
pp. 418-423

DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement (Abstract)

M. Renaudin , TIMA Laboratory, France
G. F. Bouesse , TIMA Laboratory, France
S. Dumont , TIMA Laboratory, France
Fabien Germain , SGDN/DCSSI, France
pp. 424-429
Interactive Presentations

Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition (PDF)

Elena Dubrova , Royal Institute of Technology, IMIT/KTH, Sweden
Andr? Martinelli , Royal Institute of Technology, IMIT/KTH, Sweden
pp. 430-431

Uniformly-Switching Logic for Cryptographic Hardware (PDF)

Dmitri Maslov , Univ. of Victoria
Igor L. Markov , Univ. of Michigan
pp. 432-433

Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory (PDF)

Guowu Yang , Portland State University, Oregon
William N. N. Hung , Portland State University, Oregon
Xiaoyu Song , Portland State University, Oregon
Marek Perkowski , Portland State University, Oregon
pp. 434-435
4C: Defect Detection and Characterisation

Memory Testing Under Different Stress Conditions: An Industrial Evaluation (Abstract)

Ananta K. Majhi , Philips Research Laboratory, The Netherlands
Fred Bowen , Philips Semiconductor, San Jose, CA
Mohamed Azimane , Philips Research Laboratory, The Netherlands
Maurice Lousberg , Philips Research Laboratory, The Netherlands
Stefan Eichenberger , Philips Semiconductors, The Netherlands
Guido Gronthoud , Philips Research Laboratory, The Netherlands
pp. 438-443

Worst-Case and Average-Case Analysis of n-Detection Test Sets (Abstract)

Irith Pomeranz , Purdue University, W. Lafayette, IN
Sudhakar M. Reddy , University of Iowa, Iowa City
pp. 444-449

Defect Aware Test Patterns (Abstract)

Gang Chen , University of Iowa, Iowa City
Irith Pomeranz , Purdue Univ., West Lafayette, IN
Huaxing Tang , University of Iowa, Iowa City
Sudhakar M. Reddy , University of Iowa, Iowa City
Chen Wang , Mentor Graphic Corporation, Wilsonville, OR
Janusz Rajski , Mentor Graphic Corporation, Wilsonville, OR
pp. 450-455

Computational Intelligence Characterization Method of Semiconductor Device (Abstract)

Eric Liau , Infineon Technology AG, Munich, Germany
Doris Schmitt-Landsiedel , Technische Universit?t M?nchen, Munich, Germany
pp. 456-461
Interactive Presentations

A New Embedded Measurement Structure for eDRAM Capacitor (PDF)

J. M. Portal , L2MP-Polytech-UMR CNRS, France
D. N? , ST-Microelectronics, France
L. Lopez , L2MP-Polytech-UMR CNRS, France; ST-Microelectronics, France
pp. 462-463

Smart Temperature Sensor for Thermal Testing of Cell-Based ICs (PDF)

S. A. Bota , Universitat de les Illes Balears, Spain
J. Segura , Universitat de les Illes Balears, Spain
J. L. Rossell? , Universitat de les Illes Balears, Spain
M. Rosales , Universitat de les Illes Balears, Spain
pp. 464-465
4E: Real-Time Scheduling

An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor (Abstract)

Jian-Jia Chen , National Taiwan University, Taipei
Chuan-Yue Yang , National Taiwan University, Taipei
Tei-Wei Kuo , National Taiwan University, Taipei
pp. 468-473

Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model (PDF)

Haisang Wu , Virginia Tech, Blacksburg, VA
Binoy Ravindran , Virginia Tech, Blacksburg, VA
E. Douglas Jensen , The MITRE Corporation, Bedford, MA
pp. 474-479

Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies (Abstract)

Rafik Henia , Technical University of Braunschweig, Germany
Rolf Ernst , Technical University of Braunschweig, Germany
pp. 480-485

A New Task Model for Streaming Applications and Its Schedulability Analysis (Abstract)

Samarjit Chakraborty , National University of Singapore
Lothar Thiele , Swiss Federal Institute of Technology (ETH) Z?
pp. 486-491

Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling (Abstract)

Frank Slomka , University of Oldenburg, Germany
Karsten Albers , University of Oldenburg, Germany
pp. 492-497
Interactive Presentation

Unified Modeling of Complex Real-Time Control Systems (PDF)

Cai Chi-lan , Huazhong University of Science & Technology, Wuhan, China
He Hai , Huazhong University of Science & Technology, Wuhan, China
Zhong Yi-fang , Huazhong University of Science & Technology, Wuhan, China
pp. 498-499
4F: SoC Power Optimisation

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique (Abstract)

Igor Reis , PPGCC - FACIN - PUCRS, Brazil
Ney Calazans , PPGCC - FACIN - PUCRS, Brazil
Altamiro Susin , PPGC - II - UFRGS, Brazil
C?sar Marcon , PPGC - II - UFRGS, Brazil
Fernando Moraes , PPGCC - FACIN - PUCRS, Brazil
Fabiano Hessel , PPGCC - FACIN - PUCRS, Brazil
pp. 502-507

Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints (Abstract)

Marcus T. Schmitz , University of Southampton, UK
Bashir M. Al Hashimi , University of Southampton, UK
Alexandru Andrei , Link?ping University, Sweden
Petru Eles , Link?ping University, Sweden
Zebo Peng , Link?ping University, Sweden
pp. 514-519

Tag Overflow Buffering: An Energy-Efficient Cache Architecture (Abstract)

Massimo Poncino , Politecnico di Torino, Italy
Mirko Loghi , Universit? di Verona, Italy
Paolo Azzoni , Universit? di Verona, Italy
pp. 520-525
Interactive Presentations

Q-DPM: An Efficient Model-Free Dynamic Power Management Technique (PDF)

Xiaolang Yan , Institute of VLSI Design, Zhejiang Univ., China
Xiaobo Wu , Institute of VLSI Design, Zhejiang Univ., China
Min Li , Institute of VLSI Design, Zhejiang Univ., China; Microsoft Research Asia
Richard Yao , Microsoft Research Asia
pp. 526-527

Hardware Accelerated Power Estimation (PDF)

Srivaths Ravi , NEC Laboratories America, Princeton, NJ
Anand Raghunathan , NEC Laboratories America, Princeton, NJ
Joel Coburn , NEC Laboratories America, Princeton, NJ
pp. 528-529
4G: Embedded Tutorial - Platforms and Tools for Automotive System Design

A New Approach to Component Testing (PDF)

Horst Brinkmeyer , Ingenieurb?ro Brinkmeyer
pp. 534-535
5A: System Level Languages, Verification and Simulation

Functional Validation of System Level Static Scheduling (Abstract)

Samar Abdi , University of California, Irvine, USA
Daniel Gajski , University of California, Irvine, USA
pp. 542-547

Defining an Enhanced RTL Semantics (Abstract)

Daniel D. Gajski , University of California, Irvine
Shuqing Zhao , University of California, Irvine
pp. 548-553

RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC (Abstract)

Masaharu Imai , Osaka University, Japan
Yoshinori Takeuchi , Osaka University, Japan
M. AbdElSalam Hassan , Osaka University, Japan
Keishi Sakanushi , Osaka University, Japan
pp. 554-559

Design for Verification of SystemC Transaction Level Models (Abstract)

Sofi?ne Tahar , Concordia University, Canada
Ali Habibi , Concordia University, Canada
pp. 560-565
Interactive Presentations

Systematic Transaction Level Modeling of Embedded Systems with SystemC (PDF)

Wolfgang Klingauf , Technical University of Braunschweig, Germany
pp. 566-567

Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures (PDF)

Sohini Dasgupta , University of Newcastle upon Tyne, UK
Alex Yakovlev , University of Newcastle upon Tyne, UK
pp. 568-569
5B: Panel Session - Semiconductor Industry Disaggregation vs. Reaggregation: Who will be the Shark?
5C: Reliable Memory Design

An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories (Abstract)

Jin-Fu Li , National Central University, Taiwan
Chin-Long Wey , National Central University, Taiwan
Tsu-Wei Tseng , National Central University, Taiwan
pp. 574-579

On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories (Abstract)

S. Pontarelli , University of Rome "Tor Vergata", Rome, Italy
L. Schiano , Northeastern University, Boston, MA
F. Lombardi , Northeastern University, Boston, MA
A. Salsano , University of Rome "Tor Vergata", Rome, Italy
M. Ottavi , Northeastern University, Boston, MA
pp. 580-585

Increasing Register File Immunity to Transient Errors (Abstract)

Ozcan Ozturk , Pennsylvania State University
Mahmut T. Kandemir , Pennsylvania State University
Gokhan Memik , Northwestern University
pp. 586-591

An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories (Abstract)

Steven Garverick , Case Western Reserve University, Cleveland, Ohio
Francis Wolff , Case Western Reserve University, Cleveland, Ohio
Michael Nicolaidis , iRoC Technologies, Grenoble, France
Balkaran Gill , Case Western Reserve University, Cleveland, Ohio
Chris Papachristou , Case Western Reserve University, Cleveland, Ohio
pp. 592-597
5E: Execution-Time Analysis

Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software (Abstract)

Peter Marwedel , University of Dortmund, Germany
Lars Wehmeyer , University of Dortmund, Germany
pp. 600-605

Automatic Timing Model Generation by CFG Partitioning and Model Checking (Abstract)

Peter Puschner , Technische Universit?t Wien, Austria
Raimund Kirner , Technische Universit?t Wien, Austria
Ingomar Wenzel , Technische Universit?t Wien, Austria
Bernhard Rieder , Technische Universit?t Wien, Austria
pp. 606-611

A Contribution to Branch Prediction Modeling in WCET Analysis (Abstract)

Christine Rochange , Universit? Paul Sabatier, CNRS, France
Claire Burgui?re , Universit? Paul Sabatier, CNRS, France
pp. 612-617
Interactive Presentations

Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation (PDF)

Christian Ferdinand , AbsInt Angewandte Informatik GmbH, Germany
Reinhold Heckmann , AbsInt Angewandte Informatik GmbH, Germany
pp. 618-619
5F: Battery and Current Considerations in CMOS Design

An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms (Abstract)

Jawad Khan , University of Cincinnati, Ohio
Ranga Vemuri , University of Cincinnati, Ohio
pp. 622-627

Design Method for Constant Power Consumption of Differential Logic Circuits (Abstract)

Kris Tiri , UC Los Angeles
Ingrid Verbauwhede , UC Los Angeles; K.U. Leuven
pp. 628-633

Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling (Abstract)

Chi-Ying Tsui , Hong Kong University of Science and Technology, China
Xiaobo Sharon Hu , University of Notre Dame, IN
Lap-Fai Leung , Hong Kong University of Science and Technology, China
pp. 634-639

Low Power Oriented CMOS Circuit Optimization Protocol (Abstract)

A. Verle , LIRMM, UMR CNRS/Universit? de Montpellier II, France
N. Azemard , LIRMM, UMR CNRS/Universit? de Montpellier II, France
P. Maurine , LIRMM, UMR CNRS/Universit? de Montpellier II, France
D. Auvergne , LIRMM, UMR CNRS/Universit? de Montpellier II, France
X. Michel , LIRMM, UMR CNRS/Universit? de Montpellier II, France
pp. 640-645
Interactive Presentations

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction (PDF)

Katsuhiro Seta , TOSHIBA Corporation Semiconductor Company, Japan
Toshiyuki Furusawa , TOSHIBA Microelectronics Corporation, Japan
Fimihiro Minami , TOSHIBA Corporation Semiconductor Company, Japan
Takeshi Kitahara , TOSHIBA Corporation Semiconductor Company, Japan
Naoyuki Kawabe , TOSHIBA Corporation Semiconductor Company, Japan
pp. 646-647

Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip (PDF)

G. M. Link , The Pennsylvania State University, University Park, PA
N. Vijaykrishnan , The Pennsylvania State University, University Park, PA
pp. 648-649

Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage (PDF)

Trevor Mudge , University of Michigan, Ann Arbor, MI
Tae Ho Kgil , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Nam-Sung Kim , Intel Corporation, Portland, Oregon
Robert Bai , University of Michigan, Ann Arbor, MI
pp. 650-651
5G: Panel Session - Automotive System Architectures
5K: Keynote

Author Index (PDF)

pp. 659A
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