Design, Automation & Test in Europe Conference & Exhibition (2005)
Munich, Germany Germany
Mar. 7, 2005 to Mar. 11, 2005
ISSN: 1530-1591
ISBN: 0-7695-2288-2
TABLE OF CONTENTS
Best Paper Awards [4 awards] (PDF)
pp. xxix
Intro
Technical Program Chairs (PDF)
pp. xvii,xviii
list-reviewer (PDF)
pp. xxiv,xxv,xxvi
Tutorials [10 abstracts] (PDF)
pp. xxx,xxxi,xxxii,xxxiii
A fast concurrent power-thermal model for sub-100 nm digital ICs (Abstract)
J.L. Rossello , Electron. Technol. Group, Univ. de les Illes Baleares, Palma de Mallorca, Spain
V. Canals , Electron. Technol. Group, Univ. de les Illes Baleares, Palma de Mallorca, Spain
S.A. Bota , Electron. Technol. Group, Univ. de les Illes Baleares, Palma de Mallorca, Spain
pp. 206-211 Vol. 1
8B: Interconnect Solutions: Timing, Noise, and Process Variations
Statistical timing analysis with extended pseudo-canonical timing model (Abstract)
pp. 952,953,954,955,956,957
Modeling interconnect variability using efficient parametric model order reduction (Abstract)
Peng Li , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 958,959,960,961,962,963
