The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2004)
Paris, France
Feb. 16, 2004 to Feb. 20, 2004
ISSN: 1530-1591
ISBN: 0-7695-2085-5
TABLE OF CONTENTS
Introduction
2D: Hot Topic — From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions

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pp. null

Systems on Chips Design: System Manufacturer Point of View (PDF)

Veikko Loukusa , Nokia Mobile Phones Ltd.
Helena Pohjonen , Nokia Mobile Phones Ltd.
Antti Ruha , Nokia Mobile Phones Ltd.
Tarmo Ruotsalainen , Nokia Mobile Phones Ltd.
Olli Varkki , Nokia Mobile Phones Ltd.
pp. 30003

IP Testing — The Future Differentiator? (PDF)

Bill Eklow , Cisco Systems Inc.
pp. 30006
3D: Analogue and RF Design

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pp. null

Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs (Abstract)

Ad?o A. S. J?nior , Universidade Federal do Rio Grande do Sul
Luigi Carro , Universidade Federal do Rio Grande do Sul
pp. 30010

Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology (Abstract)

Yiming Chen , IBM Microelectronics Division
Xiaojuen Yuan , IBM Microelectronics Division
David Scagnelli , IBM Microelectronics Division BTV
James Mecke , IBM Microelectronics Division
Jeff Gross , IBM Microelectronics Division BTV
David Harame , IBM Microelectronics Division BTV
pp. 30022
4D: Platform and IP Design

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pp. null

Design of Very Deep Pipelined Multipliers for FPGAs (Abstract)

Alex Panato , Universidade Federal do Rio Grande do Sul
Sandro Silva , Universidade Federal do Rio Grande do Sul
Fl?vio Wagner , Universidade Federal do Rio Grande do Sul
Marcelo Johann , Universidade Federal do Rio Grande do Sul
Ricardo Reis , Universidade Federal do Rio Grande do Sul
Sergio Bampi , Universidade Federal do Rio Grande do Sul
pp. 30052

Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding (Abstract)

Pierre G. Paulin , STMicroelectronics
Chuck Pilkington , STMicroelectronics
Essaid Bensoudane , STMicroelectronics
Michel Langevin , STMicroelectronics
Damien Lyonnard , STMicroelectronics
pp. 30058

Islands of Synchronicity, a Design Methodology for SoC Design (Abstract)

A.P. Niranjan , Philips Semiconductors
Paul Wiscombe , Philips Semiconductors
pp. 30064

The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512) (Abstract)

Luigi Dadda , ALaRI-USI and Politecnico di Milano
Marco Macchetti , Politecnico di Milano
Jeff Owen , ST Microelectronics NV
pp. 30070

LZW-Based Code Compression for VLIW Embedded Systems (Abstract)

Chang Hong Lin , Princeton University
Yuan Xie , Pennsylvania State University
Wayne Wolf , Princeton University
pp. 30076

A Generic RTOS Model for Real-time Systems Simulation with SystemC (Abstract)

R. Le Moigne , University of Nantes
O. Pasquier , University of Nantes
J-P. Calvez , University of Nantes
pp. 30082

A Scalable Architecture for LDPC Decoding (Abstract)

Mauro Cocco , Silicon Hive
John Dielissen , Philips Research
Marc Heijligers , Philips Research
Andries Hekstra , Philips Research
Jos Huisken , Silicon Hive
pp. 30088
5D: Design Verification and Test

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pp. null

Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments (Abstract)

Stephen Schmitt , Eberhard-Karls-University of Tuebingen
Wolfgang Rosenstiel , Eberhard-Karls-University of Tuebingen and Forschungszentrum Informatik
pp. 30096

Formal Refinement and Model Checking of an Echo Cancellation Unit (Abstract)

Alexander Krupp , Paderborn University
Wolfgang Mueller , Paderborn University
Ian Oliver , Nokia Research Center
pp. 30102

Test Infrastructure Design for the Nexperia™ Home Platform PNX8550 System Chip (Abstract)

Sandeep Kumar Goel , Philips Research Laboratories
Kuoshu Chiu , Philips Semiconductors
Erik Jan Marinissen , Philips Research Laboratories
Toan Nguyen , Philips Semiconductors
Steven Oostdijk , Philips Semiconductors
pp. 30108

At-Speed Testing of SOC ICs (Abstract)

Vlado Vorisek , Motorola Munich
Thomas Koch , Motorola Munich
Hermann Fischer , Motorola Munich
pp. 30120

Utilizing Formal Assertions for System Design of Network Processors (Abstract)

Xi Chen , University of California, at Riverside
Yan Luo , University of California, at Riverside
Harry Hsieh , University of California, at Riverside
Laxmi Bhuyan , University of California, at Riverside
Felice Balarin , Cadence Berkeley Laboratories
pp. 30126
6D: Design Methodology

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pp. null

A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses (Abstract)

I. M. Elfadel , IBM T. J. Watson Research Center
A. Deutsch , IBM T. J. Watson Research Center
G. Kopcsay , IBM T. J. Watson Research Center
B. Rubin , IBM T. J. Watson Research Center
H. Smith , IBM Systems Division
pp. 30144

MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators (Abstract)

J. Ruiz-Amaya , Instituto de Microelectr?nica de Sevilla
J.M. de la Rosa , Instituto de Microelectr?nica de Sevilla
F. Medeiro , Instituto de Microelectr?nica de Sevilla
F.V. Fern?ndez , Instituto de Microelectr?nica de Sevilla
R. del R? , Instituto de Microelectr?nica de Sevilla
B. P?rez-Verd? , Instituto de Microelectr?nica de Sevilla
A. Rodr?guez-V?zquez , Instituto de Microelectr?nica de Sevilla
pp. 30150

RTL Processor Synthesis for Architecture Exploration and Implementation (Abstract)

Oliver Schliebusch , Aachen University of Technology
A. Chattopadhyay , Aachen University of Technology
R. Leupers , Aachen University of Technology
G. Ascheid , Aachen University of Technology
H. Meyr , Aachen University of Technology
Mario Steinert , Infineon Technologies
Gunnar Braun , CoWare, Inc.
Achim Nohl , CoWare, Inc.
pp. 30156

Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems (Abstract)

Ankush Varma , University of Maryland at College Park
Shuvra S. Bhattacharyya , University of Maryland at College Park
pp. 30161
7D: Network Design

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pp. null

Heterogeneous Co-Simulation of Networked Embedded Systems (Abstract)

Franco Fummi , Università di Verona
Stefano Martini , Embedded Systems Design Center
Giovanni Perbellini , Embedded Systems Design Center
Massimo Poncino , Università di Verona
Fabio Ricciato , Telecom Italia Lab
Maura Turolla , Telecom Italia Lab
pp. 30168

OCCN: A Network-On-Chip Modeling and Simulation Framework (Abstract)

Marcello Coppola , ST Microelectronics
Stephane Curaba , ST Microelectronics
Miltos D. Grammatikakis , ISD S.A. and TEI-Crete
Giuseppe Maruccia , ST Microelectronics
Francesco Papariello , ST Microelectronics
pp. 30174

Software Processing Performance in Network Processors (Abstract)

I. Papaefstathiou , Foundation of Research & Technology Hellas
G. Kornaros , Ellemedia Technologies
N. Zervos , Ellemedia Technologies
pp. 30186

Channel Decoder Architecture for 3G Mobile Wireless Terminals (Abstract)

Friedbert Berens , STMicroelectronics N.V.
Gerd Kreiselmaier , University of Kaiserslautern
Norbert Wehn , University of Kaiserslautern
pp. 30192

RASoC: A Router Soft-Core for Networks-on-Chip (Abstract)

Cesar Albenes Zeferino , UNIVALI — CTTMar
M?rcio Eduardo Kreutz , UFRGS — II — PPGC
Altamiro Amadeu Susin , UFRGS — II — PPGC
pp. 30198
8D: Reconfigurable Architecture

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pp. null

Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware (Abstract)

A. Cilardo , Università degli Studi di Napoli Federico II
A. Mazzeo , Università degli Studi di Napoli Federico II
L. Romano , Università degli Studi di Napoli Federico II
G. P. Saggese , Università degli Studi di Napoli Federico II
pp. 30206

Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA (Abstract)

Hala Farouk , Arab Academy for Science, Technology & Maritime Transport
Magdy Saeb , Arab Academy for Science, Technology & Maritime Transport
pp. 30212

Customisable EPIC Processor: Architecture and Tools (Abstract)

W.W.S. Chu , Imperial College London
R.G. Dimond , Imperial College London
S. Perrott , Imperial College London
S.P. Seng , Imperial College London
W. Luk , Imperial College London
pp. 30236

A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications (Abstract)

Marcos R. Boschetti , Federal University of Rio Grande do Sul
Ivan S. Silva , Federal University of Rio Grande do Norte
Sergio Bampi , Federal University of Rio Grande do Sul
pp. 30242

Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks (Abstract)

Djones Lettnin , T?bingen University
Axel Braun , T?bingen University
Martin Bodgan , T?bingen University
Joachim Gerlach , T?bingen University
Wolfgang Rosenstiel , T?bingen University
pp. 30248
9D: Constrained and Domain Specific Architectures

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pp. null

Experiences during the Experimental Validation of the Time-Triggered Architecture (Abstract)

S. Blanc , Polytechnic University of Valencia
J. Gracia , Polytechnic University of Valencia
P. J. Gil , Polytechnic University of Valencia
pp. 30256

Evaluation of a Refinement-Driven SystemC™-Based Design Flow (Abstract)

Thorsten Schubert , OFFIS Research Institute
Jürgen Hanisch , Robert Bosch GmbH
Joachim Gerlach , Robert Bosch GmbH
Jens-E. Appell , OFFIS Research Institute
Wolfgang Nebel , OFFIS Research Institute
pp. 30262

The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip (Abstract)

W. J. Bainbridge , University of Manchester
L. A. Plana , University of Manchester
S. B. Furber , University of Manchester
pp. 30274

A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications (Abstract)

Beibei Ren , University of California at Santa Cruz
Anru Wang , University of California at Santa Cruz
Joyopriya Bakshi , University of California at Santa Cruz
Kai Liu , University of California at Santa Cruz
Wei Li , University of California at Santa Cruz
Wayne Dai , University of California at Santa Cruz
pp. 30280

Qualification and Integration of Complex I/O in SoC Design Flows (Abstract)

Jay Abraham , Magma Design Automation
Guruprasad Rao , Magma Design Automation
pp. 30286
10D: Low Power Design

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pp. null

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards (Abstract)

U. Neffe , Graz University of Technology
K. Rothbart , Graz University of Technology
Ch. Steger , Graz University of Technology
R. Weiss , Graz University of Technology
E. Rieger , Philips Semiconductors
A. M?hlberger , Philips Semiconductors
pp. 30300

Analysis and Modeling of Energy Reducing Source Code Transformations (Abstract)

C. Brandolese , Politecnico di Milano
W. Fornaciari , Politecnico di Milano
F. Salice , Politecnico di Milano
D. Sciuto , Politecnico di Milano
pp. 30306

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design (Abstract)

F. Menichelli , University of Rome "La Sapienza"
M. Olivieri , University of Rome "La Sapienza"
L. Benini , University of Bologna
M. Donno , Bulldast s.r.l
L. Bisdounis , Intracom S.A.
pp. 30312

System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip (Abstract)

Andrea Bona , STMicroelectronics
Vittorio Zaccaria , STMicroelectronics
Roberto Zafalon , STMicroelectronics
pp. 30318

IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling (Abstract)

Kriszti? Flautner , ARM Limited
David Flynn , ARM Limited
David Roberts , ARM Limited
Dipesh I. Patel , ARM Limited
pp. 30324
IP2

Can IP Quality be Objectively Measured? (PDF)

Kathy Werner , Mentor Graphics Corporation
pp. 30330

Improving Design and Verification Productivity with VHDL-200x (PDF)

Stephen Bailey , Model Technology, a Mentor Graphics Company
Erich Marschner , Cadence Design Systems
J. Bhasker , eSilicon Corporation
Jim Lewis , SynthWorks
Peter Ashenden , Ashenden Designs Pty Ltd
pp. 30332
IP3

Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components (PDF)

Pierluigi Daglio , STMicroelectronics
David Iezzi , STMicroelectronics
Danilo Rimondi , STMicroelectronics
Carlo Roma , STMicroelectronics
Salvatore Santapa , STMicroelectronics
pp. 30336

VHDL-AMS Library Development for Pacemaker Applications (PDF)

B. Hecker , ELA Medical
M. Chavassieux , ELA Medical
M. Laflutte , ELA Medical
E Beguin , ELA Medical
L. Lagasse , EFREI
J. Oudinot , Mentor Graphics
pp. 30338
IP5

Modeling and Analysis of Heterogeneous Industrial Networks Architectures (PDF)

F. Fummi , Università di Verona
S. Martini , Embedded Systems Design Center
M. Monguzzi , Sitek S.p.A.
G. Perbellini , Embedded Systems Design Center
M. Poncino , Università di Verona
pp. 30342
Author Index

Author Index (PDF)

pp. 30345
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