The Community for Technology Leaders
Design, Automation & Test in Europe Conference & Exhibition (2004)
Paris, France
Feb. 16, 2004 to Feb. 20, 2004
ISSN: 1530-1591
ISBN: 0-7695-2085-5
TABLE OF CONTENTS
6A: Performances Analysis for MPSoC

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pp. null

Analyzing On-Chip Communication in a MPSoC Environment (Abstract)

Mirko Loghi , University of Verona
Federico Angiolini , University of Bologna
Davide Bertozzi , University of Bologna
Luca Benini , University of Bologna
Roberto Zafalon , STMicroelectronics
pp. 20752

A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs (Abstract)

Matthias Gr?newald , University of Paderborn
J?rg-Christian Niemann , University of Paderborn
Mario Porrmann , University of Paderborn
Ulrich R?ckert , University of Paderborn
pp. 20758

Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach (Abstract)

Santiago Gonzalez Pestana , Philips Research Laboratories
Edwin Rijpkema , Philips Research Laboratories
Andrei Rădulescu , Philips Research Laboratories
Kees Goossens , Philips Research Laboratories
Om Prakash Gangwal , Philips Research Laboratories
pp. 20764

A Case Study in Networks-on-Chip Design for Embedded Video (Abstract)

Jiang Xu , Princeton University
Wayne Wolf , Princeton University
Joerg Henkel , NEC Laboratories America, Inc.
Srimat Chakradhar , NEC Laboratories America, Inc.
Tiehan Lv , Princeton University
pp. 20770
6B: Synthesis for Noise and Manufacturability

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pp. null

Exploiting Crosstalk to Speed up On-Chip Buses (Abstract)

Chunjie Duan , Ericsson Wireless Communications
Sunil P. Khatri , University of Colorado at Boulder
pp. 20778

False-Noise Analysis for Domino Circuits (Abstract)

A. Glebov , Microstyle - Moscow
S. Gavrilov , Microstyle - Moscow
V. Zolotov , Motorola, Inc.
Chanhee Oh , Motorola, Inc.
R. Panda , Motorola, Inc.
M. Becer , Motorola, Inc.
pp. 20784

Crosstalk Minimization in Logic Synthesis for PLA (Abstract)

Yi-Yu Liu , Tsing Hua University
Kuo-Hua Wang , Fu Jen Catholic University
TingTing Hwang , Tsing Hua University
pp. 20790

Synthesis for Manufacturability: A Sanity Check (Abstract)

Alessandra Nardi , University of California at Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley
pp. 20796
6C: Support for BIST

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pp. null

Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit (Abstract)

M.A. Abas , University of Newcastle Upon Tyne
G. Russell , University of Newcastle Upon Tyne
D.J. Kinniment , University of Newcastle Upon Tyne
pp. 20804

Impact of Test Point Insertion on Silicon Area and Timing during Layout (Abstract)

Harald Vranken , Philips Research Laboratories
Ferry Syafei Sapei , University of Stuttgart
Hans-Joachim Wunderlich , University of Stuttgart
pp. 20810

Designing Self Test Programs for Embedded DSP Cores (Abstract)

Hani Rizk , Case Western Reserve University
Chris Papachristou , Case Western Reserve University
Francis Wolff , Case Western Reserve University
pp. 20816
6E: Modelling, Simulation and Optimisation in Power/Ground/Substrate

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pp. null

Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction (Abstract)

Zhe Wang , University of Minnesota
Rajeev Murgai , Fujitsu Laboratories of America
Jaijeet Roychowdhury , University of Minnesota
pp. 20824

Thermal and Power Integrity Based Power/Ground Networks Optimization (Abstract)

Ting-Yuan Wang , University of Wisconsin-Madison
Jeng-Liang Tsai , University of Wisconsin-Madison
Charlie Chung-Ping Chen , National Taiwan University
pp. 20830
6F: Panel Session — Chips of the Future: Soft, Crunchy or Hard?

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pp. null
6G: Power-Aware Networks and Interfaces

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pp. null

Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks (Abstract)

I. Kadayif , Canakkale Onsekiz Mart University
M. Kandemir , Pennsylvania State University
pp. 20852

Power-Aware Network Swapping for Wireless Palmtop PCs (Abstract)

Andrea Acquaviva , Università di Urbino
Emanuele Lattanzi , Università di Urbino
Alessandro Bogliolo , Università di Urbino
pp. 20858

Power Aware Interface Synthesis for Bus-Based SoC Designs (Abstract)

Nikolaos D. Liveris , Northwestern University
Prithviraj Banerjee , Northwestern University
pp. 20864

Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones (Abstract)

Alex Branover , Technion-Israel Institute of Technology
Rakefet Kol , Technion-Israel Institute of Technology
Ran Ginosar , Technion-Israel Institute of Technology
pp. 20870
7A: Networks on Chip Design

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pp. null

An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration (Abstract)

Andrei Rădulescu , Philips Research Laboratories
John Dielissen , Philips Research Laboratories
Kees Goossens , Philips Research Laboratories
Edwin Rijpkema , Philips Research Laboratories
Paul Wielage , Philips Research Laboratories
pp. 20878

?pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip (Abstract)

Antoine Jalabert , LETI-DSIS
Srinivasan Murali , Stanford University
Luca Benini , University of Bologna
Giovanni De Micheli , Stanford University
pp. 20884

Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip (Abstract)

Mikael Millberg , Royal Institute of Technology
Erland Nilsson , Royal Institute of Technology
Rikard Thid , Royal Institute of Technology
Axel Jantsch , Royal Institute of Technology
pp. 20890
7B: Advances in Technology Mapping and Circuit Sizing

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pp. null

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies (Abstract)

Rui Zhang , Princeton University
Pallav Gupta , Princeton University
Lin Zhong , Princeton University
Niraj K. Jha , Princeton University
pp. 20904

Fast Comparisons of Circuit Implementations (Abstract)

Shrirang K. Karandikar , University of Minnesota
Sachin S. Sapatnekar , University of Minnesota
pp. 20910

Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs (Abstract)

Anurag Tiwari , University of Cincinnati
Karen A. Tomko , University of Cincinnati
pp. 20916

MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis (Abstract)

Manoj A Kumar , Indian Institute of Technology Madras
Jayaram Bobba , Indian Institute of Technology Madras
V Kamakoti , Indian Institute of Technology Madras
pp. 20922
7C: Panel Session — Nanometer Design — What are the Requirements for Manufacturing Test?

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pp. null

Nanometer Design: What are the Requirements for Manufacturing Test? (Abstract)

Janusz Rajski , Mentor Graphics Corporation
Kan Thapar , Mentor Graphics Corporation
pp. 20930
7E: Issues in Interconnect Simulation and Model Order Reduction

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pp. null

Poor Man?s TBR: A Simple Model Reduction Scheme (Abstract)

Joel Phillips , Cadence Berkeley Laboratories
L. Miguel Silveira , Technical University of Lisbon
pp. 20938

SCORE: SPICE COmpatible Reluctance Extraction (Abstract)

Rong Jiang , University of Wisconsin-Madison
Charlie Chung-Ping Chen , National Taiwan University
pp. 20948

A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk (Abstract)

J. L. Rosselló , Balearic Islands University
J. Segura , Balearic Islands University
pp. 20954
7F: Emerging Technologies: From Sensors to Qubits

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pp. null

A Framework for Battery-Aware Sensor Management (Abstract)

Sridhar Dasika , University of Arizona
Sarma Vrudhula , University of Arizona
Kaviraj Chopra , University of Arizona
R. Srinivasan , University of Arizona
pp. 20962

Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance (Abstract)

Phillip Stanley-Marbell , Carnegie Mellon University
Diana Marculescu , Carnegie Mellon University
pp. 20968

Smaller Two-Qubit Circuits for Quantum Communication and Computation (Abstract)

Vivek V. Shende , University of Michigan
Igor L. Markov , University of Michigan
Stephen S. Bullock , National Institute of Standards and Technology
pp. 20980
7G: Embedded Tutorial — Architectures and Design Techniques for Energy-Efficient Embedded DSP and Multimedia Processing

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pp. null

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing (Abstract)

Ingrid Verbauwhede , University of California at Los Angeles and K.U.Leuven
Patrick Schaumont , University of California at Los Angeles
Bart Kienhuis , Leiden
pp. 20988
8A: Platform-Based Design and VC Reuse Methods

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pp. null

Measurement of IP Qualification Costs and Benefits (Abstract)

Andreas V? , FZI Karlsruhe
Martin Radetzki , sci-worx GmbH
Wolfgang Rosenstiel , FZI Karlsruhe
pp. 20996

Architecture-Level Performance Estimation for IP-Based Embedded Systems (Abstract)

Kyoko Ueda , Osaka University
Keishi Sakanushi , Osaka University
Yoshinori Takeuchi , Osaka University
Masaharu Imai , Osaka University
pp. 21002

Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures (Abstract)

Montek Singh , University of North Carolina
Michael Theobald , Carnegie Mellon University
pp. 21008

Platform Based on Open-Source Cores for Industrial Applications (Abstract)

M. Bolado , University of Cantabria
H. Posadas , University of Cantabria
J. Castillo , University of Cantabria
P. Huerta , University of Cantabria
P. S?nchez , University of Cantabria
C. S?nchez , Design of System on Silicon
H. Fouren , Design of System on Silicon
F. Blasco , Design of System on Silicon
pp. 21014

MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor (Abstract)

Newton Cheung , University of New South Wales
Sri Parameswaran , University of New South Wales
Jörg Henkel , NEC Laboratories America
Jeremy Chan , University of New South Wales
pp. 21020
8B: Real-Time Issues in Embedded Systems

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pp. null

Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications (Abstract)

Paul Pop , Link?ping University
Petru Eles , Link?ping University
Zebo Peng , Link?ping University
Viacheslav Izosimov , Link?ping University
Magnus Hellring , Volvo Technology Corporation
Olof Bridal , Volvo Technology Corporation
pp. 21028

Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches (Abstract)

Yudong Tan , Georgia Institute of Technology
Vincent J. Mooney III , Georgia Institute of Technology
pp. 21034

Workload Characterization Model for Tasks with Variable Execution Demand (Abstract)

Alexander Maxiaguine , Swiss Federal Institute of Technology
Simon Künzli , Swiss Federal Institute of Technology
Lothar Thiele , Swiss Federal Institute of Technology
pp. 21040

Context-Aware Performance Analysis for Efficient Embedded System Design (Abstract)

Marek Jersak , Technische Universität Braunschweig
Rafik Henia , Technische Universität Braunschweig
Rolf Ernst , Technische Universität Braunschweig
pp. 21046

Compact Binaries with Code Compression in a Software Dynamic Translator (Abstract)

Stacey Shogan , University of Pittsburgh
Bruce R. Childers , University of Pittsburgh
pp. 21052
8C: Real-Life Defect Modelling and Detection

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pp. null

Pattern Selection for Testing of Deep Sub-Micron Timing Defects (Abstract)

Mango , University of California at Santa Barbara
C.-T. Chao , University of California at Santa Barbara
Li-C. Wang , University of California at Santa Barbara
Kwang-Ting Cheng , University of California at Santa Barbara
pp. 2160

Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects (Abstract)

Jennifer Dworak , Texas A&M University
Brad Cobb , Texas A&M University
James Wingfield , Texas A&M University
M. Ray Mercer , Texas A&M University
pp. 21066

Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis (Abstract)

Yu Huang , Mentor Graphics Corporation
Wu-Tung Cheng , Mentor Graphics Corporation
Cheng-Ju Hsieh , Faraday Technology Corporation
Huan-Yung Tseng , Faraday Technology Corporation
Alou Huang , Faraday Technology Corporation
Yu-Ting Hung , Faraday Technology Corporation
pp. 21072

Soft Faults and the Importance of Stresses in Memory Testing (Abstract)

Zaid Al-Ars , Delft University of Technology
Ad J. van de Goor , Delft University of Technology
pp. 21084
8E: Optimisation in Physical Design

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pp. null

Wire Retiming for System-on-Chip by Fixpoint Computation (Abstract)

Chuan Lin , Northwestern University
Hai Zhou , Northwestern University
pp. 21092

Boosting: Min-Cut Placement with Improved Signal Delay (Abstract)

Andrew B. Kahng , University of California at San Diego
Igor L. Markov , University of Michigan
Sherief Reda , University of California at San Diego
pp. 21098

Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus (Abstract)

Liang Deng , University of Illinois at Urbana-Champaign
Martin D. F. Wong , University of Illinois at Urbana-Champaign
pp. 21104

A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk (Abstract)

Suvodeep Gupta , University of South Florida
Srinivas Katkoori , University of South Florida
pp. 21110

Full-Chip Multilevel Routing for Power and Signal Integrity (Abstract)

Jinjun Xiong , University of California at Los Angeles
Lei He , University of California at Los Angeles
pp. 21116
8G: Hot Topic — Platforms and Tools for Energy-Efficient Design of Multimedia Systems

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pp. null

Energy-Aware System Design for Wireless Multimedia (Abstract)

Hans Van Antwerpen , Phillips Semiconductors
Nikil Dutt , University of California at Irvine
Rajesh Gupta , University of California at San Diego
Shivajit Mohapatra , University of California at Irvine
Cristiano Pereira , University of California at San Diego
Nalini Venkatasubramanian , University of California at Irvine
Ralph von Vignau , Phillips Semiconductors
pp. 21124
9A: Communication Design for MPSoC

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pp. null

An Interconnect Channel Design Methodology for High Performance Integrated Circuits (Abstract)

Vikas Chandra , Carnegie Mellon University
Anthony Xu , Carnegie Mellon University
Herman Schmit , Carnegie Mellon University
Larry Pileggi , Carnegie Mellon University
pp. 21138

Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach (Abstract)

Alex Bobrek , Carnegie Mellon University
Joshua J. Pieper , Carnegie Mellon University
Jeffrey E. Nelson , Carnegie Mellon University
JoAnn M. Paul , Carnegie Mellon University
Donald E. Thomas , Carnegie Mellon University
pp. 21144

Supporting Cache Coherence in Heterogeneous Multiprocessor Systems (Abstract)

Taeweon Suh , Georgia Institute of Technology
Douglas M. Blough , Georgia Institute of Technology
Hsien-Hsin S. Lee , Georgia Institute of Technology
pp. 21150
9B: Combining Static and Dynamic Software Optimisation

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pp. null

Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors (Abstract)

I. Kadayif , Canakkale Onsekiz Mart University
M. Kandemir , Pennsylvania State University
I. Kolcu , UMIST
pp. 21158

Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications (Abstract)

Claudio Pinello , University of California at Berkeley
Luca P. Carloni , University of California at Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California at Berkeley
pp. 21164

Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks (Abstract)

Luis Alejandro Cortés , Linköping University
Petru Eles , Linköping University
Zebo Peng , Linköping University
pp. 21176
9C: Hot Topic — The Status of the New IEEE Test Standards

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pp. null

Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 (Abstract)

Steve Sunter , LogicVision
Adam Cron , Synopsys
Neil Jacobson , Xilinx
Dave Bonnett , ASSET-InterTech
Bill Eklow , Cisco
Carl Barnhart , Cadence
Ben Bennetts , Bennetts Associates
pp. 21184
9E: Modelling and Estimation in Circuit Layout

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pp. null

Eliminating False Positives in Crosstalk Noise Analysis (Abstract)

Yajun Ran , University of California at Santa Barbara
Alex Kondratyev , Cadence Berkeley Labs
Yosinori Watanabe , Cadence Berkeley Labs
Malgorzata Marek-Sadowska , University of California at Santa Barbara
pp. 21192

A New Approach to Timing Analysis Using Event Propagation and Temporal Logic (Abstract)

Arijit Mondal , Indian Institute of Technology at Kharagpur
Partha. P. Chakrabarti , Indian Institute of Technology at Kharagpur
C. R. Mandal , Indian Institute of Technology at Kharagpur
pp. 21198

A New Effective Congestion Model in Floorplan Design (Abstract)

Yi-Lin Hsieh , Chung Yuan Christian University
Tsai-Ming Hsieh , Chung Yuan Christian University
pp. 21204

ULSI Interconnect Length Distribution Model Considering Core Utilization (Abstract)

Hidenari Nakashima , Tokyo Institute of Technology
Junpei Inoue , Tokyo Institute of Technology
Kenichi Okada , Tokyo Institute of Technology
Kazuya Masu , Tokyo Institute of Technology
pp. 21210
9G: Applications of Reconfigurability

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pp. null

Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform (Abstract)

Alberto La Rosa , Politecnico di Torino
Claudio Passerone , Politecnico di Torino
Francesco Gregoretti , Politecnico di Torino
Luciano Lavagno , Politecnico di Torino
pp. 21218

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study (Abstract)

Bingfeng Mei , IMEC vzw and Katholieke Universiteit Leuven
Serge Vernalde , IMEC vzw
Diederik Verkest , IMEC vzw, Katholieke Universiteit Leuven and Vrije Universiteit Brussel
Rudy Lauwereins , IMEC vzw and Katholieke Universiteit Leuven
pp. 21224

Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays (Abstract)

Sami Khawam , University of Edinburgh
Sajid Baloch , The Alba Centre
Arjun Pai , The Alba Centre
Imran Ahmed , The Alba Centre
Nizamettin Aydin , University of Edinburgh
Tughrul Arslan , University of Edinburgh and The Alba Centre
Fred Westall , EPSON Scotland Design Centre
pp. 21230
10A: Interconnect Modelling for MPSoC

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pp. null

A Power and Performance Model for Network-on-Chip Architectures (Abstract)

Nilanjan Banerjee , Arizona State University
Praveen Vellanki , Arizona State University
Karam S. Chatha , Arizona State University
pp. 21250

A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms (Abstract)

Andreas Wieferink , Aachen University of Technology
Tim Kogel , Aachen University of Technology
Rainer Leupers , Aachen University of Technology
Gerd Ascheid , Aachen University of Technology
Heinrich Meyr , Aachen University of Technology
Gunnar Braun , CoWare, Inc.
Achim Nohl , CoWare, Inc.
pp. 21256
10B: Embedded Software Generation and Optimisation

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pp. null

Cache-Aware Scratchpad Allocation Algorithm (Abstract)

Manish Verma , University of Dortmund
Lars Wehmeyer , University of Dortmund
Peter Marwedel , University of Dortmund
pp. 21264

Phase Coupled Code Generation for DSPs Using a Genetic Algorithm (Abstract)

Markus Lorenz , University of Dortmund
Peter Marwedel , University of Dortmund
pp. 21270

A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models (Abstract)

Manuel Hohenauer , Aachen University of Technology
Hanno Scharwaechter , Aachen University of Technology
Kingshuk Karuri , Aachen University of Technology
Oliver Wahlen , Aachen University of Technology
Tim Kogel , Aachen University of Technology
Rainer Leupers , Aachen University of Technology
Gerd Ascheid , Aachen University of Technology
Heinrich Meyr , Aachen University of Technology
Gunnar Braun , CoWare, Inc.
Hans van Someren , Associated Compiler Experts bv
pp. 21276
10C: Scan-Based Testing

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pp. null

CircularScan: A Scan Architecture for Test Cost Reduction (Abstract)

Baris Arslan , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 21290

Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes (Abstract)

A. Leininger , Infineon Technologies AG
M. Goessel , University of Potsdam
P. Muhmenthaler , Infineon Technologies AG
pp. 21302
10E: Novel Approaches to Analogue Simulation

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pp. null

Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation (Abstract)

Bo Wan , University of Washington
C.-J. Richard Shi , University of Washington
pp. 21310

Direct Nonlinear Order Reduction with Variational Analysis (Abstract)

Lihong Feng , Fudan University
Xuan Zeng , Fudan University
Charles Chiang , Synopsys Inc.
Dian Zhou , Fudan University and University of Texas at Dallas
Qiang Fang , Chinese Academy of Science
pp. 21316

Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method (Abstract)

Xin Zhou , University of Texas at Dallas
Dian Zhou , University of Texas at Dallas
Jin Liu , University of Texas at Dallas
Ruiming Li , University of Texas at Dallas
Xuan Zeng , Fudan University
Charles Chiang , Synopsys Inc.
pp. 21322

Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits (Abstract)

Takashi Mine , Shizuoka University
Hidemasa Kubota , Shizuoka University
Atsushi Kamo , Sony LSI Design Inc.
Takayuki Watanabe , University of Shizuoka
Hideki Asai , Shizuoka University
pp. 21327
10F: Embedded Tutorial — System Verilog for VHDL Users

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pp. null

System Verilog for VHDL Users (Abstract)

Tom Fitzpatrick , Synopsys, Inc.
pp. 21334
10G: Hot Topic — Quo Vadis Multimedia? From Desktop Multimedia to Distributed Multimedia Systems

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pp. null

Distributed Multimedia System Design: A Holistic Perspective (Abstract)

Radu Marculescu , Carnegie Mellon University
Massoud Pedram , University of Southern California
Joerg Henkel , NEC USA
pp. 21342
IP4: Interactive Presentations

Adaptive Prefetching for Multimedia Applications in Embedded Systems (PDF)

Hassan Sbeyti , University of Valenciennes
Smail Niar , University of Valenciennes
Lieven Eeckhout , Ghent University
pp. 21350

Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases (PDF)

Jayaprakash Pisharath , Northwestern University
Alok Choudhary , Northwestern University
Mahmut Kandemir , Pennsylvania State University
pp. 21352

High-Performance QuIDD-Based Simulation of Quantum Circuits (PDF)

George F. Viamontes , University of Michigan
Igor L. Markov , University of Michigan
John P. Hayes , University of Michigan
pp. 21354

An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation (PDF)

D. K. Reed , University of Pittsburgh
S. P. Levitan , University of Pittsburgh
J. Boles , University of Pittsburgh
J. A. Martinez , University of Pittsburgh
D. M. Chiarulli , University of Pittsburgh
pp. 21356

Fault Tolerance of Programmable Switch Blocks (PDF)

J. Huang , Northeastern University
M. B. Tahoori , Northeastern University
F. Lombardi , Northeastern University
pp. 21358

A New Self-Checking Sum-Bit Duplicated Carry-Select Adder (PDF)

E. S. Sogomonyan , University of Potsdam
D. Marienfeld , University of Potsdam
V. Ocheretnij , University of Potsdam
M. G?ssel , University of Potsdam
pp. 21360

A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation (PDF)

Luis Elvira , Universitat Polit?cnica de Catalunya
Ferran Martorell , Universitat Polit?cnica de Catalunya
Xavier Aragon? , Universitat Polit?cnica de Catalunya
Jos? Luis Gonz?lez , Universitat Polit?cnica de Catalunya
pp. 21362

Accurate Estimation of Parasitic Capacitances in Analog Circuits (PDF)

Anuradha Agarwal , University of Cincinnati
Hemanth Sampath , University of Cincinnati
Veena Yelamanchili , University of Cincinnati
Ranga Vemuri , University of Cincinnati
pp. 21364

GRAAL — A Development Framework for Embedded Graphics Accelerators (PDF)

D. Crisu , Delft University of Technology
S.D. Cotofana , Delft University of Technology
S. Vassiliadis , Delft University of Technology
P. Liuha , Nokia Research Center
pp. 21366

From Synchronous to Asynchronous: An Automatic Approach (PDF)

J. Cortadella , University Politècnica de Catalunya
A. Kondratyev , Cadence Berkeley Labs
L. Lavagno , Politecnico di Torino
K. Lwin , Cadence Berkeley Labs
C. Sotiriou , ICS-FORTH
pp. 21368

Minimization of Crosstalk Noise, Delay and Power Using a Modi.ed Bus Invert Technique (PDF)

Matheos Lampropoulos , University of Southampton
Bashir M. Al-Hashimi , University of Southampton
Paul Rosinger , University of Southampton
pp. 21372

Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors (PDF)

Juan Luis Aragon , University of California at Irvine
Dan Nicolaescu , University of California at Irvine
Alex Veidenbaum , University of California at Irvine
Ana-Maria Badulescu , University of California at Irvine
pp. 21374

Dynamic Voltage and Cache Reconfiguration for Low Power (PDF)

Andre C. Nacul , University of California at Irvine
Tony Givargis , University of California at Irvine
pp. 21376
IP5: Interactive Presentations

Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models (PDF)

Maziar Goudarzi , Sharif University of Technology and University of Cambridge
Shaahin Hessabi , Sharif University of Technology
Alan Mycroft , University of Cambridge
pp. 21380

Synthesis of Reversible Logic (PDF)

Abhinav Agrawal , Princeton University
Niraj K. Jha , Princeton University
pp. 21384

A Unified Design Space for Regular Parallel Prefix Adders (PDF)

Matthew M. Ziegler , University of Virginia
Mircea R. Stan , University of Virginia
pp. 21386

Issues in Implementing Latency Insensitive Protocols (PDF)

Mario R. Casu , Politecnico di Torino
Luca Macchiarulo , Politecnico di Torino
pp. 21390

Profile Guided Management of Code Partitions for Embedded Systems (PDF)

Shukang Zhou , University of Pittsburgh
Bruce R. Childers , University of Pittsburgh
Naveen Kumar , University of Pittsburgh
pp. 21396
IP6: Interactive Presentations

Realizable Reduction for Electromagnetically Coupled RLMC Interconnects (PDF)

Rong Jiang , University of Wisconsin—Madison
Charlie Chung-Ping Chen , National Taiwan University
pp. 21400

Statistically Aware Buffer Planning (PDF)

Giuseppe S. Garcea , Delft University of Technology
Nick P. van der Meijs , Delft University of Technology
Kees-Jan van der Kolk , Delft University of Technology
Ralph H. J. M. Otten , Eindhoven University of Technology
pp. 21402

A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology (PDF)

S. Bernardini , L2MP-Polytech — IMT Technopôle de Ch?teau Gombert
J.M. Portal , L2MP-Polytech — IMT Technopôle de Ch?teau Gombert
P. Masson , L2MP-Polytech — IMT Technopôle de Ch?teau Gombert
pp. 21404

Power Supply Noise Monitor for Signal Integrity Faults (PDF)

Josep Rius V?zquez , Universitat Polit?cnica de Catalunya
Jos? Pineda de Gyvez , Philips Research Laboratories
pp. 21406

Testing of Quantum Dot Cellular Automata Based Designs (PDF)

Mehdi Baradaran Tahoori , Northeastern University
Fabrizio Lombardi , Northeastern University
pp. 21408

Net and Pin Distribution for 3D Package Global Routing (PDF)

Jacob R. Minz , Georgia Institute of Technology
Mohit Pathak , Georgia Institute of Technology
Sung Kyu Lim , Georgia Institute of Technology
pp. 21410

Placement Using a Localization Probability Model (LPM) (PDF)

Markus Olbrich , Institute of Microelectronic Systems
Erich Barke , Institute of Microelectronic Systems
pp. 21412

CMOS Structures Suitable for Secured Hardware (PDF)

Sylvain Guilley , GET/Télécom Paris, CNRS LTCI
Philippe Hoogvorst , GET/Télécom Paris, CNRS LTCI
Yves Mathieu , GET/Télécom Paris, CNRS LTCI
Renaud Pacalet , GET/Télécom Paris, CNRS LTCI
Jean Provost , GET/Télécom Paris, CNRS LTCI
pp. 21414

Timing Correction and Optimization with Adaptive Delay Sequential Elements (PDF)

Kambiz Rahimi , University of Washington
Seth Bridges , University of Washington
Chris Diorio , University of Washington
pp. 21416
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