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Design, Automation & Test in Europe Conference & Exhibition (2004)
Paris, France
Feb. 16, 2004 to Feb. 20, 2004
ISSN: 1530-1591
ISBN: 0-7695-2085-5
pp: 21414
Renaud Pacalet , GET/Télécom Paris, CNRS LTCI
Yves Mathieu , GET/Télécom Paris, CNRS LTCI
Jean Provost , GET/Télécom Paris, CNRS LTCI
Sylvain Guilley , GET/Télécom Paris, CNRS LTCI
Philippe Hoogvorst , GET/Télécom Paris, CNRS LTCI
Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
Renaud Pacalet, Yves Mathieu, Jean Provost, Sylvain Guilley, Philippe Hoogvorst, "CMOS Structures Suitable for Secured Hardware", Design, Automation & Test in Europe Conference & Exhibition, vol. 02, no. , pp. 21414, 2004, doi:10.1109/DATE.2004.1269113
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